January 2014 - aarch64-port-dev

hg: aarch64-port/jdk8/hotspot: - Add fix spotted by Andrew Dinn to do cbnzw instead of cbnz in casw
by ed＠camswl.com 27 Jan '14

27 Jan '14

Changeset: 813458fe14ee Author: Edward Nevill edward.nevill(a)linaro.org Date: 2014-01-22 16:29 +0000 URL: http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/813458fe14ee - Add fix spotted by Andrew Dinn to do cbnzw instead of cbnz in casw - Use temp reg in emit_compare_and_swap to avoid corrupting cmpval - Minor tweak to use 2 arg vsn of encode_heap_oop ! src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp

3 3

hg: aarch64-port/jdk8/hotspot: 7 new changesets
by aph＠redhat.com 27 Jan '14

27 Jan '14

Changeset: 1f2d6153f6c1 Author: aph Date: 2014-01-24 12:18 -0500 URL: http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/1f2d6153f6c1 C1: Don't use high parts of registers in arraycopy. ! src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Changeset: ac1555087762 Author: aph Date: 2014-01-24 12:19 -0500 URL: http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/ac1555087762 Floats are not saved as doubles on AArch64. ! src/cpu/aarch64/vm/c1_Defs_aarch64.hpp Changeset: e8ce2c3b62bf Author: aph Date: 2014-01-24 12:23 -0500 URL: http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/e8ce2c3b62bf Debug code for deoptimization. ! src/share/vm/code/nmethod.hpp ! src/share/vm/runtime/deoptimization.cpp ! src/share/vm/runtime/stackValue.cpp ! src/share/vm/runtime/stackValue.hpp ! src/share/vm/runtime/vframeArray.cpp Changeset: 21a221e4a843 Author: aph Date: 2014-01-24 12:23 -0500 URL: http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/21a221e4a843 Debug code for fault handling. ! src/os_cpu/linux_aarch64/vm/os_linux_aarch64.cpp Changeset: 724d72ce083b Author: aph Date: 2014-01-24 12:25 -0500 URL: http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/724d72ce083b Backout 6514 ! src/share/vm/code/nmethod.hpp ! src/share/vm/runtime/deoptimization.cpp ! src/share/vm/runtime/stackValue.cpp ! src/share/vm/runtime/stackValue.hpp ! src/share/vm/runtime/vframeArray.cpp Changeset: 885d42813832 Author: aph Date: 2014-01-25 04:50 -0500 URL: http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/885d42813832 Backout 6515 ! src/os_cpu/linux_aarch64/vm/os_linux_aarch64.cpp Changeset: 29b33e434551 Author: aph Date: 2014-01-27 11:08 +0000 URL: http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/29b33e434551 Merge

1 0

Floats are not saved as doubles on AArch64
by Andrew Haley 27 Jan '14

27 Jan '14

Another fix for deoptimization. Without this patch, floats are not correctly saved and restored when deoptimizing at a call site. Andrew. # HG changeset patch # User aph # Date 1390583978 18000 # Fri Jan 24 12:19:38 2014 -0500 # Node ID ac15550877624b9df2ada9b7c653deffd812aed6 # Parent 1f2d6153f6c1d2cb2c3445808be069159984d968 Floats are not saved as doubles on AArch64. diff -r 1f2d6153f6c1 -r ac1555087762 src/cpu/aarch64/vm/c1_Defs_aarch64.hpp --- a/src/cpu/aarch64/vm/c1_Defs_aarch64.hpp Fri Jan 24 12:18:52 2014 -0500 +++ b/src/cpu/aarch64/vm/c1_Defs_aarch64.hpp Fri Jan 24 12:19:38 2014 -0500 @@ -72,9 +72,11 @@ }; -// encoding of float value in debug info: +// Encoding of float value in debug info. This is true on x86 where +// floats are extended to doubles when stored in the stack, false for +// AArch64 where floats and doubles are stored in their native form. enum { - pd_float_saved_as_double = true + pd_float_saved_as_double = false }; #endif // CPU_AARCH64_VM_C1_DEFS_AARCH64_HPP

1 0

C1: Don't use high parts of registers in arraycopy
by Andrew Haley 27 Jan '14

27 Jan '14

This patch cleans up LIR_Assembler::emit_arraycopy so that it is not affected by garbage in the high parts of 64-bit registers. There was a comment at the start of emit_arraycopy: "length and pos's are all sign extended at this point on 64bit" This comment is not quite right. Let's say a method is deoptimized at a call site. Its outgoing arguments are in registers, as per the Java calling convention. Deoptimization copies these arguments to the stack, as per the interpreter calling convention, but it destroys the upper half of all 32-bit registers. These then get passed to a C1-compiled method, which calls arraycopy, and boom. Andrew. # HG changeset patch # User aph # Date 1390583932 18000 # Fri Jan 24 12:18:52 2014 -0500 # Node ID 1f2d6153f6c1d2cb2c3445808be069159984d968 # Parent 1e2c91a63fc3019b4958ae443ba66d6862e8e19f C1: Don't use high parts of registers in arraycopy. diff -r 1e2c91a63fc3 -r 1f2d6153f6c1 src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp --- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Thu Jan 23 11:43:53 2014 -0500 +++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Fri Jan 24 12:18:52 2014 -0500 @@ -2267,8 +2267,6 @@ Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); - // length and pos's are all sign extended at this point on 64bit - // test for NULL if (flags & LIR_OpArrayCopy::src_null_check) { __ cbz(src, *stub->entry()); @@ -2287,31 +2285,31 @@ __ br(Assembler::LT, *stub->entry()); } + if (flags & LIR_OpArrayCopy::length_positive_check) { + __ cmpw(length, 0); + __ br(Assembler::LT, *stub->entry()); + } + if (flags & LIR_OpArrayCopy::src_range_check) { - __ lea(tmp, Address(src_pos, length)); + __ addw(tmp, src_pos, length); __ ldrw(rscratch1, src_length_addr); __ cmpw(tmp, rscratch1); __ br(Assembler::HI, *stub->entry()); } if (flags & LIR_OpArrayCopy::dst_range_check) { - __ lea(tmp, Address(dst_pos, length)); + __ addw(tmp, dst_pos, length); __ ldrw(rscratch1, dst_length_addr); __ cmpw(tmp, rscratch1); __ br(Assembler::HI, *stub->entry()); } - if (flags & LIR_OpArrayCopy::length_positive_check) { - __ cmpw(length, 0); - __ br(Assembler::LT, *stub->entry()); - } - // FIXME: The logic in LIRGenerator::arraycopy_helper clears // length_positive_check if the source of our length operand is an // arraylength. However, that arraylength might be zero, and the // stub that we're about to call contains an assertion that count != // 0 . So we make this check purely in order not to trigger an // assertion failure. - __ cbz(length, *stub->continuation()); + __ cbzw(length, *stub->continuation()); if (flags & LIR_OpArrayCopy::type_check) { // We don't know the array types are compatible @@ -2384,15 +2382,13 @@ __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); __ str(src, Address(sp, 4*BytesPerWord)); - __ uxtw(length, length); // FIXME ?? higher 32bits must be null - __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale))); __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); assert_different_registers(c_rarg0, dst, dst_pos, length); __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); assert_different_registers(c_rarg1, dst, length); - __ mov(c_rarg2, length); + __ uxtw(c_rarg2, length); assert_different_registers(c_rarg2, dst); __ load_klass(c_rarg4, dst); @@ -2503,7 +2499,7 @@ __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); assert_different_registers(c_rarg1, dst, length); - __ mov(c_rarg2, length); + __ uxtw(c_rarg2, length); assert_different_registers(c_rarg2, dst); bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;

1 0

SPECjvm2008 derby gives SIGBUS with -XX:+TieredCompilation
by Edward Nevill 25 Jan '14

25 Jan '14

Hi, On the RTSM model I get a SIGBUS from the 'derby' benchmark in SPECjvm2008 running -XX:+TieredCompilation. This seems to be 100% reproducible on the RTSM model but I cannot reproduce it on the builtin sim. My version of java is ~/SPECjvm2008$ /home/ed/images/j2sdk-server-fastdebug/bin/java -version openjdk version "1.8.0-internal-fastdebug" OpenJDK Runtime Environment (build 1.8.0-internal-fastdebug-ed_2014_01_07_17_03-b00) OpenJDK 64-Bit Server VM (build 25.0-b59-fastdebug, mixed mode) The command I use is /home/ed/images/j2sdk-server-fastdebug/bin/java -XX:+TieredCompilation -jar SPECjvm2008.jar -ikv derby This seems to run reliably if I use -bt 1 (ie to run the benchmark in 1 thread instead of the default of 8). The following is a sample output from the test. # # A fatal error has been detected by the Java Runtime Environment: # # SIGBUS (0x7) at pc=0x0000007f852c31a4, pid=2180, tid=547367154160 # # JRE version: OpenJDK Runtime Environment (8.0) (build 1.8.0-internal-fastdebug-ed_2014_01_07_17_03-b00) # Java VM: OpenJDK 64-Bit Server VM (25.0-b59-fastdebug mixed mode linux-aarch64 compressed oops) # Problematic frame: # J 4055 C1 java.util.concurrent.locks.AbstractQueuedSynchronizer.addWaiter(Ljava/util/concurrent/locks/AbstractQueuedSynchronizer$Node;)Ljava/util/concurrent/locks/AbstractQueuedSynchronizer$Node; (50 bytes) @ 0x0000007f852c31a4 [0x0000007f852c2f20+0x284] # # Failed to write core dump. Core dumps have been disabled. To enable core dumping, try "ulimit -c unlimited" before starting Java again # # An error report file with more information is saved as: # /home/ed/SPECjvm2008/hs_err_pid2180.log # # If you would like to submit a bug report, please visit: # http://bugreport.sun.com/bugreport/crash.jsp # Current thread is 547367154160 Dumping core ... LOOPING... [thread 547373445616 also had an error] [thread 547377639920 also had an error] All the best, Ed.

5 9

hg: aarch64-port/jdk8/hotspot: Remove bogus AARCH64 conditionalisation around some SSE code
by ed＠camswl.com 24 Jan '14

24 Jan '14

Changeset: 917f6620f8e3 Author: Edward Nevill edward.nevill(a)linaro.org Date: 2014-01-24 10:33 +0000 URL: http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/917f6620f8e3 Remove bogus AARCH64 conditionalisation around some SSE code ! src/share/vm/c1/c1_LIRAssembler.cpp

1 0

hg: aarch64-port/jdk8/hotspot: Fix code that jumps from interpreter to OSR method.
by aph＠redhat.com 23 Jan '14

23 Jan '14

Changeset: 1e2c91a63fc3 Author: aph Date: 2014-01-23 11:43 -0500 URL: http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/1e2c91a63fc3 Fix code that jumps from interpreter to OSR method. ! src/cpu/aarch64/vm/templateTable_aarch64.cpp

1 0

Fix code that jumps from interpreter to OSR method.
by Andrew Haley 23 Jan '14

23 Jan '14

We've been getting occasional bus errors when compiling. The problem is that the OSR code does not correctly pop the interpreter frame. Two things are wrong: firstly, the stack pointer isn't aligned when it returns, which is the cause of the bus error. Secondly, the nmethod is saved in rmethod (AKA r12) around the call to SharedRuntime::OSR_migration_begin, but r12 is a call-clobbered register. Andrew. # HG changeset patch # User aph # Date 1390495433 18000 # Thu Jan 23 11:43:53 2014 -0500 # Node ID 1e2c91a63fc3019b4958ae443ba66d6862e8e19f # Parent 813458fe14eeb9da65e68a12abb85ae1343b2b2d Fix code that jumps from interpreter to OSR method. diff -r 813458fe14ee -r 1e2c91a63fc3 src/cpu/aarch64/vm/templateTable_aarch64.cpp --- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp Wed Jan 22 16:29:43 2014 +0000 +++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp Thu Jan 23 11:43:53 2014 -0500 @@ -1759,26 +1759,24 @@ // We need to prepare to execute the OSR method. First we must // migrate the locals and monitors off of the stack. - __ mov(rmethod, r0); // save the nmethod + __ mov(r19, r0); // save the nmethod call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::OSR_migration_begin)); // r0 is OSR buffer, move it to expected parameter location __ mov(j_rarg0, r0); - // We use j_rarg definitions here so that registers don't conflict as parameter - // registers change across platforms as we are in the midst of a calling - // sequence to the OSR nmethod and we don't want collision. These are NOT parameters. - - // const Register retaddr = j_rarg2; - const Register sender_sp = j_rarg1; - - // pop the interpreter frame - __ ldr(sender_sp, Address(rfp, frame::interpreter_frame_sender_sp_offset * wordSize)); // get sender sp - __ leave(); // remove frame anchor (leaves return address in lr) - __ mov(sp, sender_sp); // set sp to sender sp + // remove activation + // get sender esp + __ ldr(esp, + Address(rfp, frame::interpreter_frame_sender_sp_offset * wordSize)); + // remove frame anchor + __ leave(); + // Ensure compiled code always sees stack at proper alignment + __ andr(sp, esp, -16); + // and begin the OSR nmethod - __ ldr(rscratch1, Address(rmethod, nmethod::osr_entry_point_offset())); + __ ldr(rscratch1, Address(r19, nmethod::osr_entry_point_offset())); __ br(rscratch1); } }

1 0

RFR: Remove bogus conditionalisation around some SSE code
by Edward Nevill 23 Jan '14

23 Jan '14

Hi, I am seeing the following error in jtreg test compiler/6855215/Test6855215.java # Internal Error (c1_LIRAssembler_aarch64.cpp:149), pid=30625, tid=547389162000 # Error: Unimplemented() Line 149 of c1_LIRAssembler_aarch64.cpp says void LIR_Assembler::ffree(int i) { Unimplemented(); } It is called from the following in c1_LIRAssembler.cpp #if (defined(X86) || defined(AARCH64)) && defined(TIERED) // C2 leave fpu stack dirty clean it if (UseSSE < 2) { int i; for ( i = 1; i <= 7 ; i++ ) { ffree(i); } if (!op->result_opr()->is_float_kind()) { ffree(0); } } #endif // X86 && TIERED This is obviously bogus. Fixed as follows. Regards, Ed. --- CUT HERE --- exporting patch: # HG changeset patch # User Edward Nevill edward.nevill(a)linaro.org # Date 1390469953 0 # Thu Jan 23 09:39:13 2014 +0000 # Node ID a5eb93bd3d45a88752b784c88047559504d42ba1 # Parent 813458fe14eeb9da65e68a12abb85ae1343b2b2d Remove bogus AARCH64 conditionalisation around some SSE code diff -r 813458fe14ee -r a5eb93bd3d45 src/share/vm/c1/c1_LIRAssembler.cpp --- a/src/share/vm/c1/c1_LIRAssembler.cpp Wed Jan 22 16:29:43 2014 +0000 +++ b/src/share/vm/c1/c1_LIRAssembler.cpp Thu Jan 23 09:39:13 2014 +0000 @@ -495,7 +495,7 @@ compilation()->set_has_method_handle_invokes(true); } -#if (defined(X86) || defined(AARCH64)) && defined(TIERED) +#if defined(X86) && defined(TIERED) // C2 leave fpu stack dirty clean it if (UseSSE < 2) { int i; --- CUT HERE ---

1 0

Patch to fix SEGV/SIGBUS in client with +CompressedOops
by Edward Nevill 22 Jan '14

22 Jan '14

Hi, The following patch fixes a problem in the client compiler whereby the cmpval in emit_compare_and_swap was being encoded as a compressed oop while still live. This variously resulted in a SIGBUS or SIGSEGV depending on whether the resultant compressed oop was aligned or not. The patch uses a temp to encode the oop. I have also incorporation a fix to the problem spotted by Andrew Dinn whereby casw did a cbnz rather than a cbnzw on a compressed oop. There is also a minor tweak to use the two arg version of encode_heap_oop(dest, src) instead of the single arg version which removes two redundant moves. OK to push? Ed. --- CUT HERE --- exporting patch: # HG changeset patch # User Edward Nevill edward.nevill(a)linaro.org # Date 1390408183 0 # Wed Jan 22 16:29:43 2014 +0000 # Node ID 813458fe14eeb9da65e68a12abb85ae1343b2b2d # Parent 895bbf967b692fecdc4919deeb8a30907b5bd2cb - Add fix spotted by Andrew Dinn to do cbnzw instead of cbnz in casw - Use temp reg in emit_compare_and_swap to avoid corrupting cmpval - Minor tweak to use 2 arg vsn of encode_heap_oop diff -r 895bbf967b69 -r 813458fe14ee src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp --- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Fri Jan 17 13:39:19 2014 -0500 +++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Wed Jan 22 16:29:43 2014 +0000 @@ -1584,7 +1584,7 @@ __ stlxrw(rscratch1, newval, addr); // retry so we only ever return after a load fails to compare // ensures we don't return a stale value after a failed write. - __ cbnz(rscratch1, retry_load); + __ cbnzw(rscratch1, retry_load); __ bind(nope); } @@ -1615,10 +1615,12 @@ if (op->code() == lir_cas_obj) { if (UseCompressedOops) { - __ encode_heap_oop(cmpval); - __ mov(rscratch2, newval); + Register t1 = op->tmp1()->as_register(); + assert(op->tmp1()->is_valid(), "must be"); + __ encode_heap_oop(t1, cmpval); + cmpval = t1; + __ encode_heap_oop(rscratch2, newval); newval = rscratch2; - __ encode_heap_oop(newval); casw(addr, newval, cmpval); } else { casl(addr, newval, cmpval); --- CUT HERE ---

2 1