September 2015 - aarch64-port-dev

Support large codecache for JDK8
by Andrew Dinn 26 Nov '15

26 Nov '15

Attached for review is a patch which adds large codecache support to jdk8 (jdk7 version will be next). It passes basic smoke tests (java hello, javac Hello.java, netbeans build and run simple project). Ok to push? regards, Andrew Dinn -----------

3 7

CFV: New aarch64-port Committer: Andrew Hughes
by Andrew Haley 13 Oct '15

13 Oct '15

I hereby nominate Andrew John Hughes to aarch64-project Committer. He's a member of many OpenJDK projects [3] and has contributed many patches. Votes are due by 4:30 PM EST, Friday October 2, 2015. Only current aarch64-port committers [1] are eligible to vote on this nomination. Votes must be cast in the open by replying to this mailing list. For Lazy Consensus voting instructions, see [2]. Andrew. [1] http://openjdk.java.net/census [2] http://openjdk.java.net/projects/#committer-vote [3] cvmi Common VM Interface Project – Lead icedtea IcedTea Project – Lead jdk6 JDK 6 Project – Reviewer jdk7 JDK 7 Project – Reviewer jdk7u JDK 7 Updates Project – Reviewer jdk8 JDK 8 Project – Reviewer jdk8u JDK 8 Updates Project – Reviewer jdk9 JDK 9 Project – Reviewer

5 6

RFR: aarch64: add support for vectorizing floating-point fabs & fneg
by Felix Yang 02 Oct '15

02 Oct '15

Hi, I would like to contribute support for vectorizing fabs & fneg instructions on aarch64 architecture. The patch takes a similar way as adding support for vectorizing double precision sqrt on Intel architectures. And two new tests are added. The performance gain for the "sumReductionImplement" function is: 30% for single precision and 10% for double precision with LoopMaxUnroll=16. I have tested this with JTreg hotspot+langtools+jdk with no regressions. Is it OK? As this patch involves changes to shared code, I also need an Oracle sponsor for it if approved. Thanks, Felix PATCH: diff -r 66d90f141fd8 src/cpu/aarch64/vm/aarch64.ad --- a/src/cpu/aarch64/vm/aarch64.ad Tue Sep 22 13:42:09 2015 +0200 +++ b/src/cpu/aarch64/vm/aarch64.ad Wed Sep 23 12:27:37 2015 +0800 @@ -15190,6 +15190,88 @@ ins_pipe(pipe_class_default); %} +// --------------------------------- ABS -------------------------------------- + +instruct vabs2F(vecD dst, vecD src) +%{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (AbsVF src)); + ins_cost(INSN_COST * 3); + format %{ "fabs $dst,$src\t# vector (2S)" %} + ins_encode %{ + __ fabs(as_FloatRegister($dst$$reg), __ T2S, + as_FloatRegister($src$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +instruct vabs4F(vecX dst, vecX src) +%{ + predicate(n->as_Vector()->length() == 4); + match(Set dst (AbsVF src)); + ins_cost(INSN_COST * 3); + format %{ "fabs $dst,$src\t# vector (4S)" %} + ins_encode %{ + __ fabs(as_FloatRegister($dst$$reg), __ T4S, + as_FloatRegister($src$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +instruct vabs2D(vecX dst, vecX src) +%{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (AbsVD src)); + ins_cost(INSN_COST * 3); + format %{ "fabs $dst,$src\t# vector (2D)" %} + ins_encode %{ + __ fabs(as_FloatRegister($dst$$reg), __ T2D, + as_FloatRegister($src$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +// --------------------------------- NEG -------------------------------------- + +instruct vneg2F(vecD dst, vecD src) +%{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (NegVF src)); + ins_cost(INSN_COST * 3); + format %{ "fneg $dst,$src\t# vector (2S)" %} + ins_encode %{ + __ fneg(as_FloatRegister($dst$$reg), __ T2S, + as_FloatRegister($src$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +instruct vneg4F(vecX dst, vecX src) +%{ + predicate(n->as_Vector()->length() == 4); + match(Set dst (NegVF src)); + ins_cost(INSN_COST * 3); + format %{ "fneg $dst,$src\t# vector (4S)" %} + ins_encode %{ + __ fneg(as_FloatRegister($dst$$reg), __ T4S, + as_FloatRegister($src$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +instruct vneg2D(vecX dst, vecX src) +%{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (NegVD src)); + ins_cost(INSN_COST * 3); + format %{ "fneg $dst,$src\t# vector (2D)" %} + ins_encode %{ + __ fneg(as_FloatRegister($dst$$reg), __ T2D, + as_FloatRegister($src$$reg)); + %} + ins_pipe(pipe_class_default); +%} + // --------------------------------- AND -------------------------------------- instruct vand8B(vecD dst, vecD src1, vecD src2) diff -r 66d90f141fd8 src/cpu/aarch64/vm/assembler_aarch64.hpp --- a/src/cpu/aarch64/vm/assembler_aarch64.hpp Tue Sep 22 13:42:09 2015 +0200 +++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp Wed Sep 23 12:27:37 2015 +0800 @@ -2106,6 +2106,19 @@ #undef INSN +#define INSN(NAME, opc, opc2) \ + void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ + starti; \ + assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \ + f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24), f(1, 23); \ + f(T==T2D ? 1:0, 22), f(opc2, 21, 10), rf(Vn, 5), rf(Vd, 0); \ + } + + INSN(fabs, 0, 0b100000111110); + INSN(fneg, 1, 0b100000111110); + +#undef INSN + #define INSN(NAME, opc) \ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ starti; \ diff -r 66d90f141fd8 src/share/vm/adlc/formssel.cpp --- a/src/share/vm/adlc/formssel.cpp Tue Sep 22 13:42:09 2015 +0200 +++ b/src/share/vm/adlc/formssel.cpp Wed Sep 23 12:27:37 2015 +0800 @@ -4143,6 +4143,8 @@ "SubVB","SubVS","SubVI","SubVL","SubVF","SubVD", "MulVS","MulVI","MulVL","MulVF","MulVD", "DivVF","DivVD", + "AbsVF","AbsVD", + "NegVF","NegVD", "SqrtVD", "AndV" ,"XorV" ,"OrV", "AddReductionVI", "AddReductionVL", diff -r 66d90f141fd8 src/share/vm/opto/classes.hpp --- a/src/share/vm/opto/classes.hpp Tue Sep 22 13:42:09 2015 +0200 +++ b/src/share/vm/opto/classes.hpp Wed Sep 23 12:27:37 2015 +0800 @@ -290,6 +290,10 @@ macro(MulReductionVD) macro(DivVF) macro(DivVD) +macro(AbsVF) +macro(AbsVD) +macro(NegVF) +macro(NegVD) macro(SqrtVD) macro(LShiftCntV) macro(RShiftCntV) diff -r 66d90f141fd8 src/share/vm/opto/superword.cpp --- a/src/share/vm/opto/superword.cpp Tue Sep 22 13:42:09 2015 +0200 +++ b/src/share/vm/opto/superword.cpp Wed Sep 23 12:27:37 2015 +0800 @@ -1858,8 +1858,8 @@ vn = VectorNode::make(opc, in1, in2, vlen, velt_basic_type(n)); vlen_in_bytes = vn->as_Vector()->length_in_bytes(); } - } else if (opc == Op_SqrtD) { - // Promote operand to vector (Sqrt is a 2 address instruction) + } else if (opc == Op_SqrtD || opc == Op_AbsF || opc == Op_AbsD || opc == Op_NegF || opc == Op_NegD) { + // Promote operand to vector (Sqrt/Abs/Neg are 2 address instructions) Node* in = vector_opd(p, 1); vn = VectorNode::make(opc, in, NULL, vlen, velt_basic_type(n)); vlen_in_bytes = vn->as_Vector()->length_in_bytes(); diff -r 66d90f141fd8 src/share/vm/opto/vectornode.cpp --- a/src/share/vm/opto/vectornode.cpp Tue Sep 22 13:42:09 2015 +0200 +++ b/src/share/vm/opto/vectornode.cpp Wed Sep 23 12:27:37 2015 +0800 @@ -92,6 +92,18 @@ case Op_DivD: assert(bt == T_DOUBLE, "must be"); return Op_DivVD; + case Op_AbsF: + assert(bt == T_FLOAT, "must be"); + return Op_AbsVF; + case Op_AbsD: + assert(bt == T_DOUBLE, "must be"); + return Op_AbsVD; + case Op_NegF: + assert(bt == T_FLOAT, "must be"); + return Op_NegVF; + case Op_NegD: + assert(bt == T_DOUBLE, "must be"); + return Op_NegVD; case Op_SqrtD: assert(bt == T_DOUBLE, "must be"); return Op_SqrtVD; @@ -280,6 +292,12 @@ case Op_DivVF: return new DivVFNode(n1, n2, vt); case Op_DivVD: return new DivVDNode(n1, n2, vt); + case Op_AbsVF: return new AbsVFNode(n1, vt); + case Op_AbsVD: return new AbsVDNode(n1, vt); + + case Op_NegVF: return new NegVFNode(n1, vt); + case Op_NegVD: return new NegVDNode(n1, vt); + // Currently only supports double precision sqrt case Op_SqrtVD: return new SqrtVDNode(n1, vt); diff -r 66d90f141fd8 src/share/vm/opto/vectornode.hpp --- a/src/share/vm/opto/vectornode.hpp Tue Sep 22 13:42:09 2015 +0200 +++ b/src/share/vm/opto/vectornode.hpp Wed Sep 23 12:27:37 2015 +0800 @@ -309,6 +309,38 @@ virtual int Opcode() const; }; +//------------------------------AbsVFNode-------------------------------------- +// Vector Abs float +class AbsVFNode : public VectorNode { + public: + AbsVFNode(Node* in, const TypeVect* vt) : VectorNode(in,vt) {} + virtual int Opcode() const; +}; + +//------------------------------AbsVDNode-------------------------------------- +// Vector Abs double +class AbsVDNode : public VectorNode { + public: + AbsVDNode(Node* in, const TypeVect* vt) : VectorNode(in,vt) {} + virtual int Opcode() const; +}; + +//------------------------------NegVFNode-------------------------------------- +// Vector Neg float +class NegVFNode : public VectorNode { + public: + NegVFNode(Node* in, const TypeVect* vt) : VectorNode(in,vt) {} + virtual int Opcode() const; +}; + +//------------------------------NegVDNode-------------------------------------- +// Vector Neg double +class NegVDNode : public VectorNode { + public: + NegVDNode(Node* in, const TypeVect* vt) : VectorNode(in,vt) {} + virtual int Opcode() const; +}; + //------------------------------SqrtVDNode-------------------------------------- // Vector Sqrt double class SqrtVDNode : public VectorNode { diff -r 66d90f141fd8 test/compiler/loopopts/superword/SumRedAbsNeg_Double.java --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/compiler/loopopts/superword/SumRedAbsNeg_Double.java Wed Sep 23 12:27:37 2015 +0800 @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2015, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +/** + * @test + * @summary Add C2 AArch64 Superword support for scalar sum reduction optimizations : double abs & neg test + * @requires os.arch=="aarch64" + * + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:+SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=2 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Double + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:-SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=2 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Double + * + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:+SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=4 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Double + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:-SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=4 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Double + * + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:+SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=8 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Double + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:-SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=8 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Double + * + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:+SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=16 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Double + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:-SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=16 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Double + */ + +public class SumRedAbsNeg_Double +{ + public static void main(String[] args) throws Exception { + double[] a = new double[256*1024]; + double[] b = new double[256*1024]; + double[] c = new double[256*1024]; + double[] d = new double[256*1024]; + sumReductionInit(a,b,c); + double total = 0; + double valid = 3.6028590866691944E19; + + for(int j = 0; j < 2000; j++) { + total = sumReductionImplement(a,b,c,d,total); + } + + if(total == valid) { + System.out.println("Success"); + } else { + System.out.println("Invalid sum of elements variable in total: " + total); + System.out.println("Expected value = " + valid); + throw new Exception("Failed"); + } + } + + public static void sumReductionInit( + double[] a, + double[] b, + double[] c) + { + for(int j = 0; j < 1; j++) + { + for(int i = 0; i < a.length; i++) + { + a[i] = i * 1 + j; + b[i] = i * 1 - j; + c[i] = i + j; + } + } + } + + public static double sumReductionImplement( + double[] a, + double[] b, + double[] c, + double[] d, + double total) + { + for(int i = 0; i < a.length; i++) + { + d[i] = Math.abs(-a[i] * -b[i]) + Math.abs(-a[i] * -c[i]) + Math.abs(-b[i] * -c[i]); + total += d[i]; + } + return total; + } + +} diff -r 66d90f141fd8 test/compiler/loopopts/superword/SumRedAbsNeg_Float.java --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/compiler/loopopts/superword/SumRedAbsNeg_Float.java Wed Sep 23 12:27:37 2015 +0800 @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2015, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +/** + * @test + * @summary Add C2 AArch64 Superword support for scalar sum reduction optimizations : float abs & neg test + * @requires os.arch=="aarch64" + * + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:+SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=2 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Float + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:-SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=2 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Float + * + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:+SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=4 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Float + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:-SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=4 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Float + * + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:+SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=8 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Float + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:-SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=8 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Float + * + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:+SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=16 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Float + * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:-SuperWordReductions -XX:LoopUnrollLimit=250 -XX:LoopMaxUnroll=16 -XX:CompileThresholdScaling=0.1 SumRedAbsNeg_Float + */ + +public class SumRedAbsNeg_Float +{ + public static void main(String[] args) throws Exception { + float[] a = new float[256*1024]; + float[] b = new float[256*1024]; + float[] c = new float[256*1024]; + float[] d = new float[256*1024]; + sumReductionInit(a,b,c); + float total = 0; + float valid = (float)4.611686E18; + + for(int j = 0; j < 2000; j++) { + total = sumReductionImplement(a,b,c,d,total); + } + + if(total == valid) { + System.out.println("Success"); + } else { + System.out.println("Invalid sum of elements variable in total: " + total); + System.out.println("Expected value = " + valid); + throw new Exception("Failed"); + } + } + + public static void sumReductionInit( + float[] a, + float[] b, + float[] c) + { + for(int j = 0; j < 1; j++) + { + for(int i = 0; i < a.length; i++) + { + a[i] = i * 1 + j; + b[i] = i * 1 - j; + c[i] = i + j; + } + } + } + + public static float sumReductionImplement( + float[] a, + float[] b, + float[] c, + float[] d, + float total) + { + for(int i = 0; i < a.length; i++) + { + d[i] = Math.abs(-a[i] * -b[i]) + Math.abs(-a[i] * -c[i]) + Math.abs(-b[i] * -c[i]); + total += d[i]; + } + return total; + } + +}

4 7

RFR: Disable C2 peephole by default for aarch64
by Felix Yang 30 Sep '15

30 Sep '15

Hi JIT members, Currently, the C2 peephole optimization is only enabled by default for x86 & aarch64 port. But we don't have any peephole rules for aarch64 port, scanning the instruction stream in PhasePeephole::do_transform does not make sense but a waste of time for this port. So I am disabling this pass for aarch64 port by default, can anyone sponsor this if approved? PATCH: diff -r a6acc533dfef src/cpu/aarch64/vm/c2_globals_aarch64.hpp --- a/src/cpu/aarch64/vm/c2_globals_aarch64.hpp Wed Aug 19 16:16:54 2015 +0100 +++ b/src/cpu/aarch64/vm/c2_globals_aarch64.hpp Fri Aug 28 09:28:07 2015 +0800 @@ -69,7 +69,7 @@ // Peephole and CISC spilling both break the graph, and so makes the // scheduler sick. -define_pd_global(bool, OptoPeephole, true); +define_pd_global(bool, OptoPeephole, false); define_pd_global(bool, UseCISCSpill, true); define_pd_global(bool, OptoScheduling, false); define_pd_global(bool, OptoBundling, false);

3 3

hg: aarch64-port/jdk8u/jdk: 8078245: AARCH64: JDK fails to build due to undefined symbol in libpng
by edward.nevill＠gmail.com 30 Sep '15

30 Sep '15

Changeset: 7411c9182f49 Author: enevill Date: 2015-09-30 11:45 +0000 URL: http://hg.openjdk.java.net/aarch64-port/jdk8u/jdk/rev/7411c9182f49 8078245: AARCH64: JDK fails to build due to undefined symbol in libpng Summary: Add -DPNG_ARM_NEON_OPT=0 to LIBSPLASHSCREEN_CFLAGS flags Reviewed-by: dholmes, ihse, erikj ! make/lib/Awt2dLibraries.gmk

1 0

jdk8u fails to build with gcc 4.9.2
by Edward Nevill 30 Sep '15

30 Sep '15

Hi, aarch64 jdk8u and jdk8u60 fail to build with gcc 4.9.2. The following is the error. /home/ed/build/1509/jdk8u-src-1508/jdk/src/share/native/sun/awt/libpng/pngrutil.c:3947: undefined reference to `png_init_filter_functions_neon' collect2: error: ld returned 1 exit status This was fixed in jdk9/hs-comp/jdk in the following changeset changeset: 11873:88d2b7d72852 user: enevill date: Tue May 05 09:08:20 2015 +0000 files: make/lib/Awt2dLibraries.gmk description: 8078245: AARCH64: JDK fails to build due to undefined symbol in libpng Summary: Add -DPNG_ARM_NEON_OPT=0 to LIBSPLASHSCREEN_CFLAGS flags Reviewed-by: dholmes, ihse, erikj OK to backport to jdk8u and jdk8u60 (patch as below)? Ed. --- CUT HERE --- # HG changeset patch # User enevill # Date 1443613529 0 # Wed Sep 30 11:45:29 2015 +0000 # Node ID 7411c9182f49f39f92996ab749d00860b75b4683 # Parent 9399aa7ef558e5fb582670de123166a5b8a4af4a 8078245: AARCH64: JDK fails to build due to undefined symbol in libpng Summary: Add -DPNG_ARM_NEON_OPT=0 to LIBSPLASHSCREEN_CFLAGS flags Reviewed-by: dholmes, ihse, erikj diff -r 9399aa7ef558 -r 7411c9182f49 make/lib/Awt2dLibraries.gmk --- a/make/lib/Awt2dLibraries.gmk Tue Sep 15 17:11:33 2015 +0000 +++ b/make/lib/Awt2dLibraries.gmk Wed Sep 30 11:45:29 2015 +0000 @@ -1204,7 +1204,7 @@ LIBSPLASHSCREEN_DIRS += $(JDK_TOPDIR)/src/macosx/native/sun/awt/splashscreen endif - LIBSPLASHSCREEN_CFLAGS := -DSPLASHSCREEN -DPNG_NO_MMX_CODE \ + LIBSPLASHSCREEN_CFLAGS := -DSPLASHSCREEN -DPNG_NO_MMX_CODE -DPNG_ARM_NEON_OPT=0 \ $(foreach dir, $(LIBSPLASHSCREEN_DIRS), -I$(dir)) ifeq ($(OPENJDK_TARGET_OS), macosx) --- CUT HERE ---

2 1

8136820: Generate better code for some Unsafe addressing patterns
by Andrew Haley 30 Sep '15

30 Sep '15

This report is for an x86 code generation improvement. I checked, and our code is already optimal: static int[] array; static long base; static int test1() { int res = 0; for (int i = 0; i < 100; i++) { long address = (((long) i) << 2) + base; res += UNSAFE.getInt(array, address); } return res; } $ ./hs-comp/build/linux-aarch64-normal-server-slowdebug/jdk/bin/java -Xbootclasspath/p:/home/aph/NetBeansProjects/Tests/build/classes -XX:LoopMaxUnroll=0 tests.Tests ;; B2: # B2 B3 <- B1 B2 Loop: B2-B2 inner Freq: 101.007 0x000003ff70468b40: ldr w11, [x10,w12,sxtw #2] 0x000003ff70468b44: add w12, w12, #0x1 ;*iinc ; - tests.Tests::test1@32 (line 22) 0x000003ff70468b48: add w0, w0, w11 ;*iadd ; - tests.Tests::test1@30 (line 24) 0x000003ff70468b4c: cmp w12, #0x64 0x000003ff70468b50: b.lt 0x000003ff70468b40 ;*if_icmpge ; - tests.Tests::test1@7 (line 22) (Having said that, we could vectorize it, but that's something for another day.) Andrew.

1 0

RFR: 8135231: add support for vectorizing double precision sqrt
by Edward Nevill 29 Sep '15

29 Sep '15

Hi, Please review the following webrev http://cr.openjdk.java.net/~enevill/8135231/webrev/ JIRA issue: https://bugs.openjdk.java.net/browse/JDK-8135231 This adds support for vector double sqrt for aarch64. I have tested this with JTreg hotspot+langtools with no regressions. There is a trivial change to test/compiler/loopopts/superword/SumRedSqrt_Double.java -* @requires os.arch=="x86" | os.arch=="amd64" | os.arch=="x86_64" +* @requires os.arch=="x86" | os.arch=="amd64" | os.arch=="x86_64" | os.arch=="aarch64" I am not clear whether this change means that the change requires sponsoring and pushing through JPRT, but if so could someone do this. Thanks for your help, Ed.

3 7

hg: aarch64-port/jdk8u/hotspot: correct elif whihc was breaking x86 build
by adinn＠redhat.com 29 Sep '15

29 Sep '15

Changeset: e8cba2da936a Author: adinn Date: 2015-09-29 10:56 +0100 URL: http://hg.openjdk.java.net/aarch64-port/jdk8u/hotspot/rev/e8cba2da936a correct elif whihc was breaking x86 build ! src/share/vm/interpreter/abstractInterpreter.hpp

1 0

RFR: aarch64: elide DecodeN when followed by CmpP 0
by Edward Nevill 28 Sep '15

28 Sep '15

Hi, Please review the following webrev http://cr.openjdk.java.net/~enevill/8136615/webrev/ JIRA issue here: https://bugs.openjdk.java.net/browse/JDK-8136615 C2 currently generates code like 0x000003ff9d3e8920: ldr w11, [x1,#16] 0x000003ff9d3e8924: lsl x10, x11, #3 0x000003ff9d3e8928: cbnz x10, 0x000003ff9d3e8950 when doing a pointer comparison against 0 The lsl instruction is generated by a DecodeN node which can be elided in this case. The following is a simple test case public class decode { public static void main(String[] args) { if (args[0] != null) { System.out.println("not null"); } } } java -XX:-TieredCompilation -Xcomp -XX:CompileOnly=decode::main -XX:+UnlockDiagnosticVMOptions -XX:+PrintAssembly -XX:+PrintOptoAssembly -XX:+PrintIdeal decode The above is a trivial case, but I have seen many of these redundant lsl instructions generated in various list chasing code. Tested with jtreg hotspot and langtools with no regressions. Thanks for your review, Ed.

5 9