March 2016 - aarch64-port-dev

RFR(s): 8149418 AArch64: replace tst+br with tbz instruction when tst's constant operand is 2 power
by Hui Shi 07 Mar '16

07 Mar '16

Would someone help review this webrev? Finding this when adding byte arrays equals for aarch64 early. webrev: http://cr.openjdk.java.net/~hshi/8149418/webrev/ bug: https://bugs.openjdk.java.net/browse/JDK-8149418 Replace consecutive tst + br instructions with tbz/tbnz when constant is 2 power and not zero. This patch perform following actions 1. tst(r, constant) + br(EQ, L) -> tbz(r, exact_log2(constant), L) 2. tst(r, constant) + br(NE, L) -> tbnz(r, exact_log2(constant), L) For remaining tst+br patterns: 1. Most are assertion for debug build, leave them there. 2. tst source register is redefined before branch, code sequence tst(r, constant) + ldr(r ..) + br(EQ, L), optimize this need another register. Regards Hui

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RFR: 8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
by Felix Yang 06 Mar '16

06 Mar '16

Hi, Please review the following webrev: http://cr.openjdk.java.net/~fyang/8151340/webrev.00/ JIRA issue: https://bugs.openjdk.java.net/browse/JDK-8151340 As discussed in LKML: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/355996.html, the cost of changing a cache line from shared to exclusive state can be significant on aarch64 cores, especially when this is triggered by an exclusive store, since it may result in having to retry the transaction. This patch makes use of the "prfm" instruction to prefetch cache lines for write prior to ldxr/stxr loops. Is it OK? Thanks, Felix

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RFR: 8150229: aarch64: c2 fix pipeline class for several instructions.
by Felix Yang 01 Mar '16

01 Mar '16

Hi, Please review the following webrev: http://cr.openjdk.java.net/~fyang/8150229/webrev.00/ Jira issue: *https://bugs.openjdk.java.net/browse/JDK-8150229 <https://bugs.openjdk.java.net/browse/JDK-8150229>* The pipeline class for some instructions is not set correctly. An example: instruct MoveF2I_reg_reg(iRegINoSp dst, vRegF src) %{ match(Set dst (MoveF2I src)); effect(DEF dst, USE src); ins_cost(INSN_COST); format %{ "fmovs $dst, $src\t# MoveF2I_reg_reg" %} ins_encode %{ __ fmovs($dst$$Register, as_FloatRegister($src$$reg)); %} ins_pipe(pipe_class_memory); => Should be "fp_f2i" %} Patch fixes this issue. Tested with jtreg hotspot. Please help commit this patch if it's OK. Thanks, Felix.

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RFR: Bug fixes for jdk8u from jdk9
by Edward Nevill 01 Mar '16

01 Mar '16

Hi, The following are a couple patches from jdk9 which fixes nasty bugs (random SEGVs) and which I think should go into jdk8u. OK to backport? Ed. --- CUT HERE --- changeset: 10294:3f537d831d9d parent: 10278:adf6fb6c302f user: aph date: Wed Feb 17 14:06:45 2016 +0000 files: src/cpu/aarch64/vm/stubGenerator_aarch64.cpp description: 8150045: arraycopy causes segfaults in SATB during garbage collection Reviewed-by: roland changeset: 10094:f776a0470c2c user: enevill date: Thu Feb 04 16:24:28 2016 +0000 files: src/cpu/aarch64/vm/macroAssembler_aarch64.cpp description: 8148783: aarch64: SEGV running SpecJBB2013 Summary: Fix calculation of offset for adrp Reviewed-by: aph

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hg: aarch64-port/jdk8u/hotspot: Apply ReservedCodeCacheSize default limiting to AArch64 only.
by gnu.andrew＠redhat.com 01 Mar '16

01 Mar '16

Changeset: 43c11664317a Author: andrew Date: 2016-03-01 02:00 +0000 URL: http://hg.openjdk.java.net/aarch64-port/jdk8u/hotspot/rev/43c11664317a Apply ReservedCodeCacheSize default limiting to AArch64 only. ! src/share/vm/runtime/arguments.cpp

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