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aarch64-port-dev@openjdk.org

April 2024

  • 2 participants
  • 2 discussions
Re: [aarch64-port-dev ] Math: optimation for doing remainder
by Andrew Haley 02 May '24

02 May '24
On 4/12/24 11:37, Jin Guojie wrote: > According to the technical documentation of Arm N2, MSUB instruction uses the same ALU with SDIV. > After testing, it was found that the combination of MUL/SUB is much faster than MSUB. > Below is a patch I wrote to optimize the opertion of doing remainder. > Testing with actual Java programs shows that the performance of this operation has indeed been significantly improved. Interesting. I wrote a JMH test for this, and on Apple M1 separate MUL/SUB is dramatically worse: Before: Divide.iters 32 avgt 5 650.431 ± 5.890 ns/op Divide.iters 342862386 avgt 5 650.597 ± 4.460 ns/op After: Divide.iters 32 avgt 5 979.338 ± 1.266 ns/op Divide.iters 342862386 avgt 5 978.652 ± 2.005 ns/op ... which is perhaps not surprising. On another Neoverse machine I got a result very similar to yours, about 15% faster with separate MUL/SUB. To be honest with you, I hate very machine-specific performance tweaks. The biggest problem is that testing is different on every kind of machine if they all have machine-specific tweaks. Given that this is a pretty rare case, for integer modulo by a non-constant value, and that the difference is small,do you really need it? I attached a JMH test for more reliable testing. Finally, please send questions to hotspot-dev, with "AArch64" in the title, or I may not see them. -- Andrew Haley (he/him) Java Platform Lead Engineer Red Hat UK Ltd. <https://www.redhat.com> https://keybase.io/andrewhaley EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671
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Re: [aarch64-port-dev ] Aarch64: CPU_Model support for Neoverse N1/N2/V1/V2
by Jin Guojie 30 Apr '24

30 Apr '24
Hi Andrew, We wrote a patch to improve the definition of CPU models for Arm Neoverse. Evgeny thinks it’s better to continue the review process. I submitted my OCA application 10 days ago, but it is still under review. Could you please create an issue in the JDK Bug System (JBS), so that I can submit this PR after the OCA is signed? Jin Guojie (Alibaba,hotspot developer) 2024/4/18 02:32. Astigeevich, Evgeny <eastig(a)amazon.co.uk> wrote: > I agree using enums will improve readability. > It's not been done to simplify backporting. > Could you please create a JBS issue and submit a PR? > Evgeny > On 12/04/2024, 09:22, "Jin Guojie" <jinguojie.jgj(a)alibaba-inc.com <mailto:jinguojie.jgj@alibaba-inc.com>> wrote: > Hi Evgeny, > Thanks for your great work in "8321025: Enable Neoverse N1 optimizations for Neoverse V2”. > I am currently optimizing the Aarch64 branch of hotspot. I found that there are also some constant numbers in this file vm_version_aarch64.cpp. > In order to make the programming style better, wouldn't it be better if we define these constants as macros? > Below is the code patch I wrote. Thank you for your opinion. > > Jin Guojie > > > From 2dd99c9851b0efbb3c9a8bdc95973f4646ad77c2 Mon Sep 17 00:00:00 2001From: Jin Guojie <jinguojie.jgj(a)alibaba-inc.com <mailto:jinguojie.jgj@alibaba-inc.com>> > Date: Tue, 2 Apr 2024 09:06:04 +0800 > Subject: CPU_Model support for Neoverse N1/N2/V1/V2 > --- > src/hotspot/cpu/aarch64/vm_version_aarch64.cpp | 12 +++--------- > src/hotspot/cpu/aarch64/vm_version_aarch64.hpp | 7 +++++++ > 2 files changed, 10 insertions(+), 9 deletions(-) > diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp > index 18f310c746c..732020a420f 100644 > --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp > +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp > @@ -213,12 +213,8 @@ void VM_Version::initialize() { > } > > > // Neoverse > - // N1: 0xd0c > - // N2: 0xd49 > - // V1: 0xd40 > - // V2: 0xd4f > - if (_cpu == CPU_ARM && (model_is(0xd0c) || model_is(0xd49) || > - model_is(0xd40) || model_is(0xd4f))) { > + if (_cpu == CPU_ARM && (model_is(CPU_MODEL_NEOVERSE_N1) || model_is(CPU_MODEL_NEOVERSE_N2) || > + model_is(CPU_MODEL_NEOVERSE_V1) || model_is(CPU_MODEL_NEOVERSE_V2))) { > if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) { > FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true); > } > @@ -248,9 +244,7 @@ void VM_Version::initialize() { > } > > // Neoverse > - // V1: 0xd40 > - // V2: 0xd4f > - if (_cpu == CPU_ARM && (model_is(0xd40) || model_is(0xd4f))) { > + if (_cpu == CPU_ARM && (model_is(CPU_MODEL_NEOVERSE_V1) || model_is(CPU_MODEL_NEOVERSE_V2))) { > if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) { > FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true); > } > diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp > index 6883dc0d93e..a9821ea50c4 100644 > --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp > +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp > @@ -114,6 +114,13 @@ enum Ampere_CPU_Model { > CPU_MODEL_AMPERE_1B = 0xac5 /* AMPERE_1B core Implements ARMv8.7 with CSSC, MTE, SM3/SM4 extensions */ > }; > > +enum Neoverse_CPU_Model { > + CPU_MODEL_NEOVERSE_N1 = 0xd0c, > + CPU_MODEL_NEOVERSE_N2 = 0xd49, > + CPU_MODEL_NEOVERSE_V1 = 0xd40, > + CPU_MODEL_NEOVERSE_V2 = 0xd4f, > +}; > + > #define CPU_FEATURE_FLAGS(decl) \ > decl(FP, fp, 0) \ > decl(ASIMD, asimd, 1) \ > -- > 2.39.3 Amazon Development Centre (London) Ltd. Registered in England and Wales with registration number 04543232 with its registered office at 1 Principal Place, Worship Street, London EC2A 2FA, United Kingdom.
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