Hi Martin, On 10/22/2018 07:07 AM, Doerr, Martin wrote:
Hi Gustavo,
thanks for contributing. I have some minor remarks. Thanks a lot for reviewing it.
I'm not sure if it's good to have L=1 hard coded in the assembler instruction, but I think it's ok for now. (One could also pass L as parameter with default value 1.)
I agree. So, if you don't mind, to reduce any future rework on that I removed the hardcoded L=1 and now it's just a default. I introduced l14() function that matches two bits in the proper field as I don't see any collision with any other one bit field at the same position (bit 14).
I think it would be nice to have the capability bit usages in the same order at all places in the source code. We could add a comment line like "rtm is determined by OS" where it was omitted. An empty line before has_mtfprd() would be good because it's just an alias. Having them everywhere as one block in the same order helps avoiding confusion.
Sure. I think that the confusion came from the fact that I split the "CPU instruction support" section in two by adding a new one called "OS instruction support" when I refactored the TM detection. Given a second thought tho I think it's not necessary, so I've put has_tm() back to the block as you instructed, adding an empty line before has_mtfprd() as it's an alias, and added the "rtm is deter- mined by OS" comment were it applies. v2 webrev: http://cr.openjdk.java.net/~gromero/8212481/v2/ I just have one question regarding the feature-string. I see instrumentation for "fsqrts" feature but it's not currently advertised by the feature-string. On the other hand, ISA info looks to indicate that fsqrt and fsqrts are not aliases, because: fsqrt P2 -> Instruction introduced in the POWER2 Architecture. fsqrts PPC -> Instruction introduced in the PowerPC Architecture prior to ISA v2.00 so I'm wondering if just for completeness the "fsqrts" feature should be included in the feature-string. Besides that I don't see instrumentation to support has_mftgpr(), which is commented out, thus should we remove it? Like the following: diff -r c860b03741ab src/hotspot/cpu/ppc/vm_version_ppc.cpp --- a/src/hotspot/cpu/ppc/vm_version_ppc.cpp Tue Oct 16 16:26:28 2018 -0400 +++ b/src/hotspot/cpu/ppc/vm_version_ppc.cpp Tue Oct 23 10:51:22 2018 -0400 @@ -134,12 +134,12 @@ // Create and print feature-string. char buf[(num_features+1) * 16]; // Max 16 chars per feature. jio_snprintf(buf, sizeof(buf), - "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", + "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", (has_fsqrt() ? " fsqrt" : ""), + (has_fsqrts() ? " fsqrts" : ""), (has_isel() ? " isel" : ""), (has_lxarxeh() ? " lxarxeh" : ""), (has_cmpb() ? " cmpb" : ""), - //(has_mftgpr()? " mftgpr" : ""), (has_popcntb() ? " popcntb" : ""), (has_popcntw() ? " popcntw" : ""), (has_fcfids() ? " fcfids" : ""), Thank you. Best regards, Gustavo
Besides this, the change looks good.
Best regards, Martin
-----Original Message----- From: ppc-aix-port-dev <ppc-aix-port-dev-bounces@openjdk.java.net> On Behalf Of Gustavo Romero Sent: Dienstag, 16. Oktober 2018 23:10 To: hotspot-dev@openjdk.java.net; ppc-aix-port-dev@openjdk.java.net Subject: RFR(S): 8212481: PPC64: Enable POWER9 CPU detection
Hi,
Could the following small change be reviewed please?
Bug : https://bugs.openjdk.java.net/browse/JDK-8212481 Webrev: http://cr.openjdk.java.net/~gromero/8212481/v1/
It adds 'darn' instruction introduced with POWER9 CPUs to the Macroassembler and uses it to set PowerArchitecturePPC64 to POWER9 when the instruction is available on the CPU so it can be used in the future by any POWER9-specific JVM code or by any JVM code specifically dependent on the 'darn' instruction, using VM_Version::has_darn().
It was checked on POWER9 as the following:
gromero@ltc-wspoon3:~/POWER9/jdk12_tip_f53671e05660+/jvm/openjdk-12-internal/bin$ lscpu Architecture: ppc64le Byte Order: Little Endian CPU(s): 176 On-line CPU(s) list: 0-175 Thread(s) per core: 4 Core(s) per socket: 22 Socket(s): 2 NUMA node(s): 8 Model: 2.2 (pvr 004e 1202) Model name: POWER9 (raw), altivec supported CPU max MHz: 2800.0000 CPU min MHz: 2300.0000 L1d cache: 32K L1i cache: 32K L2 cache: 512K L3 cache: 10240K NUMA node0 CPU(s): 0-87 NUMA node8 CPU(s): 88-175 NUMA node250 CPU(s): NUMA node251 CPU(s): NUMA node252 CPU(s): NUMA node253 CPU(s): NUMA node254 CPU(s): NUMA node255 CPU(s): gromero@ltc-wspoon3:~/POWER9/jdk12_tip_f53671e05660+/jvm/openjdk-12-internal/bin$ LD_SHOW_AUXV=1 /bin/true | egrep "HWCAP|PLATFORM" AT_HWCAP: true_le archpmu vsx arch_2_06 dfp ic_snoop smt mmu fpu altivec ppc64 ppc32 AT_HWCAP2: darn ieee128 arch_3_00 vcrypto tar isel ebb dscr arch_2_07 AT_PLATFORM: power9 AT_BASE_PLATFORM:power9 gromero@ltc-wspoon3:~/POWER9/jdk12_tip_f53671e05660+/jvm/openjdk-12-internal/bin$ ./java -XX:+Verbose -version dscr value was 0x10 Version: ppc64 fsqrt isel lxarxeh cmpb popcntb popcntw fcfids vand lqarx aes vpmsumb mfdscr vsx ldbrx stdbrx sha darn L1_data_cache_line_size=128
openjdk version "12-internal" 2019-03-19 OpenJDK Runtime Environment (fastdebug build 12-internal+0-f53671e05660.dirty.debug.POWER9) OpenJDK 64-Bit Server VM (fastdebug build 12-internal+0-f53671e05660.dirty.debug.POWER9, mixed mode, sharing)
It was also checked on POWER8 and no regression was observed:
gromero@gromero16:~/openjdks/jdk12_tip_f53671e05660+/jvm/openjdk-12-internal/bin$ lscpu Architecture: ppc64le Byte Order: Little Endian CPU(s): 80 On-line CPU(s) list: 0-79 Thread(s) per core: 8 Core(s) per socket: 10 Socket(s): 1 NUMA node(s): 1 Model: 2.1 (pvr 004b 0201) Model name: POWER8 (architected), altivec supported Hypervisor vendor: horizontal Virtualization type: full L1d cache: 64K L1i cache: 32K NUMA node0 CPU(s): 0-79 gromero@gromero16:~/openjdks/jdk12_tip_f53671e05660+/jvm/openjdk-12-internal/bin$ LD_SHOW_AUXV=1 /bin/true | egrep "HWCAP|PLATFORM" AT_HWCAP: archpmu vsx arch_2_06 dfp ic_snoop smt mmu fpu altivec ppc64 ppc32 AT_HWCAP2: htm-nosc vcrypto tar isel ebb dscr htm arch_2_07 AT_PLATFORM: power8 AT_BASE_PLATFORM:power8 gromero@gromero16:~/openjdks/jdk12_tip_f53671e05660+/jvm/openjdk-12-internal/bin$ ./java -XX:+Verbose -version dscr value was 0x0 Version: ppc64 fsqrt isel lxarxeh cmpb popcntb popcntw fcfids vand lqarx aes vpmsumb mfdscr vsx ldbrx stdbrx sha rtm L1_data_cache_line_size=128
openjdk version "12-internal" 2019-03-19 OpenJDK Runtime Environment (fastdebug build 12-internal+0-f53671e05660.dirty.debug.POWER9) OpenJDK 64-Bit Server VM (fastdebug build 12-internal+0-f53671e05660.dirty.debug.POWER9, mixed mode, sharing)
Thank you.
Best regards, Gustavo