riscv-port-dev

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riscv-port-dev@openjdk.org

November 2021

8 participants
22 discussions

Welcome announcement
by Yangfei (Felix) 09 Nov '21

09 Nov '21

Hi all, The RISC-V Port Project has been recorded in the OpenJDK Census [1]. We already have the repo [2] and the mailing list (pre-populated with initial Reviewers) [3]. The "master" branch is seeded with the most recent gh:openjdk/jdk and will automatically be sync'd to that repo. I will push a new "riscv-port" branch to the Project repo. Future Project development should happen on this new branch. We also have a web page [4] and a wikispace [5]. Note that the wikispace is still being setup, and we need to wait for write access permission. I'll add something more on the wiki page once it's ready for editing. The next thing for me to do is to propose the current code from the riscv-port-branch of jdk-sandbox as GitHub Pull-Request. This course made things simpler from the legal point of view. It would be beneficial to track our future issues in JBS. I will ask ops to add "riscv" as a CPU target. Like other Projects, we also need project-specific entries for the Affected and Fix Version fields, e.g. JDK-8251041 [6]. I think we can do the same. Aleksey Shipilev is building nightlies here [7]. And we've provided build instructions for reference [8]. You can try the RISC-V JDK with QEMU User/System mode or HiFive Unleashed/Unmatched board. Have fun and happy hacking! Thanks, Felix [1] https://openjdk.java.net/census#riscv-port [2] https://github.com/openjdk/riscv-port [3] https://mail.openjdk.java.net/mailman/listinfo/riscv-port-dev [4] http://openjdk.java.net/projects/riscv-port [5] https://wiki.openjdk.java.net/display/RISCVPort [6] https://bugs.openjdk.java.net/browse/JDK-8251041 [7] https://builds.shipilev.net/openjdk-jdk-riscv [8] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md

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[riscv-port] RFR: 8276792: RISC-V Port: Initial support for RV64GV
by Fei Yang 08 Nov '21

08 Nov '21

This riscv64 port supports RV64GV, shorthand for RV64IMAFDV ISA extensions, and covers the templateInterpreter, C1 and C2, excluding AOT/JVMCI. All existing GCs are available on riscv64, including ZGC and ShenandoahGC. Passed jtreg tier{1,2,3,4} and jcstress tests on HiFive Unmatched board. SPECjbb & SPECjvm benchmark tests are also carried out regularly. So it should be good enough to run most Java programs. ------------- Commit messages: - 8276792: RISC-V Port: Initial support for RV64GV Changes: https://git.openjdk.java.net/riscv-port/pull/1/files Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=1&range=00 Issue: https://bugs.openjdk.java.net/browse/JDK-8276792 Stats: 56639 lines in 189 files changed: 56486 ins; 55 del; 98 mod Patch: https://git.openjdk.java.net/riscv-port/pull/1.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/1/head:pull/1 PR: https://git.openjdk.java.net/riscv-port/pull/1

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