3
56
[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions
by Feilong Jiang 04 Jan '22
by Feilong Jiang 04 Jan '22
04 Jan '22
2
11
[riscv-port] RFR: 8279346: riscv: Unnecessary sign extension in BigInteger intrinsics
by Yanhong Zhu 04 Jan '22
by Yanhong Zhu 04 Jan '22
04 Jan '22
2
2
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen
by Feilong Jiang 29 Dec '21
by Feilong Jiang 29 Dec '21
29 Dec '21
3
12
git: openjdk/riscv-port: riscv-port: 8279292: riscv: Intrinsify multiplyToLen and squareToLen
by Fei Yang 29 Dec '21
by Fei Yang 29 Dec '21
29 Dec '21
1
0
1
0
1
0
1
0
Re: [riscv-port] RFR: 8279213: riscv: RVB: Add zero/sign extend instructions [v2]
by Feilong Jiang 25 Dec '21
by Feilong Jiang 25 Dec '21
25 Dec '21
1
0
1
0