Vote: yes
-----Original Message----- From: Yangfei (Felix) Sent: Friday, December 10, 2021 10:53 AM To: riscv-port-dev@openjdk.java.net Subject: CFV: New RISC-V Port Committer: Yadong Wang
I hereby nominate Yadong Wang (yadongwang) to RISC-V Port Committer.
Yadong is the main developer of OpenJDK riscv-port since the beginning of this project. He has contributed 10 patches to JDK and RISC-V Port. These references in JDK and RISC-V Port projects justify the call to make him a RISC-V Port Committer.
Votes are due by 9:00 UTC on Friday 24, December 2021.
Only current RISC-V Port Committer[1] are eligible to vote on this nomination. Votes must be cast in the open replying to this mailing list.
For Lazy Consensus voting instructions, see[2].
[1] https://openjdk.java.net/census [2] https://openjdk.java.net/projects/#committer-vote
Thanks, Felix
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8247979: aarch64: missing side effect of killing flags for clearArray_reg_reg 8264096: slowdebug jvm crashes when StrInflatedCopy match rule is not supported 8276792: RISC-V Port: Initial support for RV64GV 8277430: riscv: Refactor interpreter native wrappers 8277431: riscv: Intrinsify recursive ObjectMonitor locking for C2 8277508: need to check has_predicated_vectors before calling scalable_predicate_reg_slots 8277877: C2 fast_unlock intrinsic on riscv has unnecessary ownership check 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 8278387: riscv: Implement UseHeavyMonitors consistently