[riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2
There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation. ------------- Commit messages: - 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 Changes: https://git.openjdk.java.net/riscv-port/pull/22/files Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=22&range=00 Issue: https://bugs.openjdk.java.net/browse/JDK-8278192 Stats: 51 lines in 3 files changed: 3 ins; 30 del; 18 mod Patch: https://git.openjdk.java.net/riscv-port/pull/22.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/22/head:pull/22 PR: https://git.openjdk.java.net/riscv-port/pull/22
On Fri, 3 Dec 2021 08:20:17 GMT, Yadong Wang <yadongwang@openjdk.org> wrote:
There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.
Changes requested by fyang (Lead). src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 2202:
2200: Label retry_load, nope; 2201: bind(retry_load); 2202: // flush and load exclusive from the memory location
Could you please also fix the comments in MacroAssembler::atomic_incw? Thanks ------------- PR: https://git.openjdk.java.net/riscv-port/pull/22
On Fri, 3 Dec 2021 10:45:08 GMT, Fei Yang <fyang@openjdk.org> wrote:
There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 2202:
2200: Label retry_load, nope; 2201: bind(retry_load); 2202: // flush and load exclusive from the memory location
Could you please also fix the comments in MacroAssembler::atomic_incw? Thanks
atomic_incw has not been called anywhere, so I'll remove it in the next commit. ------------- PR: https://git.openjdk.java.net/riscv-port/pull/22
There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.
Yadong Wang has updated the pull request incrementally with one additional commit since the last revision: 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 (2) ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/22/files - new: https://git.openjdk.java.net/riscv-port/pull/22/files/d22e7729..cffa3d06 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=22&range=01 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=22&range=00-01 Stats: 18 lines in 2 files changed: 0 ins; 18 del; 0 mod Patch: https://git.openjdk.java.net/riscv-port/pull/22.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/22/head:pull/22 PR: https://git.openjdk.java.net/riscv-port/pull/22
On Sun, 5 Dec 2021 03:26:11 GMT, Yadong Wang <yadongwang@openjdk.org> wrote:
There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.
Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:
8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 (2)
Please add the testing carried out for this change in the PR description part. Thanks. ------------- PR: https://git.openjdk.java.net/riscv-port/pull/22
On Sun, 5 Dec 2021 03:26:11 GMT, Yadong Wang <yadongwang@openjdk.org> wrote:
There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation. Hotspot and jdk tier1 passed on the unmatched board. And all jtreg tests were tested on qemu without new failures.
Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:
8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 (2)
Looks good. ------------- Marked as reviewed by fyang (Lead). PR: https://git.openjdk.java.net/riscv-port/pull/22
On Fri, 3 Dec 2021 08:20:17 GMT, Yadong Wang <yadongwang@openjdk.org> wrote:
There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation. Hotspot and jdk tier1 passed on the unmatched board. And all jtreg tests were tested on qemu without new failures.
This pull request has now been integrated. Changeset: 63b0d52d Author: Yadong Wang <yadongwang@openjdk.org> Committer: Fei Yang <fyang@openjdk.org> URL: https://git.openjdk.java.net/riscv-port/commit/63b0d52d287cb2a8f3bb1aa3a7eef... Stats: 69 lines in 4 files changed: 3 ins; 48 del; 18 mod 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 Reviewed-by: fyang ------------- PR: https://git.openjdk.java.net/riscv-port/pull/22
participants (2)
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Fei Yang
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Yadong Wang