[riscv-port] RFR: 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate
This bug can be reproduced by `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1 -version` on the unmatched board where this command will hang. The reason is that the implementation of load reserved/store conditional loop in BarrierSetAssembler::eden_allocate breaks the RISC-V Atomic extension spec: For the sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and SC instructions can only contain other instructions from the base \I" subset, excluding loads, stores, backward jumps or taken backward branches, FENCE, FENCE.I, and SYSTEM instructions. It may cause an unspecified behaviour depends on specific hardware implementations. ------------- Commit messages: - 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate Changes: https://git.openjdk.java.net/riscv-port/pull/17/files Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=17&range=00 Issue: https://bugs.openjdk.java.net/browse/JDK-8277890 Stats: 24 lines in 1 file changed: 12 ins; 8 del; 4 mod Patch: https://git.openjdk.java.net/riscv-port/pull/17.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/17/head:pull/17 PR: https://git.openjdk.java.net/riscv-port/pull/17
On Mon, 29 Nov 2021 15:06:51 GMT, Yadong Wang <yadongwang@openjdk.org> wrote:
This bug can be reproduced by `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1 -version` on the unmatched board where this command will hang. The reason is that the implementation of load reserved/store conditional loop in BarrierSetAssembler::eden_allocate breaks the RISC-V Atomic extension spec:
For the sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and SC instructions can only contain other instructions from the base \I" subset, excluding loads, stores, backward jumps or taken backward branches, FENCE, FENCE.I, and SYSTEM instructions.
It may cause an unspecified behaviour depends on specific hardware implementations.
Looks good. Thanks for fixing this :-) ------------- Marked as reviewed by fyang (Lead). PR: https://git.openjdk.java.net/riscv-port/pull/17
On Mon, 29 Nov 2021 15:06:51 GMT, Yadong Wang <yadongwang@openjdk.org> wrote:
This bug can be reproduced by `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1 -version` on the unmatched board where this command will hang. The reason is that the implementation of load reserved/store conditional loop in BarrierSetAssembler::eden_allocate breaks the RISC-V Atomic extension spec:
For the sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and SC instructions can only contain other instructions from the base \I" subset, excluding loads, stores, backward jumps or taken backward branches, FENCE, FENCE.I, and SYSTEM instructions.
It may cause an unspecified behaviour depends on specific hardware implementations.
This pull request has now been integrated. Changeset: 5bb7f8bb Author: Yadong Wang <yadongwang@openjdk.org> Committer: Fei Yang <fyang@openjdk.org> URL: https://git.openjdk.java.net/riscv-port/commit/5bb7f8bb4feeed2b090ebd8038a06... Stats: 24 lines in 1 file changed: 12 ins; 8 del; 4 mod 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate Reviewed-by: fyang ------------- PR: https://git.openjdk.java.net/riscv-port/pull/17
On Mon, 29 Nov 2021 15:06:51 GMT, Yadong Wang <yadongwang@openjdk.org> wrote:
This bug can be reproduced by `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1 -version` on the unmatched board where this command will hang. The reason is that the implementation of load reserved/store conditional loop in BarrierSetAssembler::eden_allocate breaks the RISC-V Atomic extension spec:
For the sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and SC instructions can only contain other instructions from the base \I" subset, excluding loads, stores, backward jumps or taken backward branches, FENCE, FENCE.I, and SYSTEM instructions.
It may cause an unspecified behaviour depends on specific hardware implementations.
Thank you for fixing this. Qemu and C910 cannot reveal this issue so I didn't notice it. :-( I just tested this `-XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1` on both a D1 and an unleashed board, and this issue was reproduced without this patch. No need to reply -- it is just a comment. ------------- PR: https://git.openjdk.java.net/riscv-port/pull/17
participants (3)
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Fei Yang
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Xiaolin Zheng
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Yadong Wang