[riscv-port] RFR: 8277883: riscv: Fix a temp register usage in eden_allocate
Hi team, A trivial fix for a small C1 crash - this issue could be directly reproduced by using `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1`. The reason is simple: the eden_allocate uses t2 as a register and zaps it, whereas C1 will use it as a register allocation candidate, leading to a crash. In this function, t0 never gets a use so we can use it safely. Tested in all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/15) Thanks, Xiaolin ------------- Commit messages: - Fix a temp register usage in eden_allocate Changes: https://git.openjdk.java.net/riscv-port/pull/16/files Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=16&range=00 Issue: https://bugs.openjdk.java.net/browse/JDK-8277883 Stats: 6 lines in 1 file changed: 2 ins; 0 del; 4 mod Patch: https://git.openjdk.java.net/riscv-port/pull/16.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/16/head:pull/16 PR: https://git.openjdk.java.net/riscv-port/pull/16
On Mon, 29 Nov 2021 03:43:32 GMT, zhengxiaolinX <duke@openjdk.java.net> wrote:
Hi team,
A trivial fix for a small C1 crash - this issue could be directly reproduced by using `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1`. The reason is simple: the eden_allocate uses t2 as a register and zaps it, whereas C1 will use it as a register allocation candidate, leading to a crash. In this function, t0 never gets a use so we can use it safely. Tested in all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/15)
Thanks, Xiaolin
Changes requested by fyang (Lead). src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp line 182:
180: __ bind(retry); 181: 182: Register tmp = t0;
No need to introduce local variable "tmp" here. I think we can use t0 directly here. ------------- PR: https://git.openjdk.java.net/riscv-port/pull/16
On Mon, 29 Nov 2021 07:46:53 GMT, Fei Yang <fyang@openjdk.org> wrote:
zhengxiaolinX has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:
Fix a temp register usage in eden_allocate
src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp line 182:
180: __ bind(retry); 181: 182: Register tmp = t0;
No need to introduce local variable "tmp" here. I think we can use t0 directly here.
This is a reasonable point -- changed as proposal, passed fastdebug build, and tested a simple `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1`. ------------- PR: https://git.openjdk.java.net/riscv-port/pull/16
Hi team,
A trivial fix for a small C1 crash - this issue could be directly reproduced by using `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1`. The reason is simple: the eden_allocate uses t2 as a register and zaps it, whereas C1 will use it as a register allocation candidate, leading to a crash. In this function, t0 never gets a use so we can use it safely. Tested in all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/15)
Thanks, Xiaolin
zhengxiaolinX has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision: Fix a temp register usage in eden_allocate ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/16/files - new: https://git.openjdk.java.net/riscv-port/pull/16/files/b37dd6d3..ed811e74 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=16&range=01 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=16&range=00-01 Stats: 6 lines in 1 file changed: 0 ins; 2 del; 4 mod Patch: https://git.openjdk.java.net/riscv-port/pull/16.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/16/head:pull/16 PR: https://git.openjdk.java.net/riscv-port/pull/16
On Mon, 29 Nov 2021 08:05:03 GMT, zhengxiaolinX <duke@openjdk.java.net> wrote:
Hi team,
A trivial fix for a small C1 crash - this issue could be directly reproduced by using `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1`. The reason is simple: the eden_allocate uses t2 as a register and zaps it, whereas C1 will use it as a register allocation candidate, leading to a crash. In this function, t0 never gets a use so we can use it safely. Tested in all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/15)
Thanks, Xiaolin
zhengxiaolinX has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:
Fix a temp register usage in eden_allocate
Looks good. It's definitely inappropriate to use an allocatable general-purpose register here. ------------- Marked as reviewed by fyang (Lead). PR: https://git.openjdk.java.net/riscv-port/pull/16
On Mon, 29 Nov 2021 03:43:32 GMT, zhengxiaolinX <duke@openjdk.java.net> wrote:
Hi team,
A trivial fix for a small C1 crash - this issue could be directly reproduced by using `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1`. The reason is simple: the eden_allocate uses t2 as a register and zaps it, whereas C1 will use it as a register allocation candidate, leading to a crash. In this function, t0 never gets a use so we can use it safely. Tested in all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/15)
Thanks, Xiaolin
This pull request has now been integrated. Changeset: 1101c14f Author: yunyao.zxl <yunyao.zxl@alibaba-inc.com> Committer: Fei Yang <fyang@openjdk.org> URL: https://git.openjdk.java.net/riscv-port/commit/1101c14fd5c4b5ea89e6f3868bf99... Stats: 4 lines in 1 file changed: 0 ins; 0 del; 4 mod 8277883: riscv: Fix a temp register usage in eden_allocate Reviewed-by: fyang ------------- PR: https://git.openjdk.java.net/riscv-port/pull/16
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Fei Yang
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zhengxiaolinX