[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. This PR also add zext/bext C2 instructions that were missed in JDK-8279213 ------------- Commit messages: - 8279344: riscv: RVB: Add bitwise rotation instructions Changes: https://git.openjdk.java.net/riscv-port/pull/39/files Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=00 Issue: https://bugs.openjdk.java.net/browse/JDK-8279344 Stats: 417 lines in 6 files changed: 396 ins; 1 del; 20 mod Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39 PR: https://git.openjdk.java.net/riscv-port/pull/39
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision: 8279344: riscv: RVB: Add bitwise rotation instructions ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/39/files - new: https://git.openjdk.java.net/riscv-port/pull/39/files/7c081e52..565fd2e2 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=01 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=00-01 Stats: 5 lines in 1 file changed: 1 ins; 0 del; 4 mod Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39 PR: https://git.openjdk.java.net/riscv-port/pull/39
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision: remove unused instruction in riscv_b.ad ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/39/files - new: https://git.openjdk.java.net/riscv-port/pull/39/files/565fd2e2..d9f91328 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=02 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=01-02 Stats: 118 lines in 1 file changed: 0 ins; 118 del; 0 mod Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39 PR: https://git.openjdk.java.net/riscv-port/pull/39
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision: remove unused imm definition ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/39/files - new: https://git.openjdk.java.net/riscv-port/pull/39/files/d9f91328..2fd614c1 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=03 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=02-03 Stats: 47 lines in 1 file changed: 0 ins; 47 del; 0 mod Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39 PR: https://git.openjdk.java.net/riscv-port/pull/39
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision: remove unused imm definition ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/39/files - new: https://git.openjdk.java.net/riscv-port/pull/39/files/2fd614c1..428e2151 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=04 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=03-04 Stats: 19 lines in 1 file changed: 19 ins; 0 del; 0 mod Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39 PR: https://git.openjdk.java.net/riscv-port/pull/39
On Fri, 31 Dec 2021 10:07:06 GMT, Feilong Jiang <fjiang@openjdk.org> wrote:
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests: - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java - test/jdk/java/lang
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.
Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
Rebased #40 with no conflicts. ------------- PR: https://git.openjdk.java.net/riscv-port/pull/39
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests: - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java - test/jdk/java/lang
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.
Feilong Jiang has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains three additional commits since the last revision: - remove unused imm definition - remove unused instruction in riscv_b.ad - 8279344: riscv: RVB: Add bitwise rotation instructions ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/39/files - new: https://git.openjdk.java.net/riscv-port/pull/39/files/428e2151..92e21821 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=05 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=04-05 Stats: 41 lines in 4 files changed: 4 ins; 8 del; 29 mod Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39 PR: https://git.openjdk.java.net/riscv-port/pull/39
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests: - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java - test/jdk/java/lang
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.
Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision: update copyright to 2022 ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/39/files - new: https://git.openjdk.java.net/riscv-port/pull/39/files/92e21821..fe673075 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=06 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=05-06 Stats: 6 lines in 6 files changed: 1 ins; 0 del; 5 mod Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39 PR: https://git.openjdk.java.net/riscv-port/pull/39
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests: - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java - test/jdk/java/lang
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.
Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision: update copyright to 2022 ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/39/files - new: https://git.openjdk.java.net/riscv-port/pull/39/files/fe673075..1c519c74 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=07 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=06-07 Stats: 2 lines in 1 file changed: 0 ins; 1 del; 1 mod Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39 PR: https://git.openjdk.java.net/riscv-port/pull/39
On Tue, 4 Jan 2022 03:36:24 GMT, Feilong Jiang <fjiang@openjdk.org> wrote:
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests: - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java - test/jdk/java/lang
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.
Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
Changes requested by fyang (Lead). src/hotspot/cpu/riscv/riscv_b.ad line 166:
164: 165: // unsigned int to short 166: instruct convUI2S_reg_reg_rvb(iRegINoSp dst, iRegIorL2I src, immI_16bits mask) %{
We should rename this from convUI2S_reg_reg_rvb to convS2UI_reg_reg_rvb. Please also update the comments. ------------- PR: https://git.openjdk.java.net/riscv-port/pull/39
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests: - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java - test/jdk/java/lang
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.
Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision: rename some instruct to match its match rule ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/39/files - new: https://git.openjdk.java.net/riscv-port/pull/39/files/1c519c74..d4e74d53 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=08 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=07-08 Stats: 41 lines in 2 files changed: 15 ins; 17 del; 9 mod Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39 PR: https://git.openjdk.java.net/riscv-port/pull/39
On Tue, 4 Jan 2022 07:07:23 GMT, Feilong Jiang <fjiang@openjdk.org> wrote:
This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests: - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java - test/jdk/java/lang
This PR also add zext/bext C2 instructions that were missed in JDK-8279213
Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.
Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
rename some instruct to match its match rule
Looks good. Thanks. ------------- Marked as reviewed by fyang (Lead). PR: https://git.openjdk.java.net/riscv-port/pull/39
participants (2)
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Fei Yang
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Feilong Jiang