[riscv-port] RFR: 8277968: riscv: detect vector extension with vcsr
UseRVV could cause crash on D1 board(RISCV-C906). It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when UseRVV is enabled. RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support. [1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211da... [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extensi... ------------- Commit messages: - 8277968: riscv: detect vector extension with vcsr Changes: https://git.openjdk.java.net/riscv-port/pull/18/files Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=18&range=00 Issue: https://bugs.openjdk.java.net/browse/JDK-8277968 Stats: 88 lines in 4 files changed: 81 ins; 6 del; 1 mod Patch: https://git.openjdk.java.net/riscv-port/pull/18.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/18/head:pull/18 PR: https://git.openjdk.java.net/riscv-port/pull/18
UseRVV could cause crash on D1 board(RISCV-C906).
It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when UseRVV is enabled.
RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
[1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211da... [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extensi...
kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision: 8277968: riscv: Detect vector extension with vcsr ------------- Changes: - all: https://git.openjdk.java.net/riscv-port/pull/18/files - new: https://git.openjdk.java.net/riscv-port/pull/18/files/380bb30b..fecbfefd Webrevs: - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=18&range=01 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=18&range=00-01 Stats: 0 lines in 0 files changed: 0 ins; 0 del; 0 mod Patch: https://git.openjdk.java.net/riscv-port/pull/18.diff Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/18/head:pull/18 PR: https://git.openjdk.java.net/riscv-port/pull/18
On Tue, 30 Nov 2021 08:04:52 GMT, kuaiwei <duke@openjdk.java.net> wrote:
UseRVV could cause crash on D1 board(RISCV-C906).
It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when UseRVV is enabled.
RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
[1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211da... [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extensi...
kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
This might unnecessarily complicated the issue tbh. If you want to distinguish the specific cpu/core vendor, I would suggest we do in some different way. One possible way would be through checking /proc/cpuinfo for this infomation like aarch64 port [1]. I see boards like hifive unleashed and unmatched also provide necessary microarchitecure version through /proc/cpuinfo [2]. I think this kind of infomation should be made available in the system. [1] https://github.com/openjdk/jdk/blob/master/src/hotspot/os_cpu/linux_aarch64/... [2] https://t2sde.org/hardware/board/SiFive/Unmatched ------------- PR: https://git.openjdk.java.net/riscv-port/pull/18
On Tue, 30 Nov 2021 08:04:52 GMT, kuaiwei <duke@openjdk.java.net> wrote:
UseRVV could cause crash on D1 board(RISCV-C906).
It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when UseRVV is enabled.
RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
[1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211da... [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extensi...
kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
Thanks for your comment. My first thinking is to check /proc/cpuinfo . But it doesn't provide cpu model information. Below is /proc/cpuinfo from Fedora31 on D1: [riscv@fedora-riscv ~]$ cat /proc/cpuinfo processor : 0 hart : 0 isa : rv64imafdcvu mmu : sv39 ------------- PR: https://git.openjdk.java.net/riscv-port/pull/18
On Tue, 30 Nov 2021 08:04:52 GMT, kuaiwei <duke@openjdk.java.net> wrote:
UseRVV could cause crash on D1 board(RISCV-C906).
It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when UseRVV is enabled.
RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
[1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211da... [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extensi...
kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
Thanks for your comment. My first thinking is to check /proc/cpuinfo . But it doesn't provide cpu model information. Below is /proc/cpuinfo from Fedora31 on D1:
```shell [riscv@fedora-riscv ~]$ cat /proc/cpuinfo processor : 0 hart : 0 isa : rv64imafdcvu mmu : sv39 ``` Is it a OS porting problem? See `cat /proc/cpuinfo` from Ubuntu 21.04 on unmatched:
processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc ------------- PR: https://git.openjdk.java.net/riscv-port/pull/18
On Tue, 30 Nov 2021 08:04:52 GMT, kuaiwei <duke@openjdk.java.net> wrote:
UseRVV could cause crash on D1 board(RISCV-C906).
It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when UseRVV is enabled.
RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
[1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211da... [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extensi...
kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
I'm not sure about it. But it looks we can not check cpu arch with /proc/cpuinfo. It's dependent on os implementation. ------------- PR: https://git.openjdk.java.net/riscv-port/pull/18
On Tue, 30 Nov 2021 08:04:52 GMT, kuaiwei <duke@openjdk.java.net> wrote:
UseRVV could cause crash on D1 board(RISCV-C906).
It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when UseRVV is enabled.
RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
[1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211da... [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extensi...
kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
After offline discussion with Yadong, this patch is pending to wait linux kernel update dts infomation. [1] So d1 cpu model can be retrieved from /proc/cpuinfo. [1] https://github.com/T-head-Semi/linux/blob/linux-5.10.4/arch/riscv/boot/dts/t... ------------- PR: https://git.openjdk.java.net/riscv-port/pull/18
On Tue, 30 Nov 2021 07:22:04 GMT, kuaiwei <duke@openjdk.java.net> wrote:
UseRVV could cause crash on D1 board(RISCV-C906).
It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when UseRVV is enabled.
RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
[1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211da... [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extensi...
This pull request has been closed without being integrated. ------------- PR: https://git.openjdk.java.net/riscv-port/pull/18
participants (3)
-
Fei Yang
-
kuaiwei
-
Yadong Wang