[8u] RFR: assembler canonical modified imm encoding

[Alex Kashchenko]

Hi,

On 03/30/2016 09:23 PM, Anton Kozlov wrote:
> Hi, All!
>
> In 'prec1' commit, modified imm encoding was changed to use constant amount of time for any immediate.
> Sadly, new encoding became not canonical i.e. rotate value may be not minimal as possible, which is not recommended, but allowed by ARM. Start of -XX:+PrintInterpreter looks like
>    0x72df8320: mov       r3, sp
>    0x72df8324: sub       sp, sp, #88     ; 0x58
>    0x72df8328: str       lr, [sp]
>    0x72df832c: mov       r2, r6
>    0x72df8330: mov       r1, sl
>    0x72df8334: str       r5, [fp, #-32]  ; 0xffffffe0
>    0x72df8338: ldr       r9, [fp, #-12]
>    0x72df833c: cmp       r9, #0, 8
>    0x72df8340: beq       0x72df8374
>    0x72df8344: push      {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
>    0x72df8348: add       ip, sp, #224, 2 ; 0x38
>    0x72df834c: push      {ip}            ; (str ip, [sp, #-4]!)
>    0x72df8350: movw      r0, #33092      ; 0x8144
>    0x72df8354: movt      r0, #30085      ; 0x7585
>    0x72df8358: mov       r1, pc
>    0x72df835c: sub       r1, r1, #128, 4
>
> Note instructions like
>    0x72df833c: cmp       r9, #0, 8 // zero encoded as 0 rotated at 8.
>
> The patch restores recommended encoding (still constant time encoding), after applying listing looks like
>    0x72dae320: mov       r3, sp
>    0x72dae324: sub       sp, sp, #88     ; 0x58
>    0x72dae328: str       lr, [sp]
>    0x72dae32c: mov       r2, r6
>    0x72dae330: mov       r1, sl
>    0x72dae334: str       r5, [fp, #-32]  ; 0xffffffe0
>    0x72dae338: ldr       r9, [fp, #-12]
>    0x72dae33c: cmp       r9, #0
>    0x72dae340: beq       0x72dae374
>    0x72dae344: push      {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
>    0x72dae348: add       ip, sp, #56     ; 0x38
>    0x72dae34c: push      {ip}            ; (str ip, [sp, #-4]!)
>    0x72dae350: movw      r0, #45548      ; 0xb1ec
>    0x72dae354: movt      r0, #30080      ; 0x7580
>    0x72dae358: mov       r1, pc
>    0x72dae35c: sub       r1, r1, #8
>
> Sorry for temporary inconvenience in debugging. Happy hacking again!

For what it's worth, commented part of the change (first 3 hunks - 
commented aarch32ops disassembly) cannot be applied cleanly (looks like 
the whitespaces problem). Other part applies and compiles fine.


-- 
-Alex