JTreg testcase jdk/test/javax/xml/jaxp/common/8144593/TransformationWarningsTest.java failed randomly (Aarch64 Fixed)

[yuanxiang (F)]

Hi all:
  The JTreg testcase jdk/test/javax/xml/jaxp/common/8144593/TransformationWarningsTest.java is found to be failed randomly.
  And it reported:

#  SIGSEGV (0xb) at pc=0xb3403848, pid=10744, tid=0xa280e4d0
#
# ......
# Problematic frame:
# j  com.sun.org.apache.xalan.internal.xsltc.compiler.SyntaxTreeNode.updateScope(Lcom/sun/org/apache/xalan/internal/xsltc/compiler/Parser;Lcom/sun/org/apache/xalan/internal/xsltc/compiler/SyntaxTreeNode;)Lcom/sun/org/apache/xalan/internal/xsltc/compiler/QName;+0

The problematic frame may be different each failed run.

We find that this bug is fixed in Aarch64 port.
And the error scenario is :
(1) A thread is write tag and klass to constant pool cache ( there is a barrier between these two store).
(2) Another thread is read tag and klass from constant pool cache (these is no barrier between them).
(3) Load klass may be executed before load tag, and get an error result.

The corresponding aarch64 patches add barriers.
http://hg.openjdk.java.net/aarch64-port/jdk8u/hotspot/rev/2a885c3fa856
http://hg.openjdk.java.net/aarch64-port/jdk8u/hotspot/rev/a8e2e5e2062b



According to the aarch64 patch, we made the following patch for aarch32 port.

/***********Patch Begin****************/
diff -r c0e2beb1a261 src/cpu/aarch32/vm/interp_masm_aarch32.cpp
--- a/src/cpu/aarch32/vm/interp_masm_aarch32.cpp   Sat Jun 25 19:32:07 2016 +0100
+++ b/src/cpu/aarch32/vm/interp_masm_aarch32.cpp         Fri Aug 26 18:13:49 2016 +0800
@@ -189,6 +189,7 @@
   ldr(bytecode, Address(cache,
                         ConstantPoolCache::base_offset()
                         + ConstantPoolCacheEntry::indices_offset()));
+  membar(MacroAssembler::LoadLoad);
   const int shift_count = (1 + byte_no) * BitsPerByte;
   //ubfx(bytecode, bytecode, shift_count, BitsPerByte);
   assert(shift_count >= 0 && shift_count <= 24 && 0 == (shift_count & 7), "Invalid shift count");
diff -r c0e2beb1a261 src/cpu/aarch32/vm/templateTable_aarch32.cpp
--- a/src/cpu/aarch32/vm/templateTable_aarch32.cpp Sat Jun 25 19:32:07 2016 +0100
+++ b/src/cpu/aarch32/vm/templateTable_aarch32.cpp       Fri Aug 26 18:13:49 2016 +0800
@@ -392,6 +392,7 @@
   // get type
   __ add(r3, r1, tags_offset);
   __ ldrb(r3, Address(r0, r3));
+  __ membar(MacroAssembler::LoadLoad);
   // unresolved class - get the resolved class
   __ cmp(r3, JVM_CONSTANT_UnresolvedClass);
@@ -3475,6 +3476,7 @@
   const int tags_offset = Array<u1>::base_offset_in_bytes();
   __ lea(rscratch1, Address(r0, r3, lsl(0)));
   __ ldrb(rscratch1, Address(rscratch1, tags_offset));
+  __ membar(MacroAssembler::LoadLoad);
   __ cmp(rscratch1, JVM_CONSTANT_Class);
   __ b(slow_case, Assembler::NE);
@@ -3625,6 +3627,7 @@
   // See if bytecode has already been quicked
   __ add(rscratch1, r3, Array<u1>::base_offset_in_bytes());
   __ ldrb(r1, Address(rscratch1, r14));
+  __ membar(MacroAssembler::LoadLoad);
   __ cmp(r1, JVM_CONSTANT_Class);
   __ b(quicked, Assembler::EQ);
@@ -3680,6 +3683,7 @@
   // See if bytecode has already been quicked
   __ add(rscratch1, r3, Array<u1>::base_offset_in_bytes());
   __ ldrb(r1, Address(rscratch1, r14));
+  __ membar(MacroAssembler::LoadLoad);
   __ cmp(r1, JVM_CONSTANT_Class);
   __ b(quicked, Assembler::EQ);
/***********Patch End  ****************/


  Best Wishes!
  Xiang Yuan
  08/26/2016