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<p class="MsoNormal"><span style="font-size:11.0pt;mso-fareast-language:EN-US">> Yes, I read it the same way. So we repeat the CAS for lost reservation. I'm<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;mso-fareast-language:EN-US">> interested in when this could happen and why it would be okay to sometimes<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;mso-fareast-language:EN-US">> omit this loop and do the "raw" LDREX-STREX sequence. See my original mail.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;mso-fareast-language:EN-US">Hm, I don't understand. The loop in the sequence A-F is always there. How is it omitted?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><b><span style="font-size:12.0pt;color:black">From:
</span></b><span style="font-size:12.0pt;color:black">Thomas Stüfe <thomas.stuefe@gmail.com><br>
<b>Date: </b>Monday, 13. March 2023 at 10:54<br>
<b>To: </b>Reingruber, Richard <richard.reingruber@sap.com><br>
<b>Cc: </b>porters-dev@openjdk.org <porters-dev@openjdk.org>, aarch32-port-dev@openjdk.org <aarch32-port-dev@openjdk.org><br>
<b>Subject: </b>Re: Question about CAS via LDREX/STREX on 32-bit arm<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt">Hi Richard :)<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt">On Mon, Mar 13, 2023 at 10:02 AM Reingruber, Richard <<a href="mailto:richard.reingruber@sap.com">richard.reingruber@sap.com</a>> wrote:<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> Hi ARM experts,<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">Hi Thomas, not at all an ARM expert... :)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">but I think I understand the code.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> I am trying to understand how CAS is implemented on arm; in particular, "MacroAssembler::atomic_cas_bool":<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> MacroAssembler::atomic_cas_bool<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> ```<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> assert_different_registers(tmp_reg, oldval, newval, base);<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> Label loop;<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> bind(loop);<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> A ldrex(tmp_reg, Address(base, offset));<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> B subs(tmp_reg, tmp_reg, oldval);<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> C strex(tmp_reg, newval, Address(base, offset), eq);<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> D cmp(tmp_reg, 1, eq);<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> E b(loop, eq);<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> F cmp(tmp_reg, 0);<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> if (tmpreg == noreg) {<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> pop(tmp_reg);<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> }<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> ```<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> It uses LDREX and STREX to perform a cas of *(base+offset) from oldval to newval. It does so in a loop. The code distinguishes two failures: STREX
failing, and a "semantically failed" CAS.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> Here is what I think this code does:<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> A) LDREX: tmp=*(base+offset)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> B) tmp -= oldvalue
<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> If *(base+offset) was unchanged, tmp_reg is now 0 and Z is 1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> C) If Z is 1: STREX the new value: *(base+offset)=newval. Otherwise, omit.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> After this, if the store succeeded, tmp_reg is 0, if the store failed its 1.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> D) Here, tmp_reg is: 0 if the store succeeded, 1 if it failed, 1...n if *(base+offset) had been modified before LDREX.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> We now compare with 1 and ...<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> E) ...repeat the loop if tmp_reg was 1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> So we loop until either *(base+offset) had been changed to some other value concurrently before out LDREX. Or until our store succeeded.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">> I wondered what the loop guards against. And why it would be okay sometimes to omit it.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">The loop is needed to try again if the reservation
</span><span lang="DE" style="font-size:11.0pt">was</span><span style="font-size:11.0pt"> lost</span><span lang="DE" style="font-size:11.0pt"> until the STREX succeeds or
</span><span style="font-size:11.0pt">*(base+offset) != oldvalue</span><span lang="DE" style="font-size:11.0pt">.</span><span style="font-size:11.0pt"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE" style="font-size:11.0pt">So there are two cases.
</span><span style="font-size:11.0pt">The loop is left iff<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">(1) *(base+offset) != oldvalue<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">(2) the STREX succeeded<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE" style="font-size:11.0pt">First i</span><span style="font-size:11.0pt">t is important to understand that C, D, E are only executed if at B the eq-condition is set
to true.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">This is based on the "Conditional Execution"
</span><span lang="DE" style="font-size:11.0pt">f</span><span style="font-size:11.0pt">eature of ARM: execution of most instructions can be made dependent on a condition (see
<a href="https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdeveloper.arm.com%2Fdocumentation%2Fden0013%2Fd%2FARM-Thumb-Unified-Assembly-Language-Instructions%2FInstruction-set-basics%2FConditional-execution%3Flang%3Den&data=05%7C01%7Crichard.reingruber%40sap.com%7C5e217cf5139c4ca453b608db23a8ef6e%7C42f7676cf455423c82f6dc2d99791af7%7C0%7C0%7C638142980698821044%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=gBV1sR3DFdVAklgjVRdAdb7oIEv8Zwj%2FasRfwEB10vQ%3D&reserved=0" target="_blank">
https://developer.arm.com/documentation/den0013/d/ARM-Thumb-Unified-Assembly-Language-Instructions/Instruction-set-basics/Conditional-execution?lang=en</a>)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">So in case (1) C, D, E are not executed because B indicates that *(base+offset) and oldvalue are not-eq</span><span lang="DE" style="font-size:11.0pt">
and the loop is left.</span><span style="font-size:11.0pt"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt">Ah, thanks, that was my thinking error. I did not realize that CMP was also conditional. I assumed the "eq" in the CMP (D) was a condition for the CMP. Which makes no sense, as I know now, since CMP just does
a sub and only needs two arguments. So that meant the full branch CDE was controlled from the subtraction result at B.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt">That also resolves the "1 has a double meaning" question. It hasn't.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">In case (2) C, D, E are executed. At C, if the reservation from A still exists, tmp_reg will be set to 0 otherwise to 1. At E the branch is taken
if D indicated tmp_reg == 1 (reservation was lost) otherwise the loop is left.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt">Yes, I read it the same way. So we repeat the CAS for lost reservation. I'm interested in when this could happen and why it would be okay to sometimes omit this loop and do the "raw" LDREX-STREX sequence.
See my original mail.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt">I suspect it has something to do with context switches. That the kernel does a CLREX when we switch, so if we switch between LDREX and STREX, the reservation could be lost. But why would it then be okay to
ignore this sometimes?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt">Thanks!<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt">Thomas<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">Cheers, Richard.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-bottom:12.0pt"><b><span style="font-size:12.0pt;color:black">From:
</span></b><span style="font-size:12.0pt;color:black">porters-dev <<a href="mailto:porters-dev-retn@openjdk.org" target="_blank">porters-dev-retn@openjdk.org</a>> on behalf of Thomas Stüfe <<a href="mailto:thomas.stuefe@gmail.com" target="_blank">thomas.stuefe@gmail.com</a>><br>
<b>Date: </b>Saturday, 11. March 2023 at 11:19<br>
<b>To: </b><a href="mailto:porters-dev@openjdk.org" target="_blank">porters-dev@openjdk.org</a> <<a href="mailto:porters-dev@openjdk.org" target="_blank">porters-dev@openjdk.org</a>>,
<a href="mailto:aarch32-port-dev@openjdk.org" target="_blank">aarch32-port-dev@openjdk.org</a> <<a href="mailto:aarch32-port-dev@openjdk.org" target="_blank">aarch32-port-dev@openjdk.org</a>><br>
<b>Subject: </b>Question about CAS via LDREX/STREX on 32-bit arm</span><span style="font-size:11.0pt"><o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">Hi ARM experts,<br>
<br>
I am trying to understand how CAS is implemented on arm; in particular, "MacroAssembler::atomic_cas_bool":<br>
<br>
MacroAssembler::atomic_cas_bool<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">```<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-bottom:12.0pt"><span style="font-size:11.0pt"> assert_different_registers(tmp_reg, oldval, newval, base);<br>
Label loop;<br>
bind(loop);<br>
A ldrex(tmp_reg, Address(base, offset));<br>
B subs(tmp_reg, tmp_reg, oldval);<br>
C strex(tmp_reg, newval, Address(base, offset), eq);<br>
D cmp(tmp_reg, 1, eq);<br>
E b(loop, eq);<br>
F cmp(tmp_reg, 0);<br>
if (tmpreg == noreg) {<br>
pop(tmp_reg);<br>
}<br>
```<br>
<br>
It uses LDREX and STREX to perform a cas of *(base+offset) from oldval to newval. It does so in a loop. The code distinguishes two failures: STREX failing, and a "semantically failed" CAS.<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt">Here is what I think this code does:<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-bottom:12.0pt"><span style="font-size:11.0pt">A) LDREX: tmp=*(base+offset)<br>
B) tmp -= oldvalue <br>
If *(base+offset) was unchanged, tmp_reg is now 0 and Z is 1<br>
C) If Z is 1: STREX the new value: *(base+offset)=newval. Otherwise, omit.<br>
After this, if the store succeeded, tmp_reg is 0, if the store failed its 1.<br>
D) Here, tmp_reg is: 0 if the store succeeded, 1 if it failed, 1...n if *(base+offset) had been modified before LDREX.<br>
We now compare with 1 and ...<br>
E) ...repeat the loop if tmp_reg was 1<br>
<br>
So we loop until either *(base+offset) had been changed to some other value concurrently before out LDREX. Or until our store succeeded.<br>
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I wondered what the loop guards against. And why it would be okay sometimes to omit it.<br>
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IIUC, STREX fails if the core did lose its exclusive access to the memory location since the LDREX. This can be one of three things, right? :<br>
- another core slipped in an LDREX+STREX to the same location between our LDREX and STREX<br>
- Or we context switched to another thread or process. I assume it does a CLREX then, right? Because how could you prevent a sequence like "LDREX(p1) -> switch -> LDREX(p2) -> switch back STREX(p1)" - if I understand the ARM manual [1] correctly, a STREX to
a different location than the preceding LDREX is undefined.<br>
- Or we had a signal after LDREX and did a second LDREX in the signal handler. Does the kernel do a CLREX when invoking a signal handler?<br>
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More questions:<br>
<br>
- If I got it right, at (D), tmp_reg value "1" has two meanings: either STREX failed or some thread increased the value concurrently by 1. We repeat the loop either way. Is this just accepted behavior? Increasing by 1 is maybe not that rare.<br>
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- If I understood this correctly, the loop guards us mainly against context switches. Without the loop a context switch would count as a "semantically failed" CAS. Why would that be okay? Should we not do this loop always?<br>
<br>
- Do we not need an explicit CLREX after the operation? Or does the STREX also clear the hardware monitor? Or does it just not matter?<br>
<br>
- We have VM_Version::supports_ldrex(). Code seems to me sometimes guarded by this (e.g MacroAssembler::atomic_cas_bool), sometimes code just executes ldrex/strex (e.g. the one-shot path of MacroAssembler::cas_for_lock_acquire). Am I mistaken? Or is LDREX now
generally available? Does ARMv6 mean STREX and LDREX are available?<br>
<br>
<br>
Thanks a lot!<br>
<br>
Cheers, Thomas<br>
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