[aarch64-port-dev ] Small aarch64 simulator ready for assembler/C2 vector extensions?

[Andrew Dinn]

I have added to the small aarch64 simulator what is close to being the
set of vector instructions necessary to add vector operations to the C2
compiler:

  vector load and store from/to memory
   for all available vector types 8/16B, 4/8H, 2/4W, 2X, 2/4S, 2D
   I have implemented these both along a single indexed lane of N
vectors or down all lanes of N vectors although I think we only need the
latter for N == 1

  load constant to all lanes of vector register
   for all available vector types 8/16B, 4/8H, 2/4W, 2X, 2/4S, 2D

  integer and float arithmetic
   for all available vector types 8/16B, 4/8H, 2/4W, 2X, 2/4S, 2D
   n.b. the hw appears to provide vector ADD, SUB and MUL for both
integral and floating and vector FDIV but no vector integral DIV

  logical ops (only AND, OR, NAND and NOR are defined in the hw)
   for vector types 8/16B

  signed and unsigned shifts of a vector register
    for all available vector types 8/16B, 4/8H, 2/4W, 2X, 2/4S,
    - by a vector register of shift counts
    - by an immediate constant shift count

These have been tested using hand-cranked assembly of some test code.

Omissions:

I don't think we need this but it might be required/useful to provide an
instruction which replicates a scalar constant to all lanes of a vector
(e.g. fill with zeros?)

I am not sure I have the correct semantics for shift of a vector
register by a vector register of shift counts. It looks like the
intended behaviour is that a negative count means right shift (hence why
there are both signed and unsigned shift variants). I need to validate
this on the ARM simulator.

regards,


Andrew Dinn
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