[aarch64-port-dev ] Fix prefetching
Andrew Haley
aph at redhat.com
Fri Nov 15 04:06:13 PST 2013
Does what it says on the tin.
Andrew.
# HG changeset patch
# User aph
# Date 1384516350 0
# Node ID e109c3759e3834bdb1fd98bb6d8b576aa9701854
# Parent cbc8c470e3bd2fa1711f3e135bc5b52240ba14a0
Fix prefetching in C2
diff -r cbc8c470e3bd -r e109c3759e38 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Thu Nov 14 12:59:57 2013 +0000
+++ b/src/cpu/aarch64/vm/aarch64.ad Fri Nov 15 11:52:30 2013 +0000
@@ -714,14 +714,6 @@
source_hpp %{
-// this really ought to be defined in assembler_aarch64.hpp
-
-enum {
- PLDL1KEEP = 0,
- PSTL1KEEP = 16,
- PSTL1STRM = 17
-};
-
%}
source %{
@@ -2467,7 +2459,7 @@
int scale = $mem$$scale;
int disp = $mem$$disp;
if (index == -1) {
- //__ prfm(Address(base, disp), PLDL1KEEP);
+ __ prfm(Address(base, disp), PLDL1KEEP);
__ nop();
} else {
Register index_reg = as_Register(index);
@@ -2476,7 +2468,7 @@
__ nop();
} else {
__ lea(rscratch1, Address(base, disp));
- //__ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PLDL1KEEP);
+ __ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PLDL1KEEP);
__ nop();
}
}
@@ -2489,16 +2481,16 @@
int scale = $mem$$scale;
int disp = $mem$$disp;
if (index == -1) {
- //__ prfm(Address(base, disp), PSTL1KEEP);
+ __ prfm(Address(base, disp), PSTL1KEEP);
__ nop();
} else {
Register index_reg = as_Register(index);
if (disp == 0) {
- //__ prfm(Address(base, index_reg, Address::lsl(scale)), PSTL1KEEP);
+ __ prfm(Address(base, index_reg, Address::lsl(scale)), PSTL1KEEP);
__ nop();
} else {
__ lea(rscratch1, Address(base, disp));
- //__ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1KEEP);
+ __ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1KEEP);
__ nop();
}
}
@@ -2511,16 +2503,16 @@
int scale = $mem$$scale;
int disp = $mem$$disp;
if (index == -1) {
- //__ prfm(Address(base, disp), PSTL1STRM);
+ __ prfm(Address(base, disp), PSTL1STRM);
__ nop();
} else {
Register index_reg = as_Register(index);
if (disp == 0) {
- //__ prfm(Address(base, index_reg, Address::lsl(scale)), PSTL1STRM);
+ __ prfm(Address(base, index_reg, Address::lsl(scale)), PSTL1STRM);
__ nop();
} else {
__ lea(rscratch1, Address(base, disp));
- //__ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1STRM);
+ __ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1STRM);
__ nop();
}
}
@@ -4938,7 +4930,7 @@
match(Set dst src);
ins_cost(DEFAULT_COST);
- format %{ "mov $dst, $src\t# int" %}
+ format %{ "mov $dst, $src\t# long" %}
ins_encode( aarch64_enc_mov_imm(dst, src) );
diff -r cbc8c470e3bd -r e109c3759e38 src/cpu/aarch64/vm/assembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.cpp Thu Nov 14 12:59:57 2013 +0000
+++ b/src/cpu/aarch64/vm/assembler_aarch64.cpp Fri Nov 15 11:52:30 2013 +0000
@@ -1415,13 +1415,13 @@
}
}
-void Assembler::wrap_label(Label &L, int prfop, prefetch_insn insn) {
+void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
if (L.is_bound()) {
- (this->*insn)(target(L), prfop);
+ (this->*insn)(target(L), op);
} else {
InstructionMark im(this);
L.add_patch_at(code(), locator());
- (this->*insn)(pc(), prfop);
+ (this->*insn)(pc(), op);
}
}
diff -r cbc8c470e3bd -r e109c3759e38 src/cpu/aarch64/vm/assembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp Thu Nov 14 12:59:57 2013 +0000
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp Fri Nov 15 11:52:30 2013 +0000
@@ -595,6 +595,11 @@
};
const int FPUStateSizeInWords = 32 * 2;
+typedef enum {
+ PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
+ PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
+ PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
+} prfop;
class Assembler : public AbstractAssembler {
@@ -668,12 +673,12 @@
typedef void (Assembler::* uncond_branch_insn)(address dest);
typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
- typedef void (Assembler::* prefetch_insn)(address target, int prfop);
+ typedef void (Assembler::* prefetch_insn)(address target, prfop);
void wrap_label(Label &L, uncond_branch_insn insn);
void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
- void wrap_label(Label &L, int prfop, prefetch_insn insn);
+ void wrap_label(Label &L, prfop, prefetch_insn insn);
// PC-rel. addressing
@@ -1158,15 +1163,15 @@
#undef INSN
#define INSN(NAME, opc, V) \
- void NAME(address dest, int prfop = 0) { \
+ void NAME(address dest, prfop op = PLDL1KEEP) { \
long offset = (dest - pc()) >> 2; \
starti; \
f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
sf(offset, 23, 5); \
- f(prfop, 4, 0); \
+ f(op, 4, 0); \
} \
- void NAME(Label &L, int prfop = 0) { \
- wrap_label(L, prfop, &Assembler::NAME); \
+ void NAME(Label &L, prfop op = PLDL1KEEP) { \
+ wrap_label(L, op, &Assembler::NAME); \
}
INSN(prfm, 0b11, 0);
@@ -1251,9 +1256,9 @@
#undef INSN
-#define INSN(NAME, size, op) \
- void NAME(const Address &adr) { \
- ld_st2((Register)0, adr, size, op); \
+#define INSN(NAME, size, op) \
+ void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
+ ld_st2((Register)pfop, adr, size, op); \
}
INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
diff -r cbc8c470e3bd -r e109c3759e38 src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp Thu Nov 14 12:59:57 2013 +0000
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp Fri Nov 15 11:52:30 2013 +0000
@@ -1319,6 +1319,8 @@
#ifdef BUILTIN_SIM
void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type);
+#else
+ void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
#endif
// special version of call_VM_leaf_base needed for aarch64 simulator
diff -r cbc8c470e3bd -r e109c3759e38 src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Thu Nov 14 12:59:57 2013 +0000
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Fri Nov 15 11:52:30 2013 +0000
@@ -211,11 +211,8 @@
// stub code
-#ifdef BUILTIN_SIM
// we need a C prolog to bootstrap the x86 caller into the sim
-
__ c_stub_prolog(8, 0, MacroAssembler::ret_type_void);
-#endif
address aarch64_entry = __ pc();
diff -r cbc8c470e3bd -r e109c3759e38 src/cpu/aarch64/vm/vm_version_aarch64.cpp
--- a/src/cpu/aarch64/vm/vm_version_aarch64.cpp Thu Nov 14 12:59:57 2013 +0000
+++ b/src/cpu/aarch64/vm/vm_version_aarch64.cpp Fri Nov 15 11:52:30 2013 +0000
@@ -86,6 +86,8 @@
_supports_atomic_getadd4 = true;
_supports_atomic_getset8 = true;
_supports_atomic_getadd8 = true;
+
+ FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
}
void VM_Version::initialize() {
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