From aph at redhat.com  Tue Oct  1 02:10:20 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 01 Oct 2013 10:10:20 +0100
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>
	<1380531319.7194.4.camel@localhost.localdomain>
	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>
Message-ID: <524A917C.1040802@redhat.com>

On 10/01/2013 03:46 AM, Cao Hoang Thu wrote:
> I think GC has problem... because when I run JAVA done, memory still keep, not release

What experiment have you done that shows this result?  How can we
reproduce this?

> From: Edward Nevill <edward.nevill at linaro.org>
> To: aarch64-port-dev at openjdk.java.net 
> Sent: Monday, September 30, 2013 3:55 PM
> Subject: Re: [aarch64-port-dev ] Internal Error (frame.cpp:1150), Error: ShouldNotReachHere()
>  
> 
> Hi Thu Cao,
> 
> It seems to be a problem with GC. I am looking into it.
> 
> In the meantime you may try with a smaller number such as 1E8, or even
> 1E7 depending on how much memory you have in your model.
> 
> All the best,
> Ed.
> 
> On Sun, 2013-09-29 at 09:17 +0700, Cao Hoang Thu wrote:
>> Hi all,
>>
>> I ran dhry.har with using openjdk8_sever_release, i got error:
>> java -jar dhry.jar 
>> Dhrystone Benchmark, Version 2.1 (Language: Java)
>>
>> Please give the number of runs through the benchmark: 1000000000
>> Execution starts, 1000000000 runs through Dhrystone
>> #
>> # A fatal error has been detected by the Java Runtime Environment:
>> #
>> #  Internal Error (frame.cpp:1150), pid=1081, tid=548372099600
>> #  Error: ShouldNotReachHere()



From thuhc at yahoo.com  Tue Oct  1 02:43:04 2013
From: thuhc at yahoo.com (Cao Hoang Thu)
Date: Tue, 1 Oct 2013 02:43:04 -0700 (PDT)
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <524A917C.1040802@redhat.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>
	<1380531319.7194.4.camel@localhost.localdomain>
	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A917C.1040802@redhat.com>
Message-ID: <1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>

You can run hadoop single node, run teragen:
bin/hadoop jar hadoop-examples-1.0.3.jar teragen 1000000000 teragen-100GB

After run done, you can check memory...

Regards,
Thu Cao


________________________________
 From: Andrew Haley <aph at redhat.com>
To: Cao Hoang Thu <thuhc at yahoo.com> 
Cc: "edward.nevill at linaro.org" <edward.nevill at linaro.org>; "aarch64-port-dev at openjdk.java.net" <aarch64-port-dev at openjdk.java.net> 
Sent: Tuesday, October 1, 2013 4:10 PM
Subject: Re: [aarch64-port-dev ] Internal Error (frame.cpp:1150), Error: ShouldNotReachHere()
 

On 10/01/2013 03:46 AM, Cao Hoang Thu wrote:
> I think GC has problem... because when I run JAVA done, memory still keep, not release

What experiment have you done that shows this result?? How can we
reproduce this?

> From: Edward Nevill <edward.nevill at linaro.org>
> To: aarch64-port-dev at openjdk.java.net 
> Sent: Monday, September 30, 2013 3:55 PM
> Subject: Re: [aarch64-port-dev ] Internal Error (frame.cpp:1150), Error: ShouldNotReachHere()
>? 
> 
> Hi Thu Cao,
> 
> It seems to be a problem with GC. I am looking into it.
> 
> In the meantime you may try with a smaller number such as 1E8, or even
> 1E7 depending on how much memory you have in your model.
> 
> All the best,
> Ed.
> 
> On Sun, 2013-09-29 at 09:17 +0700, Cao Hoang Thu wrote:
>> Hi all,
>>
>> I ran dhry.har with using openjdk8_sever_release, i got error:
>> java -jar dhry.jar 
>> Dhrystone Benchmark, Version 2.1 (Language: Java)
>>
>> Please give the number of runs through the benchmark: 1000000000
>> Execution starts, 1000000000 runs through Dhrystone
>> #
>> # A fatal error has been detected by the Java Runtime Environment:
>> #
>> #? Internal Error (frame.cpp:1150), pid=1081, tid=548372099600
>> #? Error: ShouldNotReachHere()

From andrew.mcdermott at linaro.org  Tue Oct  1 02:55:25 2013
From: andrew.mcdermott at linaro.org (Andrew McDermott)
Date: Tue, 1 Oct 2013 10:55:25 +0100
Subject: [aarch64-port-dev ] Missing some classes
In-Reply-To: <1380596029.96713.YahooMailNeo@web164606.mail.gq1.yahoo.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>
	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>
	<1380531319.7194.4.camel@localhost.localdomain>
	<1380596029.96713.YahooMailNeo@web164606.mail.gq1.yahoo.com>
Message-ID: <CABn4x4O-UeDgoZOtgTLbiJbtn8GJgK7LgKXowZ1G=-UBFMoJzw@mail.gmail.com>

Hi,

I was able to reproduce this on jdk8 (x86) b90 as well so it is common to
both the x86 and the aarch64-port. I haven't tried building against a later
version and it may well have been fixed there already.


On 1 October 2013 03:53, Cao Hoang Thu <thuhc at yahoo.com> wrote:

> Hi all,
>
> I got new source (merge up to jdk8-b90): OpenJDK Runtime Environment
> (build 1.8.0-internal-thcao_2013_09_28_14_23-b00)
>
> #java -Xmx1024m -jar dacapo-9.12-bach.jar eclipse
> Unzip workspace
> ===== DaCapo 9.12 eclipse starting =====
> Initialize workspace ...................
> Index workspace .....................
> Build workspace Unexpected ERROR marker(s):
> org.eclipse.update.configurator:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> SiteEntry.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> org.eclipse.text:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> UndoEdit.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> org.eclipse.team.core:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> StringMatcher.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> ValidateEditChecker.java:
>         The import java.util.Arrays cannot be resolved
> ValidateEditChecker.java:
>         Arrays cannot be resolved
> ParticipantExtensionPoint.java:
>         Arrays cannot be resolved
> ParticipantExtensionPoint.java:
>         The import java.util.Arrays cannot be resolved
> TextChange.java:
>         The import java.util.Arrays cannot be resolved
> TextChange.java:
>         Arrays cannot be resolved
> TextChange.java:
>         Arrays cannot be resolved
> TextChange.java:
>         Arrays cannot be resolved
> DocumentChange.java:
>         Cannot reduce the visibility of the inherited method from
> TextChange
> DocumentChange.java:
>         Cannot reduce the visibility of the inherited method from
> TextChange
> DocumentChange.java:
>         Cannot reduce the visibility of the inherited method from
> TextChange
> DocumentChange.java:
>         Cannot reduce the visibility of the inherited method from
> TextChange
> org.eclipse.jdt.core:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> JDTCompilerAdapter.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> org.eclipse.core.variables:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> StringSubstitutionEngine.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> org.eclipse.core.runtime.compatibility:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> PluginActivator.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> org.eclipse.core.runtime:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> MultiRule.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> org.eclipse.core.resources:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> ElementTreeIterator.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> org.eclipse.core.filebuffers:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> ResourceTextFileBuffer.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> org.eclipse.core.expressions:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> TypeExtensionManager.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> org.eclipse.ant.core:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> AntRunner.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
> org.apache.lucene:
>         The project was not built since its build path is incomplete.
> Cannot find the class file for java.lang.CharSequence. Fix the build path
> then try building this project
> TokenMgrError.java:
>         The type java.lang.CharSequence cannot be resolved. It is
> indirectly referenced from required .class files
>
> Old-version: OpenJDK Runtime Environment (build
> 1.8.0-internal-thcao_2013_09_23_09_46-b00)
> #java -Xmx1024m -jar dacapo-9.12-bach.jar eclipse
> Unzip workspace
> ===== DaCapo 9.12 eclipse starting =====
> Initialize workspace ...................
> Index workspace .....................
> Build workspace
> Search .. 4,207 references for default constructor in workspace
>        .. 1,957 references for method 'equals' in workspace
> Type hierarchy tests
> AST tests
> Completion tests .........
> Format tests ..............
> Model tests ................
> ===== DaCapo 9.12 eclipse PASSED in 72643 msec =====
> Delete workspace
>
> Regards,
> Thu Cao
>


From aph at redhat.com  Tue Oct  1 03:07:13 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 01 Oct 2013 11:07:13 +0100
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>
	<1380531319.7194.4.camel@localhost.localdomain>
	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A917C.1040802@redhat.com>
	<1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
Message-ID: <524A9ED1.3090201@redhat.com>

On 10/01/2013 10:43 AM, Cao Hoang Thu wrote:
> You can run hadoop single node, run teragen:
> bin/hadoop jar hadoop-examples-1.0.3.jar teragen 1000000000 teragen-100GB
>
> After run done, you can check memory...

Whet tool do you use to check memory?  I need to be able to reproduce
your results.

Andrew.




From andrew.mcdermott at linaro.org  Tue Oct  1 03:20:12 2013
From: andrew.mcdermott at linaro.org (Andrew McDermott)
Date: Tue, 1 Oct 2013 11:20:12 +0100
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>
	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>
	<1380531319.7194.4.camel@localhost.localdomain>
	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A917C.1040802@redhat.com>
	<1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
Message-ID: <CABn4x4P+pRyj06b_QffexA12B_nbet8AZSuw0NG_EChHQp08ew@mail.gmail.com>

It is not clear what tool you're using to measure memory in use but if you
want to forcefully evict pages from the kernel caches try:

  $ free
  $ sync; echo 3 | sudo tee -a /proc/sys/vm/drop_caches
  $ free




On 1 October 2013 10:43, Cao Hoang Thu <thuhc at yahoo.com> wrote:

> You can run hadoop single node, run teragen:
> bin/hadoop jar hadoop-examples-1.0.3.jar teragen 1000000000 teragen-100GB
>
> After run done, you can check memory...
>
> Regards,
> Thu Cao
>
>
> ________________________________
>  From: Andrew Haley <aph at redhat.com>
> To: Cao Hoang Thu <thuhc at yahoo.com>
> Cc: "edward.nevill at linaro.org" <edward.nevill at linaro.org>; "
> aarch64-port-dev at openjdk.java.net" <aarch64-port-dev at openjdk.java.net>
> Sent: Tuesday, October 1, 2013 4:10 PM
> Subject: Re: [aarch64-port-dev ] Internal Error (frame.cpp:1150), Error:
> ShouldNotReachHere()
>
>
> On 10/01/2013 03:46 AM, Cao Hoang Thu wrote:
> > I think GC has problem... because when I run JAVA done, memory still
> keep, not release
>
> What experiment have you done that shows this result?  How can we
> reproduce this?
>
> > From: Edward Nevill <edward.nevill at linaro.org>
> > To: aarch64-port-dev at openjdk.java.net
> > Sent: Monday, September 30, 2013 3:55 PM
> > Subject: Re: [aarch64-port-dev ] Internal Error (frame.cpp:1150), Error:
> ShouldNotReachHere()
> >
> >
> > Hi Thu Cao,
> >
> > It seems to be a problem with GC. I am looking into it.
> >
> > In the meantime you may try with a smaller number such as 1E8, or even
> > 1E7 depending on how much memory you have in your model.
> >
> > All the best,
> > Ed.
> >
> > On Sun, 2013-09-29 at 09:17 +0700, Cao Hoang Thu wrote:
> >> Hi all,
> >>
> >> I ran dhry.har with using openjdk8_sever_release, i got error:
> >> java -jar dhry.jar
> >> Dhrystone Benchmark, Version 2.1 (Language: Java)
> >>
> >> Please give the number of runs through the benchmark: 1000000000
> >> Execution starts, 1000000000 runs through Dhrystone
> >> #
> >> # A fatal error has been detected by the Java Runtime Environment:
> >> #
> >> #  Internal Error (frame.cpp:1150), pid=1081, tid=548372099600
> >> #  Error: ShouldNotReachHere()
>


From aph at redhat.com  Tue Oct  1 03:21:05 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 01 Oct 2013 11:21:05 +0100
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <524A9ED1.3090201@redhat.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>
	<1380531319.7194.4.camel@localhost.localdomain>
	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A917C.1040802@redhat.com>
	<1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A9ED1.3090201@redhat.com>
Message-ID: <524AA211.1080000@redhat.com>

On 10/01/2013 11:07 AM, Andrew Haley wrote:
> On 10/01/2013 10:43 AM, Cao Hoang Thu wrote:
>> You can run hadoop single node, run teragen:
>> bin/hadoop jar hadoop-examples-1.0.3.jar teragen 1000000000 teragen-100GB
>>
>> After run done, you can check memory...
>
> Whet tool do you use to check memory?  I need to be able to reproduce
> your results.

By the way, I never did get Hadoop to work.  The documentation is
terrible, and I can't figure out how to install it.

Andrew.



From andrew.mcdermott at linaro.org  Tue Oct  1 05:46:10 2013
From: andrew.mcdermott at linaro.org (Andrew McDermott)
Date: Tue, 1 Oct 2013 13:46:10 +0100
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <524AA211.1080000@redhat.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>
	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>
	<1380531319.7194.4.camel@localhost.localdomain>
	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A917C.1040802@redhat.com>
	<1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A9ED1.3090201@redhat.com> <524AA211.1080000@redhat.com>
Message-ID: <CABn4x4Om6jqeDRBm0YpJLr9QqJzqm1ix98WCaKGmy157_L78rA@mail.gmail.com>

Andrew:

I have a pre-compiled version here:

  http://people.linaro.org/~andrew.mcdermott/personal-hadoop.tar.bz2

It's something that works for me if untarred into $HOME.

A quick example would be:

$ cd ~/personal-hadoop
$ . env.sh
$ which hadoop

and then you can try running the teragen example(s):

$ hadoop jar
${HADOOP_COMMON_HOME}/mapreduce/hadoop-mapreduce-examples-3.0.0-SNAPSHOT.jar
teragen 10000000 teragen-1GB
$ hadoop jar
${HADOOP_COMMON_HOME}/mapreduce/hadoop-mapreduce-examples-3.0.0-SNAPSHOT.jar
terasort teragen-1GB teragen-1GB-sorted
$ hadoop jar
${HADOOP_COMMON_HOME}/mapreduce/hadoop-mapreduce-examples-3.0.0-SNAPSHOT.jar
teravalidate teragen-1GB-sorted teragen-1GB-validate

HTH,
Andy.


From thuhc at yahoo.com  Tue Oct  1 05:55:34 2013
From: thuhc at yahoo.com (Cao Hoang Thu)
Date: Tue, 1 Oct 2013 05:55:34 -0700 (PDT)
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <CABn4x4Om6jqeDRBm0YpJLr9QqJzqm1ix98WCaKGmy157_L78rA@mail.gmail.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>	<1380531319.7194.4.camel@localhost.localdomain>	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>	<524A917C.1040802@redhat.com>	<1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>	<524A9ED1.3090201@redhat.com>	<524AA211.1080000@redhat.com>
	<CABn4x4Om6jqeDRBm0YpJLr9QqJzqm1ix98WCaKGmy157_L78rA@mail.gmail.com>
Message-ID: <1380632134.36873.YahooMailNeo@web164605.mail.gq1.yahoo.com>

You can download here:
http://archive.apache.org/dist/hadoop/core/hadoop-1.0.3/


Guide setup/run hadoop here:
http://hadoop.apache.org/docs/stable/single_node_setup.html


Regards,
Thu Cao

________________________________
 From: Andrew McDermott <andrew.mcdermott at linaro.org>
To: Andrew Haley <aph at redhat.com> 
Cc: Cao Hoang Thu <thuhc at yahoo.com>; "aarch64-port-dev at openjdk.java.net" <aarch64-port-dev at openjdk.java.net> 
Sent: Tuesday, October 1, 2013 7:46 PM
Subject: Re: [aarch64-port-dev ] Internal Error (frame.cpp:1150), Error: ShouldNotReachHere()
 


Andrew:

I have a pre-compiled version here:

? http://people.linaro.org/~andrew.mcdermott/personal-hadoop.tar.bz2

It's something that works for me if untarred into $HOME.

A quick example would be:

$ cd ~/personal-hadoop
$ . env.sh
$ which hadoop

and then you can try running the teragen example(s):

$ hadoop jar ${HADOOP_COMMON_HOME}/mapreduce/hadoop-mapreduce-examples-3.0.0-SNAPSHOT.jar teragen 10000000 teragen-1GB

$ hadoop jar ${HADOOP_COMMON_HOME}/mapreduce/hadoop-mapreduce-examples-3.0.0-SNAPSHOT.jar terasort teragen-1GB teragen-1GB-sorted
$ hadoop jar ${HADOOP_COMMON_HOME}/mapreduce/hadoop-mapreduce-examples-3.0.0-SNAPSHOT.jar teravalidate teragen-1GB-sorted teragen-1GB-validate

HTH,
Andy.

From thuhc at yahoo.com  Tue Oct  1 05:56:49 2013
From: thuhc at yahoo.com (Cao Hoang Thu)
Date: Tue, 1 Oct 2013 05:56:49 -0700 (PDT)
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <CABn4x4P+pRyj06b_QffexA12B_nbet8AZSuw0NG_EChHQp08ew@mail.gmail.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>	<1380531319.7194.4.camel@localhost.localdomain>	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>	<524A917C.1040802@redhat.com>	<1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<CABn4x4P+pRyj06b_QffexA12B_nbet8AZSuw0NG_EChHQp08ew@mail.gmail.com>
Message-ID: <1380632209.53941.YahooMailNeo@web164603.mail.gq1.yahoo.com>

Yes, I used free for checking memory...


________________________________
 From: Andrew McDermott <andrew.mcdermott at linaro.org>
To: Cao Hoang Thu <thuhc at yahoo.com> 
Cc: Andrew Haley <aph at redhat.com>; "aarch64-port-dev at openjdk.java.net" <aarch64-port-dev at openjdk.java.net> 
Sent: Tuesday, October 1, 2013 5:20 PM
Subject: Re: [aarch64-port-dev ] Internal Error (frame.cpp:1150), Error: ShouldNotReachHere()
 


It is not clear what tool you're using to measure memory in use but if you want to forcefully evict pages from the kernel caches try:


? $ free
? $ sync; echo 3 | sudo tee -a /proc/sys/vm/drop_caches

? $ free





On 1 October 2013 10:43, Cao Hoang Thu <thuhc at yahoo.com> wrote:

You can run hadoop single node, run teragen:
>bin/hadoop jar hadoop-examples-1.0.3.jar teragen 1000000000 teragen-100GB
>
>After run done, you can check memory...
>
>Regards,
>Thu Cao
>
>
>
>________________________________
>?From: Andrew Haley <aph at redhat.com>
>To: Cao Hoang Thu <thuhc at yahoo.com>
>Cc: "edward.nevill at linaro.org" <edward.nevill at linaro.org>; "aarch64-port-dev at openjdk.java.net" <aarch64-port-dev at openjdk.java.net>
>Sent: Tuesday, October 1, 2013 4:10 PM
>
>Subject: Re: [aarch64-port-dev ] Internal Error (frame.cpp:1150), Error: ShouldNotReachHere()
>
>
>On 10/01/2013 03:46 AM, Cao Hoang Thu wrote:
>> I think GC has problem... because when I run JAVA done, memory still keep, not release
>
>What experiment have you done that shows this result?? How can we
>reproduce this?
>
>> From: Edward Nevill <edward.nevill at linaro.org>
>> To: aarch64-port-dev at openjdk.java.net
>> Sent: Monday, September 30, 2013 3:55 PM
>> Subject: Re: [aarch64-port-dev ] Internal Error (frame.cpp:1150), Error: ShouldNotReachHere()
>>?
>>
>> Hi Thu Cao,
>>
>> It seems to be a problem with GC. I am looking into it.
>>
>> In the meantime you may try with a smaller number such as 1E8, or even
>> 1E7 depending on how much memory you have in your model.
>>
>> All the best,
>> Ed.
>>
>> On Sun, 2013-09-29 at 09:17 +0700, Cao Hoang Thu wrote:
>>> Hi all,
>>>
>>> I ran dhry.har with using openjdk8_sever_release, i got error:
>>> java -jar dhry.jar
>>> Dhrystone Benchmark, Version 2.1 (Language: Java)
>>>
>>> Please give the number of runs through the benchmark: 1000000000
>>> Execution starts, 1000000000 runs through Dhrystone
>>> #
>>> # A fatal error has been detected by the Java Runtime Environment:
>>> #
>>> #? Internal Error (frame.cpp:1150), pid=1081, tid=548372099600
>>> #? Error: ShouldNotReachHere()
>

From aph at redhat.com  Tue Oct  1 06:03:54 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 01 Oct 2013 14:03:54 +0100
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <1380632209.53941.YahooMailNeo@web164603.mail.gq1.yahoo.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>	<1380531319.7194.4.camel@localhost.localdomain>	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>	<524A917C.1040802@redhat.com>	<1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<CABn4x4P+pRyj06b_QffexA12B_nbet8AZSuw0NG_EChHQp08ew@mail.gmail.com>
	<1380632209.53941.YahooMailNeo@web164603.mail.gq1.yahoo.com>
Message-ID: <524AC83A.1000103@redhat.com>

On 10/01/2013 01:56 PM, Cao Hoang Thu wrote:
> Yes, I used free for checking memory...

That's not the right thing to do.

To find out what memory a process is using, do

   cat /proc/$PID/maps

There's no point using free because memory is used by the filesystem
cache.

Andrew.



From aph at redhat.com  Tue Oct  1 06:19:34 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 01 Oct 2013 14:19:34 +0100
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <CABn4x4Om6jqeDRBm0YpJLr9QqJzqm1ix98WCaKGmy157_L78rA@mail.gmail.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>
	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>
	<1380531319.7194.4.camel@localhost.localdomain>
	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A917C.1040802@redhat.com>
	<1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A9ED1.3090201@redhat.com> <524AA211.1080000@redhat.com>
	<CABn4x4Om6jqeDRBm0YpJLr9QqJzqm1ix98WCaKGmy157_L78rA@mail.gmail.com>
Message-ID: <524ACBE6.2040500@redhat.com>

On 10/01/2013 01:46 PM, Andrew McDermott wrote:
> Andrew:
>
> I have a pre-compiled version here:
>
>    http://people.linaro.org/~andrew.mcdermott/personal-hadoop.tar.bz2
>
> It's something that works for me if untarred into $HOME.
>
> A quick example would be:
>
> $ cd ~/personal-hadoop
> $ . env.sh
> $ which hadoop
>
> and then you can try running the teragen example(s):
>
> $ hadoop jar
> ${HADOOP_COMMON_HOME}/mapreduce/hadoop-mapreduce-examples-3.0.0-SNAPSHOT.jar

Hmmm, that didn't work.  This did:

  hadoop jar $HADOOP_COMMON_HOME/share/hadoop/mapreduce/hadoop-mapreduce-examples-3.0.0-SNAPSHOT.jar teragen 10000000 teragen-1GB

Andrew.


From andrew.mcdermott at linaro.org  Tue Oct  1 06:29:35 2013
From: andrew.mcdermott at linaro.org (Andrew McDermott)
Date: Tue, 1 Oct 2013 14:29:35 +0100
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <524ACBE6.2040500@redhat.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>
	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>
	<1380531319.7194.4.camel@localhost.localdomain>
	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A917C.1040802@redhat.com>
	<1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A9ED1.3090201@redhat.com> <524AA211.1080000@redhat.com>
	<CABn4x4Om6jqeDRBm0YpJLr9QqJzqm1ix98WCaKGmy157_L78rA@mail.gmail.com>
	<524ACBE6.2040500@redhat.com>
Message-ID: <CABn4x4M2yhWEcesTHLAZr05i76SeeQMJxkK9rVJO4r8_mGAEdA@mail.gmail.com>

OK, good. (My environment may well be a little polluted...)


On 1 October 2013 14:19, Andrew Haley <aph at redhat.com> wrote:

> On 10/01/2013 01:46 PM, Andrew McDermott wrote:
>
>> Andrew:
>>
>> I have a pre-compiled version here:
>>
>>    http://people.linaro.org/~**andrew.mcdermott/personal-**hadoop.tar.bz2<http://people.linaro.org/~andrew.mcdermott/personal-hadoop.tar.bz2>
>>
>> It's something that works for me if untarred into $HOME.
>>
>> A quick example would be:
>>
>> $ cd ~/personal-hadoop
>> $ . env.sh
>> $ which hadoop
>>
>> and then you can try running the teragen example(s):
>>
>> $ hadoop jar
>> ${HADOOP_COMMON_HOME}/**mapreduce/hadoop-mapreduce-**
>> examples-3.0.0-SNAPSHOT.jar
>>
>
> Hmmm, that didn't work.  This did:
>
>  hadoop jar $HADOOP_COMMON_HOME/share/**hadoop/mapreduce/hadoop-**
> mapreduce-examples-3.0.0-**SNAPSHOT.jar teragen 10000000 teragen-1GB
>
> Andrew.
>


From aph at redhat.com  Tue Oct  1 06:29:54 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 01 Oct 2013 14:29:54 +0100
Subject: [aarch64-port-dev ] Internal Error (frame.cpp:1150),
	Error: ShouldNotReachHere()
In-Reply-To: <524ACBE6.2040500@redhat.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>
	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>
	<1380531319.7194.4.camel@localhost.localdomain>
	<1380595588.36774.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A917C.1040802@redhat.com>
	<1380620584.37776.YahooMailNeo@web164602.mail.gq1.yahoo.com>
	<524A9ED1.3090201@redhat.com> <524AA211.1080000@redhat.com>
	<CABn4x4Om6jqeDRBm0YpJLr9QqJzqm1ix98WCaKGmy157_L78rA@mail.gmail.com>
	<524ACBE6.2040500@redhat.com>
Message-ID: <524ACE52.9040102@redhat.com>

On 10/01/2013 02:19 PM, Andrew Haley wrote:
> On 10/01/2013 01:46 PM, Andrew McDermott wrote:
>> Andrew:
>>
>> I have a pre-compiled version here:
>>
>>     http://people.linaro.org/~andrew.mcdermott/personal-hadoop.tar.bz2
>>
>> It's something that works for me if untarred into $HOME.
>>
>> A quick example would be:
>>
>> $ cd ~/personal-hadoop
>> $ . env.sh
>> $ which hadoop
>>
>> and then you can try running the teragen example(s):
>>
>> $ hadoop jar
>> ${HADOOP_COMMON_HOME}/mapreduce/hadoop-mapreduce-examples-3.0.0-SNAPSHOT.jar
>
> Hmmm, that didn't work.  This did:
>
>    hadoop jar $HADOOP_COMMON_HOME/share/hadoop/mapreduce/hadoop-mapreduce-examples-3.0.0-SNAPSHOT.jar teragen 10000000 teragen-1GB

And I can't reproduce any fault.  I'm not going to proceed any further on
this for the time being.

Andrew.



From aph at redhat.com  Tue Oct  1 06:52:15 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 01 Oct 2013 14:52:15 +0100
Subject: [aarch64-port-dev ] Another AArch64 reproducer -
 jvmtiEnv->ForceEarlyReturn*() called from JVM TI agent cause HS crash
In-Reply-To: <1691444888.18070325.1379692134417.JavaMail.root@redhat.com>
References: <1691444888.18070325.1379692134417.JavaMail.root@redhat.com>
Message-ID: <524AD38F.2040008@redhat.com>

On 09/20/2013 04:48 PM, Pavel Tisnovsky wrote:
> Hi Andrew,
>
> here's another AArch64 reproducer which uses jvmtiEnv->ForceEarlyReturn*() functionality
> from JVM TI interface. The reproducer is not complicated:
>
>
> 1) JVM TI agent setup breakpoints for all methods in Test33.java class which have name appropriate to
>     regexp *method(). I used the easiest solution so please don't add/remove any lines in Test33.java,
>     because line numbers are hardcoded in the agent in the array breakpoints.
>
> 2) breakpoints are set to the second line/second statement on all those methods.
>
> 3) Test33 is started and JVM TI agent is connected to JVM on startup.
>
> 4) when some breakpoint is reached, the corresponding jvmtiEnv->ForceEarlyReturn*() function
>     is called (there are six functions depending of the type which is to be returned)
>
> 5) ->  only first line/statement of each method should be executed, but in case of AArch64 JVM
>     I got a HS crash (similar when I used JDWP instead of JVM TI).
>
> Please note that you would need to update the script compile.sh and test_aarch64.sh because
> there's a need to set a proper path to AArch64 JDK.

??

  $ LD_LIBRARY_PATH=. /local/aarch64/jdk8/build/linux-aarch64-normal-client-slowdebug/images/j2sdk-image/jre/bin/java  -classpath . -agentlib:jvmti=test test -platform.jvmtiSupported true
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib64/libthread_db.so.1".
[New Thread 0x7ffff6d83700 (LWP 17070)]
ON_LOAD_ENTRY() called
test_setup() called
Agent(test, true)
attach check begin
attach check ok
load library: jvmti
load library: jvmti loaded
connecting with otherJVMmode=true
connected with otherJVMmode=true
Agent_OnLoad invoked
Agent_isOnAttachMode invoked
prepare() called
can generate breakpoint events
prepare/setEventCallback ok
prepare/setEventNotificationMode ok
GetMethodLocation ok
SetBreakpoint ok
prepare() exits with ok status 0
breakpoint visited!!!
check() called
check() exits status 0

Andrew.


From aph at redhat.com  Tue Oct  1 06:56:44 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 01 Oct 2013 14:56:44 +0100
Subject: [aarch64-port-dev ] Fix register corrption caused by
	check_klass_subtype_slow_path.
Message-ID: <524AD49C.4040502@redhat.com>

This is a silly bug from some time ago.  We weren't saving registers
correctly.

Andrew.


# HG changeset patch
# User aph
# Date 1380561206 -3600
# Node ID d020dd3e1d3f71328688dfa1635366c3dabc8ee4
# Parent  4cf0e7f0e764565125537b99cbb10018209aecfd
Fix register corrption caused by check_klass_subtype_slow_path.

diff -r 4cf0e7f0e764 -r d020dd3e1d3f src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Mon Sep 30 16:16:13 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Mon Sep 30 18:13:26 2013 +0100
@@ -800,14 +800,14 @@
    assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)

    // Get super_klass value into r0 (even if it was in r5 or r2).
-  bool pushed_r0 = false, pushed_r2 = IS_A_TEMP(r2), pushed_r5 = IS_A_TEMP(r5);
+  bool pushed_r0 = false, pushed_r2 = !IS_A_TEMP(r2), pushed_r5 = !IS_A_TEMP(r5);

    if (super_klass != r0 || UseCompressedOops) {
      if (!IS_A_TEMP(r0))
        pushed_r0 = true;
    }

-  push(r0->bit(pushed_r0) | r2->bit(pushed_r2) | r2->bit(pushed_r5), sp);
+  push(r0->bit(pushed_r0) | r2->bit(pushed_r2) | r5->bit(pushed_r5), sp);

  #ifndef PRODUCT
    mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr);
@@ -830,7 +830,7 @@
    repne_scan(r5, r0, r2, rscratch1);

    // Unspill the temp. registers:
-  pop(r0->bit(pushed_r0) | r2->bit(pushed_r2) | r2->bit(pushed_r5), sp);
+  pop(r0->bit(pushed_r0) | r2->bit(pushed_r2) | r5->bit(pushed_r5), sp);

    br(Assembler::NE, *L_failure);



From aph at redhat.com  Tue Oct  1 07:01:41 2013
From: aph at redhat.com (aph at redhat.com)
Date: Tue, 01 Oct 2013 14:01:41 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: 4 new changesets
Message-ID: <20131001140150.BE06C62C42@hg.openjdk.java.net>

Changeset: 4cf0e7f0e764
Author:    aph
Date:      2013-09-30 16:16 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/4cf0e7f0e764

Rewrite checkcasting array copy stub

! src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
! src/cpu/aarch64/vm/stubGenerator_aarch64.cpp

Changeset: d020dd3e1d3f
Author:    aph
Date:      2013-09-30 18:13 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/d020dd3e1d3f

Fix register corrption caused by check_klass_subtype_slow_path.

! src/cpu/aarch64/vm/macroAssembler_aarch64.cpp

Changeset: 7350196bdc1a
Author:    aph
Date:      2013-09-30 18:39 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/7350196bdc1a

Assertion check only

! src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp

Changeset: c2d6e3b390e8
Author:    aph
Date:      2013-10-01 15:01 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/c2d6e3b390e8

Merge




From aph at redhat.com  Tue Oct  1 07:00:23 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 01 Oct 2013 15:00:23 +0100
Subject: [aarch64-port-dev ] Rewrite checkcasting array copy stub
Message-ID: <524AD577.2010207@redhat.com>

This is a complete rewrite of the version of the arraycopy stub that
does piecewise checkcasting.

It was originally based on the x86 equivalent, but that resulted in
some pretty awful unidiomatic aarch64 code, so I've rewritten it to be
much more straightforward and have a simpler interface to its caller
which I've changed to fit.

Andrew.


# HG changeset patch
# User aph
# Date 1380554173 -3600
# Node ID 4cf0e7f0e764565125537b99cbb10018209aecfd
# Parent  35932bf7751a020993f89fe11b325f429fb3f9ec
Rewrite checkcasting array copy stub

diff -r 35932bf7751a -r 4cf0e7f0e764 src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Fri Sep 27 18:04:00 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Mon Sep 30 16:16:13 2013 +0100
@@ -2216,10 +2216,6 @@

      __ cbz(r0, *stub->continuation());

-    if (copyfunc_addr != NULL) {
-      __ eon(tmp, r0, zr);
-    }
-
      // Reload values from the stack so they are where the stub
      // expects them.
      __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
@@ -2227,9 +2223,10 @@
      __ ldr(src,              Address(sp, 4*BytesPerWord));

      if (copyfunc_addr != NULL) {
-      __ subw(length, length, tmp);
-      __ addw(src_pos, src_pos, tmp);
-      __ addw(dst_pos, dst_pos, tmp);
+      __ subw(rscratch1, length, r0); // Number of oops actually copied
+      __ addw(src_pos, src_pos, rscratch1);
+      __ addw(dst_pos, dst_pos, rscratch1);
+      __ mov(length, r0); // Number of oops left to copy
      }
      __ b(*stub->entry());

@@ -2398,17 +2395,15 @@
          }
  #endif

-        __ eon(tmp, r0, zr);
-
          // Restore previously spilled arguments
  	__ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
  	__ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
  	__ ldr(src,              Address(sp, 4*BytesPerWord));

-
-        __ subw(length, length, tmp);
-        __ addw(src_pos, src_pos, tmp);
-        __ addw(dst_pos, dst_pos, tmp);
+	__ subw(rscratch1, length, r0); // Number of oops actually copied
+	__ addw(src_pos, src_pos, rscratch1);
+	__ addw(dst_pos, dst_pos, rscratch1);
+	__ mov(length, r0); // Number of oops left to copy
        }

        __ b(*stub->entry());
diff -r 35932bf7751a -r 4cf0e7f0e764 src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Fri Sep 27 18:04:00 2013 +0100
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Mon Sep 30 16:16:13 2013 +0100
@@ -1223,7 +1223,8 @@
    //   used by generate_conjoint_byte_copy().
    //
    address generate_disjoint_byte_copy(bool aligned, address* entry, const char *name) {
-    return generate_disjoint_copy(sizeof (jbyte), aligned, /*is_oop*/false, entry, name);
+    const bool not_oop = false;
+    return generate_disjoint_copy(sizeof (jbyte), aligned, not_oop, entry, name);
    }

    // Arguments:
@@ -1243,7 +1244,8 @@
    //
    address generate_conjoint_byte_copy(bool aligned, address nooverlap_target,
                                        address* entry, const char *name) {
-    return generate_conjoint_copy(sizeof (jbyte), aligned, /*is_oop*/false, nooverlap_target, entry, name);
+    const bool not_oop = false;
+    return generate_conjoint_copy(sizeof (jbyte), aligned, not_oop, nooverlap_target, entry, name);
    }

    // Arguments:
@@ -1267,7 +1269,8 @@
    //
    address generate_disjoint_short_copy(bool aligned,
  				       address* entry, const char *name) {
-    return generate_disjoint_copy(sizeof (jshort), aligned, /*is_oop*/false, entry, name);
+    const bool not_oop = false;
+    return generate_disjoint_copy(sizeof (jshort), aligned, not_oop, entry, name);
    }

    // Arguments:
@@ -1287,7 +1290,8 @@
    //
    address generate_conjoint_short_copy(bool aligned, address nooverlap_target,
                                         address *entry, const char *name) {
-    return generate_conjoint_copy(sizeof (jshort), aligned, /*is_oop*/false, nooverlap_target, entry, name);
+    const bool not_oop = false;
+    return generate_conjoint_copy(sizeof (jshort), aligned, not_oop, nooverlap_target, entry, name);

    }
    // Arguments:
@@ -1390,10 +1394,8 @@
    address generate_disjoint_oop_copy(bool aligned, address *entry,
  				     const char *name, bool dest_uninitialized = false) {
      const bool is_oop = true;
-    if (UseCompressedOops)
-      return generate_disjoint_copy(sizeof (jint), aligned, is_oop, entry, name);
-    else
-      return generate_disjoint_copy(sizeof (jlong), aligned, is_oop, entry, name);
+    const size_t size = UseCompressedOops ? sizeof (jint) : sizeof (jlong);
+    return generate_disjoint_copy(size, aligned, is_oop, entry, name);
    }

    // Arguments:
@@ -1410,10 +1412,8 @@
  				     address nooverlap_target, address *entry,
  				     const char *name, bool dest_uninitialized = false) {
      const bool is_oop = true;
-    if (UseCompressedOops)
-      return generate_conjoint_copy(sizeof (jint), aligned, is_oop, nooverlap_target, entry, name);
-    else
-      return generate_conjoint_copy(sizeof (jlong), aligned, is_oop, nooverlap_target, entry, name);
+    const size_t size = UseCompressedOops ? sizeof (jint) : sizeof (jlong);
+    return generate_conjoint_copy(size, aligned, is_oop, nooverlap_target, entry, name);
    }


@@ -1448,8 +1448,7 @@
    //    c_rarg4   - oop ckval (super_klass)
    //
    //  Output:
-  //    r0 ==  0  -  success
-  //    r0 == -1^K - failure, where K is partial transfer count
+  //    r0        -  count of oops remaining to copy
    //
    address generate_checkcast_copy(const char *name, address *entry,
                                    bool dest_uninitialized = false) {
@@ -1459,20 +1458,14 @@
      // Input registers (after setup_arg_regs)
      const Register from        = c_rarg0;   // source array address
      const Register to          = c_rarg1;   // destination array address
-    const Register length      = c_rarg2;   // elements count
+    const Register count       = c_rarg2;   // elementscount
      const Register ckoff       = c_rarg3;   // super_check_offset
      const Register ckval       = c_rarg4;   // super_klass

-    // Registers used as temps (r16, r17, r18, r19, r20 are save-on-entry)
-    const Register end_from    = from;  // source array end address
-    const Register end_to      = r16;   // destination array end address
-    const Register count       = r20;   // -(count_remaining)
-    const Register r17_length  = r17;   // saved copy of length
-    // End pointers are inclusive, and if length is not zero they point
-    // to the last unit copied:  end_to[0] := end_from[0]
-
-    const Register copied_oop  = r18;    // actual oop copied
-    const Register r19_klass   = r19;    // oop._klass
+    // Registers used as temps (r18, r19, r20 are save-on-entry)
+    const Register start_to    = r20;       // destination array start address
+    const Register copied_oop  = r18;       // actual oop copied
+    const Register r19_klass   = r19;       // oop._klass

      //---------------------------------------------------------------
      // Assembler stub will be used for this call to arraycopy
@@ -1481,6 +1474,9 @@
      // of the source type.  Each element must be separately
      // checked.

+    assert_different_registers(from, to, count, ckoff, ckval, start_to,
+			       copied_oop, r19_klass);
+
      __ align(CodeEntryAlignment);
      StubCodeMark mark(this, "StubRoutines", name);
      address start = __ pc();
@@ -1503,7 +1499,10 @@
        BLOCK_COMMENT("Entry:");
      }

-    __ push(r16->bit() | r17->bit() | r18->bit() | r19->bit() | r20->bit(), sp);
+    // Empty array:  Nothing to do.
+    __ cbz(count, L_done);
+
+    __ push(r18->bit() | r19->bit() | r20->bit(), sp);

  #ifdef ASSERT
      BLOCK_COMMENT("assert consistent ckoff/ckval");
@@ -1511,49 +1510,36 @@
      // even though caller generates both.
      { Label L;
        int sco_offset = in_bytes(Klass::super_check_offset_offset());
-      __ ldrw(count, Address(ckval, sco_offset));
-      __ cmpw(ckoff, count);
+      __ ldrw(start_to, Address(ckval, sco_offset));
+      __ cmpw(ckoff, start_to);
        __ br(Assembler::EQ, L);
        __ stop("super_check_offset inconsistent");
        __ bind(L);
      }
  #endif //ASSERT

-    // Loop-invariant addresses.  They are exclusive end pointers.
-    Address end_from_addr(from, length, TIMES_OOP);
-    Address   end_to_addr(to,   length, TIMES_OOP);
-    // Loop-variant addresses.  They assume post-incremented count < 0.
-    Address from_element_addr(end_from, count, TIMES_OOP);
-    Address   to_element_addr(end_to,   count, TIMES_OOP);
-
-    gen_write_ref_array_pre_barrier(to, count, dest_uninitialized);
-
-    // Copy from low to high addresses, indexed from the end of each array.
-    __ lea(end_from, end_from_addr);
-    __ lea(end_to, end_to_addr);
-    __ mov(r17_length, length);        // save a copy of the length
-    __ neg(count, length);    // negate and test the length
-    __ cbnz(count, L_load_element);
-
-    // Empty array:  Nothing to do.
-    __ mov(r0, zr);                  // return 0 on (trivial) success
-    __ b(L_done);
+    // Copy from low to high addresses
+    __ mov(start_to, to);              // Save destination array start address
+    __ b(L_load_element);

      // ======== begin loop ========
      // (Loop is rotated; its entry is L_load_element.)
      // Loop control:
-    //   for (count = -count; count != 0; count++)
-    // Base pointers src, dst are biased by 8*(count-1),to last element.
+    //   for (; count != 0; count--) {
+    //     copied_oop = load_heap_oop(from++);
+    //     ... generate_type_check ...;
+    //     store_heap_oop(to++, copied_oop);
+    //   }
      __ align(OptoLoopAlignment);

      __ BIND(L_store_element);
-    __ store_heap_oop(to_element_addr, copied_oop);  // store the oop
-    __ add(count, count, 1);               // increment the count toward zero
+    __ store_heap_oop(__ post(to, UseCompressedOops ? 4 : 8), copied_oop);  // store the oop
+    __ sub(count, count, 1);
      __ cbz(count, L_do_card_marks);

      // ======== loop entry is here ========
      __ BIND(L_load_element);
-    __ load_heap_oop(copied_oop, from_element_addr); // load the oop
+    __ load_heap_oop(copied_oop, __ post(from, UseCompressedOops ? 4 : 8)); // load the oop
      __ cbz(copied_oop, L_store_element);

      __ load_klass(r19_klass, copied_oop);// query the object klass
@@ -1561,28 +1547,23 @@
      // ======== end loop ========

      // It was a real error; we must depend on the caller to finish the job.
-    // Register r0 = -1 * number of *remaining* oops, r17 = *total* oops.
+    // Register r0 = number of *remaining* oops
      // Emit GC store barriers for the oops we have copied and report
      // their number to the caller.
-    assert_different_registers(r0, r17_length, count, to, end_to, ckoff);
-    __ lea(end_to, to_element_addr);
-    __ add(end_to, end_to, -heapOopSize);      // make an inclusive end pointer
-    gen_write_ref_array_post_barrier(to, end_to, rscratch1);
-    __ add(r0, r17_length, count);                // K = (original - remaining) oops
-    __ eon(r0, r0, zr);                       // report (-1^K) to caller
-    __ b(L_done);

-    // Come here on success only.
-    __ BIND(L_do_card_marks);
-    __ add(end_to, end_to, -heapOopSize);         // make an inclusive end pointer
-    gen_write_ref_array_post_barrier(to, end_to, rscratch1);
-    __ mov(r0, zr);                  // return 0 on success
+    DEBUG_ONLY(__ nop());

      // Common exit point (success or failure).
-    __ BIND(L_done);
-    __ pop(r16->bit() | r17->bit() | r18->bit() | r19->bit() | r20->bit(), sp);
+    __ BIND(L_do_card_marks);
+    __ add(to, to, -heapOopSize);         // make an inclusive end pointer
+    gen_write_ref_array_post_barrier(start_to, to, rscratch1);
+
+    __ pop(r18->bit() | r19->bit() | r20->bit(), sp);
      inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr);
-    __ leave(); // required for proper stackwalking of RuntimeStub frame
+
+    __ bind(L_done);
+    __ mov(r0, count);                    // report count remaining to caller
+    __ leave();
      __ ret(lr);

      return start;


From aph at redhat.com  Tue Oct  1 08:18:53 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 01 Oct 2013 16:18:53 +0100
Subject: [aarch64-port-dev ] JVMTI earlyreturn support
Message-ID: <524AE7DD.5080808@redhat.com>

changeset:   5315:2ce0fb54933f
tag:         tip
user:        aph
date:        Tue Oct 01 16:17:58 2013 +0100
files:       src/cpu/aarch64/vm/interp_masm_aarch64.cpp src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp
description:
JVMTI earlyreturn support


diff -r c2d6e3b390e8 -r 2ce0fb54933f src/cpu/aarch64/vm/interp_masm_aarch64.cpp
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Tue Oct 01 15:01:30 2013 +0100
+++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Tue Oct 01 16:17:58 2013 +0100
@@ -71,12 +71,33 @@
    }
  }

+
  void InterpreterMacroAssembler::load_earlyret_value(TosState state) {
-  if (JvmtiExport::can_force_early_return()) {
-    Unimplemented();
+  ldr(r2, Address(rthread, JavaThread::jvmti_thread_state_offset()));
+  const Address tos_addr(r2, JvmtiThreadState::earlyret_tos_offset());
+  const Address oop_addr(r2, JvmtiThreadState::earlyret_oop_offset());
+  const Address val_addr(r2, JvmtiThreadState::earlyret_value_offset());
+  switch (state) {
+    case atos: ldr(r0, oop_addr);
+               str(zr, oop_addr);
+               verify_oop(r0, state);               break;
+    case ltos: ldr(r0, val_addr);                   break;
+    case btos:                                   // fall through
+    case ctos:                                   // fall through
+    case stos:                                   // fall through
+    case itos: ldrw(r0, val_addr);                  break;
+    case ftos: ldrs(v0, val_addr);                  break;
+    case dtos: ldrd(v0, val_addr);                  break;
+    case vtos: /* nothing to do */                  break;
+    default  : ShouldNotReachHere();
    }
+  // Clean up tos value in the thread object
+  movw(rscratch1, (int) ilgl);
+  strw(rscratch1, tos_addr);
+  strw(zr, val_addr);
  }

+
  void InterpreterMacroAssembler::check_and_handle_earlyret(Register java_thread) {
    if (JvmtiExport::can_force_early_return()) {
      Label L;
diff -r c2d6e3b390e8 -r 2ce0fb54933f src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp	Tue Oct 01 15:01:30 2013 +0100
+++ b/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp	Tue Oct 01 16:17:58 2013 +0100
@@ -1752,8 +1752,30 @@
  //
  // JVMTI ForceEarlyReturn support
  //
-address TemplateInterpreterGenerator::generate_earlyret_entry_for(TosState state) { __ call_Unimplemented(); return 0; }
-// end of ForceEarlyReturn support
+address TemplateInterpreterGenerator::generate_earlyret_entry_for(TosState state) {
+  address entry = __ pc();
+
+  __ restore_bcp();
+  __ restore_locals();
+  __ empty_expression_stack();
+  __ load_earlyret_value(state);
+
+  __ ldr(rscratch1, Address(rthread, JavaThread::jvmti_thread_state_offset()));
+  Address cond_addr(rscratch1, JvmtiThreadState::earlyret_state_offset());
+
+  // Clear the earlyret state
+  assert(JvmtiThreadState::earlyret_inactive == 0, "should be");
+  __ str(zr, cond_addr);
+
+  __ remove_activation(state,
+                       false, /* throw_monitor_exception */
+                       false, /* install_monitor_exception */
+                       true); /* notify_jvmdi */
+  __ ret(lr);
+
+  return entry;
+} // end of ForceEarlyReturn support
+


  //-----------------------------------------------------------------------------



From aph at redhat.com  Tue Oct  1 08:19:06 2013
From: aph at redhat.com (aph at redhat.com)
Date: Tue, 01 Oct 2013 15:19:06 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: JVMTI
	earlyreturn support
Message-ID: <20131001151911.A53CF62C4A@hg.openjdk.java.net>

Changeset: 2ce0fb54933f
Author:    aph
Date:      2013-10-01 16:17 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/2ce0fb54933f

JVMTI earlyreturn support

! src/cpu/aarch64/vm/interp_masm_aarch64.cpp
! src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp



From aph at redhat.com  Tue Oct  1 10:09:36 2013
From: aph at redhat.com (aph at redhat.com)
Date: Tue, 01 Oct 2013 17:09:36 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: Remove a little
	bogosity
Message-ID: <20131001170942.A192862C59@hg.openjdk.java.net>

Changeset: d717fbbfec8a
Author:    aph
Date:      2013-10-01 18:09 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/d717fbbfec8a

Remove a little bogosity

! src/share/vm/runtime/stubRoutines.cpp



From ed at camswl.com  Tue Oct  1 13:52:42 2013
From: ed at camswl.com (Edward Nevill)
Date: Tue, 01 Oct 2013 21:52:42 +0100
Subject: [aarch64-port-dev ] Add missing export
Message-ID: <1380660762.22275.4.camel@mint>

Add missing export in cross_compile

Ed.

--- CUT HERE ---
exporting patch:
# HG changeset patch
# User Edward Nevill edward.nevill at linaro.org
# Date 1380660897 -3600
#      Tue Oct 01 21:54:57 2013 +0100
# Node ID 60ddcc7923e7a386c2927da27bd0f7a65e960ca8
# Parent  c4e0096dad572325713409d06f19786504d7c51a
Export ALT_SDT_H

diff -r c4e0096dad57 -r 60ddcc7923e7 cross_compile
--- a/cross_compile	Fri Sep 27 15:49:31 2013 +0100
+++ b/cross_compile	Tue Oct 01 21:54:57 2013 +0100
@@ -8,5 +8,5 @@
 	fi
 mkdir -p /tmp/oe_45434e/jenkins-setup/build/tmp-eglibc
 ln -f -s $IWD/sysroots /tmp/oe_45434e/jenkins-setup/build/tmp-eglibc/
-ALT_SDT_H=$IWD/sysroots/genericarmv8/usr/include/sys/sdt.h
+export ALT_SDT_H=$IWD/sysroots/genericarmv8/usr/include/sys/sdt.h
 make STRIP_POLICY=no_strip POST_STRIP_CMD="" images
--- CUT HERE ---




From ed at camswl.com  Tue Oct  1 13:58:11 2013
From: ed at camswl.com (ed at camswl.com)
Date: Tue, 01 Oct 2013 20:58:11 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8: Export ALT_SDT_H
Message-ID: <20131001205811.99D7662C6F@hg.openjdk.java.net>

Changeset: 60ddcc7923e7
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-01 21:54 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/60ddcc7923e7

Export ALT_SDT_H

! cross_compile



From trivikram at iitj.ac.in  Thu Oct  3 05:16:24 2013
From: trivikram at iitj.ac.in (Trivikram Chaudhary)
Date: Thu, 3 Oct 2013 17:46:24 +0530
Subject: [aarch64-port-dev ] Regarding Javac
Message-ID: <CAK-Chhsm19gGnE-SNrZm43EChZbWXPtVXAXmGK2OkCCQYUV5Rw@mail.gmail.com>

Sir,
javac takes java files and produces byte code which is machine independent.
So we need not modify the work done by javac while porting. However, javac
itself has to be compiled and run on our machine to make it work but javac
source code is written in java again. How to compile that on a new
processor. Do we need to modify the source code according to architecture.
Please let me know.
Thank You


From aph at redhat.com  Thu Oct  3 05:36:38 2013
From: aph at redhat.com (Andrew Haley)
Date: Thu, 03 Oct 2013 13:36:38 +0100
Subject: [aarch64-port-dev ] Regarding Javac
In-Reply-To: <CAK-Chhsm19gGnE-SNrZm43EChZbWXPtVXAXmGK2OkCCQYUV5Rw@mail.gmail.com>
References: <CAK-Chhsm19gGnE-SNrZm43EChZbWXPtVXAXmGK2OkCCQYUV5Rw@mail.gmail.com>
Message-ID: <524D64D6.2040607@redhat.com>

On 10/03/2013 01:16 PM, Trivikram Chaudhary wrote:
> javac takes java files and produces byte code which is machine independent.
> So we need not modify the work done by javac while porting. However, javac
> itself has to be compiled and run on our machine to make it work but javac
> source code is written in java again.

Javac is a Java program  It is distributed as Java bytecode with a
small native-code loader that starts the Java virtual machine.  So,
you don't need to recompile javac.

However, you do need a Java virtual machine that will run on your
new processor.

> How to compile that on a new processor. Do we need to modify the
> source code according to architecture.

There is a (rather slow) Java virtual machine written entirely in C++.
You can use that.

Andrew.


From riku.voipio at linaro.org  Thu Oct  3 05:36:51 2013
From: riku.voipio at linaro.org (Riku Voipio)
Date: Thu, 3 Oct 2013 15:36:51 +0300
Subject: [aarch64-port-dev ] [RFC] [PATCH] replace fork syscall with
	equivalent clone
Message-ID: <CAAqcGH=8JqeKBofGTQPy0ogns9d2vD_hsURQQ0ezrxfN9wmRLw@mail.gmail.com>

Hi,

According to the man page of fork, under linux that is implemented by
clone(SIGCHLD, ..) . Calling fork system call is considered
deprecated.

The following patch is against openjdk-7 25b30 / icedtea 2.1.8 as used
in linaro openembedded overlay for building openjdk-7. I see openjdk-8
has taken a more conservative approach by defining the fork system
call number for Aarch64. While this works, I think it would be more
cleaner to use clone system call, since that is guaranteed to be
available on all linux platforms. If you disagree, then we should just
backport the openjdk-8 patch to openjdk-7.

Riku

From aph at redhat.com  Thu Oct  3 05:56:44 2013
From: aph at redhat.com (Andrew Haley)
Date: Thu, 03 Oct 2013 13:56:44 +0100
Subject: [aarch64-port-dev ] [RFC] [PATCH] replace fork syscall with
 equivalent clone
In-Reply-To: <CAAqcGH=8JqeKBofGTQPy0ogns9d2vD_hsURQQ0ezrxfN9wmRLw@mail.gmail.com>
References: <CAAqcGH=8JqeKBofGTQPy0ogns9d2vD_hsURQQ0ezrxfN9wmRLw@mail.gmail.com>
Message-ID: <524D698C.2010205@redhat.com>

On 10/03/2013 01:36 PM, Riku Voipio wrote:
> According to the man page of fork, under linux that is implemented by
> clone(SIGCHLD, ..) . Calling fork system call is considered
> deprecated.
> 
> The following patch is against openjdk-7 25b30 / icedtea 2.1.8 as used
> in linaro openembedded overlay for building openjdk-7. I see openjdk-8
> has taken a more conservative approach by defining the fork system
> call number for Aarch64. While this works, I think it would be more
> cleaner to use clone system call, since that is guaranteed to be
> available on all linux platforms. If you disagree, then we should just
> backport the openjdk-8 patch to openjdk-7.

I'm trying really hard to figure out why this matters.  BTW, there was
no patch attached.

Andrew.



From riku.voipio at linaro.org  Thu Oct  3 06:17:21 2013
From: riku.voipio at linaro.org (Riku Voipio)
Date: Thu, 3 Oct 2013 16:17:21 +0300
Subject: [aarch64-port-dev ] [RFC] [PATCH] replace fork syscall with
 equivalent clone
In-Reply-To: <524D698C.2010205@redhat.com>
References: <CAAqcGH=8JqeKBofGTQPy0ogns9d2vD_hsURQQ0ezrxfN9wmRLw@mail.gmail.com>
	<524D698C.2010205@redhat.com>
Message-ID: <CAAqcGHnzsVHKqcqizeaw5kOzzDCo6bTWyDgU9ci51qwqQ2BDCw@mail.gmail.com>

On 3 October 2013 15:56, Andrew Haley <aph at redhat.com> wrote:
> On 10/03/2013 01:36 PM, Riku Voipio wrote:
>> According to the man page of fork, under linux that is implemented by
>> clone(SIGCHLD, ..) . Calling fork system call is considered
>> deprecated.
>>
>> The following patch is against openjdk-7 25b30 / icedtea 2.1.8 as used
>> in linaro openembedded overlay for building openjdk-7. I see openjdk-8
>> has taken a more conservative approach by defining the fork system
>> call number for Aarch64. While this works, I think it would be more
>> cleaner to use clone system call, since that is guaranteed to be
>> available on all linux platforms. If you disagree, then we should just
>> backport the openjdk-8 patch to openjdk-7.
>
> I'm trying really hard to figure out why this matters.  BTW, there was
> no patch attached.

Less lines of code and less arch specific ifdefs, mainly.

I guess the mailing list scrubbed it. The patch is also viewable from here:

https://git.linaro.org/gitweb?p=openembedded/meta-linaro.git;a=blob_plain;f=meta-aarch64/recipes-core/openjdk/files/icedtea-openjdk-aarch64.patch

Riku


From aph at redhat.com  Thu Oct  3 06:41:50 2013
From: aph at redhat.com (Andrew Haley)
Date: Thu, 03 Oct 2013 14:41:50 +0100
Subject: [aarch64-port-dev ] [RFC] [PATCH] replace fork syscall with
 equivalent clone
In-Reply-To: <CAAqcGHnzsVHKqcqizeaw5kOzzDCo6bTWyDgU9ci51qwqQ2BDCw@mail.gmail.com>
References: <CAAqcGH=8JqeKBofGTQPy0ogns9d2vD_hsURQQ0ezrxfN9wmRLw@mail.gmail.com>
	<524D698C.2010205@redhat.com>
	<CAAqcGHnzsVHKqcqizeaw5kOzzDCo6bTWyDgU9ci51qwqQ2BDCw@mail.gmail.com>
Message-ID: <524D741E.7020609@redhat.com>

On 10/03/2013 02:17 PM, Riku Voipio wrote:
> On 3 October 2013 15:56, Andrew Haley <aph at redhat.com> wrote:
>> On 10/03/2013 01:36 PM, Riku Voipio wrote:
>>> According to the man page of fork, under linux that is implemented by
>>> clone(SIGCHLD, ..) . Calling fork system call is considered
>>> deprecated.
>>>
>>> The following patch is against openjdk-7 25b30 / icedtea 2.1.8 as used
>>> in linaro openembedded overlay for building openjdk-7. I see openjdk-8
>>> has taken a more conservative approach by defining the fork system
>>> call number for Aarch64. While this works, I think it would be more
>>> cleaner to use clone system call, since that is guaranteed to be
>>> available on all linux platforms. If you disagree, then we should just
>>> backport the openjdk-8 patch to openjdk-7.
>>
>> I'm trying really hard to figure out why this matters.  BTW, there was
>> no patch attached.
> 
> Less lines of code and less arch specific ifdefs, mainly.
> 
> I guess the mailing list scrubbed it. The patch is also viewable from here:
> 
> https://git.linaro.org/gitweb?p=openembedded/meta-linaro.git;a=blob_plain;f=meta-aarch64/recipes-core/openjdk/files/icedtea-openjdk-aarch64.patch

That patch seems not to have anything to do with Aarch64.

Andrew.




From edward.nevill at linaro.org  Thu Oct  3 06:55:58 2013
From: edward.nevill at linaro.org (Edward Nevill)
Date: Thu, 03 Oct 2013 14:55:58 +0100
Subject: [aarch64-port-dev ] [RFC] [PATCH] replace fork syscall with
 equivalent clone
In-Reply-To: <CAAqcGHnzsVHKqcqizeaw5kOzzDCo6bTWyDgU9ci51qwqQ2BDCw@mail.gmail.com>
References: <CAAqcGH=8JqeKBofGTQPy0ogns9d2vD_hsURQQ0ezrxfN9wmRLw@mail.gmail.com>
	<524D698C.2010205@redhat.com>
	<CAAqcGHnzsVHKqcqizeaw5kOzzDCo6bTWyDgU9ci51qwqQ2BDCw@mail.gmail.com>
Message-ID: <1380808558.16277.13.camel@localhost.localdomain>


On Thu, 2013-10-03 at 16:17 +0300, Riku Voipio wrote:
> On 3 October 2013 15:56, Andrew Haley <aph at redhat.com> wrote:
> > On 10/03/2013 01:36 PM, Riku Voipio wrote:
> >> The following patch is against openjdk-7 25b30 / icedtea 2.1.8 as used
> >> in linaro openembedded overlay for building openjdk-7. I see openjdk-8
> >> has taken a more conservative approach by defining the fork system
> >> call number for Aarch64. While this works, I think it would be more
> >> cleaner to use clone system call, since that is guaranteed to be
> >> available on all linux platforms. If you disagree, then we should just
> >> backport the openjdk-8 patch to openjdk-7.
> >
> > I'm trying really hard to figure out why this matters.  BTW, there was
> > no patch attached.
> 
> Less lines of code and less arch specific ifdefs, mainly.
> https://git.linaro.org/gitweb?p=openembedded/meta-linaro.git;a=blob_plain;f=meta-aarch64/recipes-core/openjdk/files/icedtea-openjdk-aarch64.patch

Hi Riku,

Thanks for this. Yes I agree that the current sequence of architecture
specific conditions is a bit of a mess and just using SYS_clone is
neater.

However, the tip of OpenJDK8 currently does it this way and it is very
difficult to get patches pushed into the tip of OpenJDK8.

Therefore I have just followed what was done before and defined the fork
nos for aarch64.

We could change the aarch64 branch to just use SYS_clone and then when
it comes time to merge with the OpenJDK8 tip review this and see if they
will accept this. Maybe this piece of code would have already been fixed
by such time.

Do you plan to propose a patch against the OpenJDK7 tip for these
changes. If the changes were accepted in OpenJDK7 then accepting them in
OpenJDK8 would be pretty automatic.

Andrew: Do you want me to make these changes (with a suitable comment)
as an aide memoir when we come to merger with OpenJDK8 tip. Or just
leave as is?

All the best,
Ed.




From aph at redhat.com  Thu Oct  3 07:25:38 2013
From: aph at redhat.com (Andrew Haley)
Date: Thu, 03 Oct 2013 15:25:38 +0100
Subject: [aarch64-port-dev ] [RFC] [PATCH] replace fork syscall with
 equivalent clone
In-Reply-To: <1380808558.16277.13.camel@localhost.localdomain>
References: <CAAqcGH=8JqeKBofGTQPy0ogns9d2vD_hsURQQ0ezrxfN9wmRLw@mail.gmail.com>
	<524D698C.2010205@redhat.com>
	<CAAqcGHnzsVHKqcqizeaw5kOzzDCo6bTWyDgU9ci51qwqQ2BDCw@mail.gmail.com>
	<1380808558.16277.13.camel@localhost.localdomain>
Message-ID: <524D7E62.9030406@redhat.com>

On 10/03/2013 02:55 PM, Edward Nevill wrote:
> 
> On Thu, 2013-10-03 at 16:17 +0300, Riku Voipio wrote:
>> On 3 October 2013 15:56, Andrew Haley <aph at redhat.com> wrote:
>>> On 10/03/2013 01:36 PM, Riku Voipio wrote:
>>>> The following patch is against openjdk-7 25b30 / icedtea 2.1.8 as used
>>>> in linaro openembedded overlay for building openjdk-7. I see openjdk-8
>>>> has taken a more conservative approach by defining the fork system
>>>> call number for Aarch64. While this works, I think it would be more
>>>> cleaner to use clone system call, since that is guaranteed to be
>>>> available on all linux platforms. If you disagree, then we should just
>>>> backport the openjdk-8 patch to openjdk-7.
>>>
>>> I'm trying really hard to figure out why this matters.  BTW, there was
>>> no patch attached.
>>
>> Less lines of code and less arch specific ifdefs, mainly.
>> https://git.linaro.org/gitweb?p=openembedded/meta-linaro.git;a=blob_plain;f=meta-aarch64/recipes-core/openjdk/files/icedtea-openjdk-aarch64.patch
> 
> Thanks for this. Yes I agree that the current sequence of architecture
> specific conditions is a bit of a mess and just using SYS_clone is
> neater.
> 
> However, the tip of OpenJDK8 currently does it this way and it is very
> difficult to get patches pushed into the tip of OpenJDK8.
> 
> Therefore I have just followed what was done before and defined the fork
> nos for aarch64.
> 
> We could change the aarch64 branch to just use SYS_clone and then when
> it comes time to merge with the OpenJDK8 tip review this and see if they
> will accept this. Maybe this piece of code would have already been fixed
> by such time.
> 
> Do you plan to propose a patch against the OpenJDK7 tip for these
> changes. If the changes were accepted in OpenJDK7 then accepting them in
> OpenJDK8 would be pretty automatic.
> 
> Andrew: Do you want me to make these changes (with a suitable comment)
> as an aide memoir when we come to merger with OpenJDK8 tip. Or just
> leave as is?

It's a divergence from upstream that affects all arches.  It's being done
for the sake of tidiness.  I say we revisit this at some time in the future.
I would accept a change surrounded by #ifdef AARCH64 that does not touch
existing code.

Andrew.



From adinn at redhat.com  Fri Oct  4 04:46:27 2013
From: adinn at redhat.com (adinn at redhat.com)
Date: Fri, 04 Oct 2013 11:46:27 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: 2 new changesets
Message-ID: <20131004114641.7125562D6B@hg.openjdk.java.net>

Changeset: 54d593948b41
Author:    adinn
Date:      2013-10-04 12:44 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/54d593948b41

fix compare long against immediate to pass case for 0 into correct branch

was planting cmn rn, 0 instead of cmp rn, 0

! src/cpu/aarch64/vm/aarch64.ad

Changeset: c1ee24843b4b
Author:    adinn
Date:      2013-10-04 12:45 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/c1ee24843b4b

Merge




From adinn at redhat.com  Fri Oct  4 05:17:54 2013
From: adinn at redhat.com (adinn at redhat.com)
Date: Fri, 04 Oct 2013 12:17:54 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: corrected
	compare of long reg value to	a long immediate which cannot be
	inlined
Message-ID: <20131004121800.3ABF662D6F@hg.openjdk.java.net>

Changeset: 2a22f57aad36
Author:    adinn
Date:      2013-10-04 13:16 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/2a22f57aad36

corrected compare of long reg value to a long immediate which cannot be inlined

was wrongly using movw and cmpw

! src/cpu/aarch64/vm/aarch64.ad



From adinn at redhat.com  Fri Oct  4 09:40:55 2013
From: adinn at redhat.com (Andrew Dinn)
Date: Fri, 04 Oct 2013 17:40:55 +0100
Subject: [aarch64-port-dev ] C2 error on ARM sim only regardingcall to
 runtime from non-compiled code
Message-ID: <524EEF97.3070701@redhat.com>

When running on the ARM sim Ed found that routine check_compiled_frame
throws an error claiming that a call out to the runtime is occuring from
a non-compiler generated address. This happens when a stub enters the
runtime from one fo the optoRuntime stubs (see opto/runtime.cpp). These
stubs save only the stack pointer in the thread's frame anchor i.e
_anchor.last_Java_sp==0xfff..... but _anchor.last_Java_fp==0x0 and
_anchor.last_Java_pc=0x0.

Now check_compiled_frame relies on thread->last_frame() to identify the
start of the Java frame chain. It uses frame::frame(long sp, long fp) to
create the frame.

If fp is 0 then the frame code picks up the pc by evaluating sp[-1].
i.e. it assumes that the VM (C) function called from the stub will
create a frame just above (negatively) the saved stack pointer with the
return PC in its first (64-bit) word. This allows the code buffer to be
retrieved and thence the frame size. This always works on x86 since the
hw call pushes the return address.

On our sim this is not true by default -- recall our blrt call is
actually handled a callout from the sim.  When transitioning from
simulator execution to x86 code we push some intermediate data on the
Java thread stack before entering the called routine via a linking
function which also switches stacks. So, I fiddled things by pushing LR
and a magic word (0xdeadbede) onto the Java thread stack before pushing
the transition data and then entering the x86-compiled C function.

Ok, so here's the terrible confession! I just assumed that on the real
hardware when calling the C code directly from the stub the compiled
routine would build a frame with lr and sp as its first two elements.
That's what we do when building a Java frame. Alas, this is not a valid
assumption.

The first callout I encounter when running on the real hardware is to
OptoRuntime::new_array_nozero_C which is called from the C2 generated
new_array_nozero_Java stub. DIsassembly reveals the following

(gdb) x/i OptoRuntime::new_array_nozero_C
   0x7fb79f1f10 <OptoRuntime::new_array_nozero_C(Klass*, int,
JavaThread*)>:  stp      x29, x30, [sp,#-128]!

i.e the return address is at offset 128. This is rather unfortunate
because looking at some of the other stubs we have e.g.

(gdb) x/i OptoRuntime::multianewarray2_C
   0x7fb79f2948 <OptoRuntime::multianewarray2_C(Klass*, int, int,
JavaThread*)>:       stp     x29, x30, [sp,#-80]!
(gdb)  x/i OptoRuntime::multianewarray3_C
   0x7fb79f2d70 <OptoRuntime::multianewarray3_C(Klass*, int, int, int,
JavaThread*)>:  stp     x29, x30, [sp,#-112]!
(gdb)

. . .

In other words the return address is not at a fixed offset from SP. So,
we cannot use this trick to identify the frame's code buffer and hence
it's size.

I think it may be possible to fix this by making the OptoRuntime stubs
write the current PC to the thread anchor. I am not certain why the C2
stubs don't only write SP. The stubs are generated by building the
required ideal graph and it looks to me like ideal code is not able to
express what is needed i.e. loading the current code address in to a
register as a constant. So, this may be why the stub leaves it to the
call routine and the frame code to obtain the callee code address.
Alternatively, it may just have been omitted because loading via sp[-1]
is cheaper and quicker. I'll post when I find out more.

regards,


Andrew Dinn
-----------



From aph at redhat.com  Fri Oct  4 10:05:26 2013
From: aph at redhat.com (Andrew Haley)
Date: Fri, 04 Oct 2013 18:05:26 +0100
Subject: [aarch64-port-dev ] C2 error on ARM sim only regardingcall to
 runtime from non-compiled code
In-Reply-To: <524EEF97.3070701@redhat.com>
References: <524EEF97.3070701@redhat.com>
Message-ID: <524EF556.4090802@redhat.com>

On 10/04/2013 05:40 PM, Andrew Dinn wrote:
> (gdb) x/i OptoRuntime::new_array_nozero_C
>    0x7fb79f1f10 <OptoRuntime::new_array_nozero_C(Klass*, int,
> JavaThread*)>:  stp      x29, x30, [sp,#-128]!
> 
> i.e the return address is at offset 128. 

No it's not.  That's a predecrement with a writeback.

Andrew.



From adinn at redhat.com  Fri Oct  4 10:16:37 2013
From: adinn at redhat.com (Andrew Dinn)
Date: Fri, 04 Oct 2013 18:16:37 +0100
Subject: [aarch64-port-dev ] C2 error on ARM sim only regardingcall to
 runtime from non-compiled code
In-Reply-To: <524EF556.4090802@redhat.com>
References: <524EEF97.3070701@redhat.com> <524EF556.4090802@redhat.com>
Message-ID: <524EF7F5.6070505@redhat.com>



On 04/10/13 18:05, Andrew Haley wrote:
> On 10/04/2013 05:40 PM, Andrew Dinn wrote:
>> (gdb) x/i OptoRuntime::new_array_nozero_C
>>    0x7fb79f1f10 <OptoRuntime::new_array_nozero_C(Klass*, int,
>> JavaThread*)>:  stp      x29, x30, [sp,#-128]!
>>
>> i.e the return address is at offset 128. 
> 
> No it's not.  That's a predecrement with a writeback.

Hmm, not sure what the objection is here unless its that I omitted the
direction of my 128.

On Intel x29 is written at offset -8 (bytes) from the SP value in the
anchor -- equivalently, offset 8 bytes from the value of SP when the
routine is called.

That's where the frame code expects it (i evaluates _anchor._sp[-1]).

The above instruction writes x29 at offset -128 bytes from the value of
SP when the routine is called i.e. not where the frame code expects it.

regards,


Andrew Dinn
-----------



From aph at redhat.com  Fri Oct  4 10:21:41 2013
From: aph at redhat.com (Andrew Haley)
Date: Fri, 04 Oct 2013 18:21:41 +0100
Subject: [aarch64-port-dev ] C2 error on ARM sim only regardingcall to
 runtime from non-compiled code
In-Reply-To: <524EF7F5.6070505@redhat.com>
References: <524EEF97.3070701@redhat.com> <524EF556.4090802@redhat.com>
	<524EF7F5.6070505@redhat.com>
Message-ID: <524EF925.4010304@redhat.com>

On 10/04/2013 06:16 PM, Andrew Dinn wrote:
> 
> 
> On 04/10/13 18:05, Andrew Haley wrote:
>> On 10/04/2013 05:40 PM, Andrew Dinn wrote:
>>> (gdb) x/i OptoRuntime::new_array_nozero_C
>>>    0x7fb79f1f10 <OptoRuntime::new_array_nozero_C(Klass*, int,
>>> JavaThread*)>:  stp      x29, x30, [sp,#-128]!
>>>
>>> i.e the return address is at offset 128. 
>>
>> No it's not.  That's a predecrement with a writeback.
> 
> Hmm, not sure what the objection is here unless its that I omitted the
> direction of my 128.

Just sayin' that after that instruction executes, the return address
is just above the SP, not at offset 128.

> On Intel x29 is written at offset -8 (bytes) from the SP value in the
> anchor -- equivalently, offset 8 bytes from the value of SP when the
> routine is called.
> 
> That's where the frame code expects it (i evaluates _anchor._sp[-1]).
> 
> The above instruction writes x29 at offset -128 bytes from the value of
> SP when the routine is called i.e. not where the frame code expects it.

Sure, I get that.

Andrew.




From adinn at redhat.com  Fri Oct  4 10:27:45 2013
From: adinn at redhat.com (Andrew Dinn)
Date: Fri, 04 Oct 2013 18:27:45 +0100
Subject: [aarch64-port-dev ] C2 error on ARM sim only regardingcall to
 runtime from non-compiled code
In-Reply-To: <524EF925.4010304@redhat.com>
References: <524EEF97.3070701@redhat.com> <524EF556.4090802@redhat.com>
	<524EF7F5.6070505@redhat.com> <524EF925.4010304@redhat.com>
Message-ID: <524EFA91.5000906@redhat.com>

On 04/10/13 18:21, Andrew Haley wrote:
> On 10/04/2013 06:16 PM, Andrew Dinn wrote:
>>
>>
>> On 04/10/13 18:05, Andrew Haley wrote:
>>> On 10/04/2013 05:40 PM, Andrew Dinn wrote:
>>>> (gdb) x/i OptoRuntime::new_array_nozero_C
>>>>    0x7fb79f1f10 <OptoRuntime::new_array_nozero_C(Klass*, int,
>>>> JavaThread*)>:  stp      x29, x30, [sp,#-128]!
>>>>
>>>> i.e the return address is at offset 128. 
>>>
>>> No it's not.  That's a predecrement with a writeback.
>>
>> Hmm, not sure what the objection is here unless its that I omitted the
>> direction of my 128.
> 
> Just sayin' that after that instruction executes, the return address
> is just above the SP, not at offset 128.

Ah, ok, you are looking at this half empty glass from below (i.e. sp
after it been decremented) whereas I am looking at it from above (i.e.
sp before it has been decremented).

>> On Intel x29 is written at offset -8 (bytes) from the SP value in the
>> anchor -- equivalently, offset 8 bytes from the value of SP when the
>> routine is called.

 of course that second 8 should have been -8

>> That's where the frame code expects it (i evaluates _anchor._sp[-1]).
>>
>> The above instruction writes x29 at offset -128 bytes from the value of
>> SP when the routine is called i.e. not where the frame code expects it.
> 
> Sure, I get that.

Ok, good.

regards,


Andrew Dinn
-----------



From aph at redhat.com  Wed Oct  9 05:47:44 2013
From: aph at redhat.com (Andrew Haley)
Date: Wed, 09 Oct 2013 13:47:44 +0100
Subject: [aarch64-port-dev ] Simplify memory barrier generation
Message-ID: <52555070.7060004@redhat.com>

This patch doesn't make memory barriers any different, it just makes them
easier to read and write.  Now, you can just say something like

    membar(Assembler::StoreStore|Assembler::StoreLoad);

Andrew.


# HG changeset patch
# User aph
# Date 1380807225 -3600
# Node ID 1b73f7fb6f30402ed55ac131125d5d9d28a9c710
# Parent  2a22f57aad360e0e2d615da94e0bff2a98fe9ea2
Simplify memory barrier generation

diff -r 2a22f57aad36 -r 1b73f7fb6f30 src/cpu/aarch64/vm/assembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp	Fri Oct 04 13:16:35 2013 +0100
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp	Thu Oct 03 14:33:45 2013 +0100
@@ -995,6 +995,19 @@
     system(0b01, 0b011, 0b0111, 0b0101, 0b001, Rt);
   }

+  // A more convenient access to dmb for our purposes
+  enum Membar_mask_bits {
+    StoreStore = ST,
+    LoadStore  = LD,
+    LoadLoad   = LD,
+    StoreLoad  = SY,
+    AnyAny     = SY
+  };
+
+  void membar(Membar_mask_bits order_constraint) {
+    dmb(Assembler::barrier(order_constraint));
+  }
+
   // Unconditional branch (register)
   void branch_reg(Register R, int opc) {
     starti;
diff -r 2a22f57aad36 -r 1b73f7fb6f30 src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Fri Oct 04 13:16:35 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Thu Oct 03 14:33:45 2013 +0100
@@ -2883,10 +2883,10 @@

 void LIR_Assembler::membar() {
   COMMENT("membar");
-  __ dsb(__ SY);
+  __ membar(MacroAssembler::AnyAny);
 }

-void LIR_Assembler::membar_acquire() {
+void LIR_Assembler::membar_acquire() {
   __ block_comment("membar_acquire");
 }

@@ -2898,7 +2898,7 @@

 void LIR_Assembler::membar_storestore() {
   COMMENT("membar_storestore");
-  __ dsb(__ ST);
+  __ membar(MacroAssembler::StoreStore);
 }

 void LIR_Assembler::membar_loadstore() { Unimplemented(); }
diff -r 2a22f57aad36 -r 1b73f7fb6f30 src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Fri Oct 04 13:16:35 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Thu Oct 03 14:33:45 2013 +0100
@@ -1331,30 +1331,6 @@
     Label*   retaddr = NULL
   );

-  enum Membar_mask_bits {
-    StoreStore = 1 << 3,
-    LoadStore  = 1 << 2,
-    StoreLoad  = 1 << 1,
-    LoadLoad   = 1 << 0
-  };
-
-  void membar(Membar_mask_bits order_constraint) {
-    // LD     Load-Load, Load-Store
-    // ST     Store-Store
-    // SY     Any-Any
-
-    // Handle simple cases first
-    if (order_constraint == StoreStore) {
-      dsb(ST);
-    } else if (order_constraint == LoadLoad
-	|| order_constraint == LoadStore
-	|| order_constraint == (LoadLoad | LoadStore)) {
-      dsb(LD);
-    } else {
-      dsb(SY);
-    }
-  }
-
   void ldr_constant(Register dest, address const_addr) {
     guarantee(const_addr, "constant pool overflow");
     if (NearCpool) {


From aph at redhat.com  Wed Oct  9 05:48:53 2013
From: aph at redhat.com (Andrew Haley)
Date: Wed, 09 Oct 2013 13:48:53 +0100
Subject: [aarch64-port-dev ] C1: Correct half word types in loads and stores
Message-ID: <525550B5.4080000@redhat.com>

We were writing halfword types wit the wrong modes.

Andrew.


# HG changeset patch
# User aph
# Date 1381309495 -3600
# Node ID 5db717e716d938bccf57ddd9558c66b9b14d56c8
# Parent  1b73f7fb6f30402ed55ac131125d5d9d28a9c710
Correct half word types in loads and stores

diff -r 1b73f7fb6f30 -r 5db717e716d9 src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Thu Oct 03 14:33:45 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Wed Oct 09 10:04:55 2013 +0100
@@ -2756,7 +2756,7 @@

       case T_CHAR:    // fall through
       case T_SHORT:
-	__ stlrw(src->as_register(), rscratch1);
+	__ stlrh(src->as_register(), rscratch1);
 	break;

       default:
@@ -2802,7 +2802,7 @@

     case T_CHAR:    // fall through
     case T_SHORT:
-      __ ldarw(dest->as_register(), rscratch1);
+      __ ldarh(dest->as_register(), rscratch1);
       break;

     case T_FLOAT:


From aph at redhat.com  Wed Oct  9 05:51:31 2013
From: aph at redhat.com (Andrew Haley)
Date: Wed, 09 Oct 2013 13:51:31 +0100
Subject: [aarch64-port-dev ] C2: Use ldar and stlr for volatile fields
Message-ID: <52555153.2090601@redhat.com>

We don't need to generate explicit barriers for volatile fields.

Instead, we can use ldar and stlr ; dmb for accesses.  This patch adds
all the patters needed for volatile field accesses.

I had to define MemNode::is_volatile() in the shared C2 code.

Andrew.


# HG changeset patch
# User aph
# Date 1381321967 -3600
# Node ID 557a6ed9e5d03270183926ca313ea72cce2896cf
# Parent  5db717e716d938bccf57ddd9558c66b9b14d56c8
C2: Handle volatile fields by generating ldar and stlr instructions.
Define instruct patterns for all volatile variants.
Define enc patterns for all variants.
Predicate non-volatile field accesses with !((MemNode*)n)->is_volatile().
Define MemNode::is_volatile() for use in predicates.

diff -r 5db717e716d9 -r 557a6ed9e5d0 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 09 10:04:55 2013 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 09 13:32:47 2013 +0100
@@ -1755,6 +1755,23 @@
   }
 }

+#define MOV_VOLATILE(REG, BASE, INDEX, SCALE, DISP, SCRATCH, INSN)	\
+  MacroAssembler _masm(&cbuf);						\
+  {									\
+    Register base = as_Register(BASE);					\
+    if (INDEX == -1) {							\
+	__ lea(SCRATCH, Address(base, DISP));				\
+    } else {								\
+	Register index_reg = as_Register(INDEX);			\
+	if (DISP == 0) {						\
+	  __ lea(SCRATCH, Address(base, index_reg, Address::lsl(SCALE))); \
+	} else {							\
+	  __ lea(SCRATCH, Address(base, DISP));				\
+	  __ lea(SCRATCH, Address(SCRATCH, index_reg, Address::lsl(SCALE))); \
+	}								\
+    }									\
+    __ INSN(REG, SCRATCH);						\
+  }
 %}

 //----------ENCODING BLOCK-----------------------------------------------------
@@ -2255,6 +2272,234 @@
     }
   %}

+  // volatile loads and stores
+
+  enc_class aarch64_enc_ldarsbw(iRegI dst, memory mem) %{
+    Register dst_reg = as_Register($dst$$reg);
+    MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarb);
+    __ sxtbw(dst_reg, dst_reg);
+  %}
+
+  enc_class aarch64_enc_ldarsb(iRegL dst, memory mem) %{
+    Register dst_reg = as_Register($dst$$reg);
+    MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarb);
+    __ sxtb(dst_reg, dst_reg);
+  %}
+
+  enc_class aarch64_enc_ldarbw(iRegI dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarb);
+  %}
+
+  enc_class aarch64_enc_ldarb(iRegL dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarb);
+  %}
+
+  enc_class aarch64_enc_ldarshw(iRegI dst, memory mem) %{
+    Register dst_reg = as_Register($dst$$reg);
+    MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarh);
+    __ sxthw(dst_reg, dst_reg);
+  %}
+
+  enc_class aarch64_enc_ldarsh(iRegL dst, memory mem) %{
+    Register dst_reg = as_Register($dst$$reg);
+    MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarh);
+    __ sxth(dst_reg, dst_reg);
+  %}
+
+  enc_class aarch64_enc_ldarhw(iRegI dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarh);
+  %}
+
+  enc_class aarch64_enc_ldarh(iRegL dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarh);
+  %}
+
+  enc_class aarch64_enc_ldarw(iRegI dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarw);
+  %}
+
+  enc_class aarch64_enc_ldarw(iRegL dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarw);
+  %}
+
+  enc_class aarch64_enc_ldar(iRegL dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldar);
+  %}
+
+  enc_class aarch64_enc_fldars(vRegF dst, memory mem) %{
+    MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarw);
+    __ fmovs(as_FloatRegister($dst$$reg), rscratch1);
+  %}
+
+  enc_class aarch64_enc_fldard(vRegD dst, memory mem) %{
+    MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldar);
+    __ fmovd(as_FloatRegister($dst$$reg), rscratch1);
+  %}
+  enc_class aarch64_enc_stlrb(iRegI src, memory mem) %{
+    MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+		 rscratch1, stlrb);
+  %}
+
+  enc_class aarch64_enc_stlrh(iRegI src, memory mem) %{
+    MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+		 rscratch1, stlrh);
+  %}
+
+  enc_class aarch64_enc_stlrw(iRegI src, memory mem) %{
+    MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+		 rscratch1, stlrw);
+  %}
+
+
+  enc_class aarch64_enc_ldarsbw(iRegI dst, memory mem) %{
+    Register dst_reg = as_Register($dst$$reg);
+    MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarb);
+    __ sxtbw(dst_reg, dst_reg);
+  %}
+
+  enc_class aarch64_enc_ldarsb(iRegL dst, memory mem) %{
+    Register dst_reg = as_Register($dst$$reg);
+    MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarb);
+    __ sxtb(dst_reg, dst_reg);
+  %}
+
+  enc_class aarch64_enc_ldarbw(iRegI dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarb);
+  %}
+
+  enc_class aarch64_enc_ldarb(iRegL dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarb);
+  %}
+
+  enc_class aarch64_enc_ldarshw(iRegI dst, memory mem) %{
+    Register dst_reg = as_Register($dst$$reg);
+    MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarh);
+    __ sxthw(dst_reg, dst_reg);
+  %}
+
+  enc_class aarch64_enc_ldarsh(iRegL dst, memory mem) %{
+    Register dst_reg = as_Register($dst$$reg);
+    MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarh);
+    __ sxth(dst_reg, dst_reg);
+  %}
+
+  enc_class aarch64_enc_ldarhw(iRegI dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarh);
+  %}
+
+  enc_class aarch64_enc_ldarh(iRegL dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarh);
+  %}
+
+  enc_class aarch64_enc_ldarw(iRegI dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarw);
+  %}
+
+  enc_class aarch64_enc_ldarw(iRegL dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarw);
+  %}
+
+  enc_class aarch64_enc_ldar(iRegL dst, memory mem) %{
+    MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldar);
+  %}
+
+  enc_class aarch64_enc_fldars(vRegF dst, memory mem) %{
+    MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldarw);
+    __ fmovs(as_FloatRegister($dst$$reg), rscratch1);
+  %}
+
+  enc_class aarch64_enc_fldard(vRegD dst, memory mem) %{
+    MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+	     rscratch1, ldar);
+    __ fmovd(as_FloatRegister($dst$$reg), rscratch1);
+  %}
+
+  enc_class aarch64_enc_stlr(iRegL src, memory mem) %{
+    Register src_reg = as_Register($src$$reg);
+    // we sometimes get asked to store the stack pointer into the
+    // current thread -- we cannot do that directly on AArch64
+    if (src_reg == r31_sp) {
+ 	MacroAssembler _masm(&cbuf);
+      assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
+      __ mov(rscratch2, sp);
+      src_reg = rscratch2;
+    }
+    MOV_VOLATILE(src_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+		 rscratch1, stlr);
+  %}
+
+  enc_class aarch64_enc_fstlrs(vRegF src, memory mem) %{
+    {
+      MacroAssembler _masm(&cbuf);
+      FloatRegister src_reg = as_FloatRegister($src$$reg);
+      __ fmovs(rscratch2, src_reg);
+    }
+    MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+		 rscratch1, stlrw);
+  %}
+
+  enc_class aarch64_enc_fstlrd(vRegD src, memory mem) %{
+    {
+      MacroAssembler _masm(&cbuf);
+      FloatRegister src_reg = as_FloatRegister($src$$reg);
+      __ fmovd(rscratch2, src_reg);
+    }
+    MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+		 rscratch1, stlr);
+  %}
+
+  enc_class aarch64_enc_stlrw_immn(immN src, memory mem) %{
+    {
+      MacroAssembler _masm(&cbuf);
+      address con = (address)$src$$constant;
+      // need to do this the hard way until we can manage relocs
+      // for 32 bit constants
+      __ movoop(rscratch2, (jobject)con);
+      __ encode_heap_oop_not_null(rscratch2);
+    }
+    MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+		 rscratch1, stlrw);
+  %}
+
+  enc_class aarch64_enc_stlrw_immnk(immN src, memory mem) %{
+    {
+      MacroAssembler _masm(&cbuf);
+      address con = (address)$src$$constant;
+      // need to do this the hard way until we can manage relocs
+      // for 32 bit constants
+      __ movoop(rscratch2, (jobject)con);
+      __ encode_heap_oop_not_null(rscratch2);
+      __ encode_klass_not_null(rscratch2);
+    }
+    MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
+		 rscratch1, stlrw);
+  %}
+
   // synchronized read/update encodings

   enc_class aarch64_enc_ldaxr(iRegL dst, memory mem) %{
@@ -2934,7 +3179,7 @@
     }

     // Set displaced_header to be (markOop of object | UNLOCK_VALUE).
-    __ orrw(disp_hdr, disp_hdr, markOopDesc::unlocked_value);
+    __ orr(disp_hdr, disp_hdr, markOopDesc::unlocked_value);

     // Load Compare Value application register.

@@ -4229,6 +4474,7 @@
 instruct loadB(iRegINoSp dst, memory mem)
 %{
   match(Set dst (LoadB mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrsbw  $dst, $mem\t# byte" %}
@@ -4242,6 +4488,7 @@
 instruct loadB2L(iRegLNoSp dst, memory mem)
 %{
   match(Set dst (ConvI2L (LoadB mem)));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrsb  $dst, $mem\t# byte" %}
@@ -4255,6 +4502,7 @@
 instruct loadUB(iRegINoSp dst, memory mem)
 %{
   match(Set dst (LoadUB mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrbw  $dst, $mem\t# byte" %}
@@ -4268,6 +4516,7 @@
 instruct loadUB2L(iRegLNoSp dst, memory mem)
 %{
   match(Set dst (ConvI2L (LoadUB mem)));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrb  $dst, $mem\t# byte" %}
@@ -4281,6 +4530,7 @@
 instruct loadS(iRegINoSp dst, memory mem)
 %{
   match(Set dst (LoadS mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrshw  $dst, $mem\t# short" %}
@@ -4294,6 +4544,7 @@
 instruct loadS2L(iRegLNoSp dst, memory mem)
 %{
   match(Set dst (ConvI2L (LoadS mem)));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrsh  $dst, $mem\t# short" %}
@@ -4307,6 +4558,7 @@
 instruct loadUS(iRegINoSp dst, memory mem)
 %{
   match(Set dst (LoadUS mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrhw  $dst, $mem\t# short" %}
@@ -4320,6 +4572,7 @@
 instruct loadUS2L(iRegLNoSp dst, memory mem)
 %{
   match(Set dst (ConvI2L (LoadUS mem)));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrh  $dst, $mem\t# short" %}
@@ -4333,6 +4586,7 @@
 instruct loadI(iRegINoSp dst, memory mem)
 %{
   match(Set dst (LoadI mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrw  $dst, $mem\t# int" %}
@@ -4346,6 +4600,7 @@
 instruct loadI2L(iRegLNoSp dst, memory mem)
 %{
   match(Set dst (ConvI2L (LoadI mem)));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrsw  $dst, $mem\t# int" %}
@@ -4359,6 +4614,7 @@
 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
 %{
   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrw  $dst, $mem\t# int" %}
@@ -4372,6 +4628,7 @@
 instruct loadL(iRegLNoSp dst, memory mem)
 %{
   match(Set dst (LoadL mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldr  $dst, $mem\t# int" %}
@@ -4398,6 +4655,7 @@
 instruct loadP(iRegPNoSp dst, memory mem)
 %{
   match(Set dst (LoadP mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldr  $dst, $mem\t# ptr" %}
@@ -4411,6 +4669,7 @@
 instruct loadN(iRegNNoSp dst, memory mem)
 %{
   match(Set dst (LoadN mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrw  $dst, $mem\t# compressed ptr" %}
@@ -4424,6 +4683,7 @@
 instruct loadKlass(iRegPNoSp dst, memory mem)
 %{
   match(Set dst (LoadKlass mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldr  $dst, $mem\t# class" %}
@@ -4437,6 +4697,7 @@
 instruct loadNKlass(iRegNNoSp dst, memory mem)
 %{
   match(Set dst (LoadNKlass mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrw  $dst, $mem\t# compressed class ptr" %}
@@ -4450,6 +4711,7 @@
 instruct loadF(vRegF dst, memory mem)
 %{
   match(Set dst (LoadF mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrs  $dst, $mem\t# float" %}
@@ -4463,6 +4725,7 @@
 instruct loadD(vRegD dst, memory mem)
 %{
   match(Set dst (LoadD mem));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "ldrd  $dst, $mem\t# double" %}
@@ -4472,6 +4735,7 @@
   ins_pipe(pipe_class_memory);
 %}

+
 // Load Int Constant
 instruct loadConI(iRegINoSp dst, immI src)
 %{
@@ -4655,6 +4919,7 @@
 instruct storeB(iRegI src, memory mem)
 %{
   match(Set mem (StoreB mem src));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "strb  $src, $mem\t# byte" %}
@@ -4668,6 +4933,7 @@
 instruct storeC(iRegI src, memory mem)
 %{
   match(Set mem (StoreC mem src));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "strh  $src, $mem\t# short" %}
@@ -4682,6 +4948,7 @@
 instruct storeI(iRegIorL2I src, memory mem)
 %{
   match(Set mem(StoreI mem src));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "strw  $src, $mem\t# int" %}
@@ -4695,6 +4962,7 @@
 instruct storeL(iRegL src, memory mem)
 %{
   match(Set mem (StoreL mem src));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "str  $src, $mem\t# int" %}
@@ -4708,6 +4976,7 @@
 instruct storeP(iRegP src, memory mem)
 %{
   match(Set mem (StoreP mem src));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "str  $src, $mem\t# ptr" %}
@@ -4721,6 +4990,7 @@
 instruct storeN(iRegN src, memory mem)
 %{
   match(Set mem (StoreN mem src));
+  predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
   format %{ "strw  $src, $mem\t# compressed ptr" %}
@@ -4755,6 +5025,38 @@
   ins_pipe(pipe_class_memory);
 %}

+
+// Store Float
+instruct storeF(vRegF src, memory mem)
+%{
+  match(Set mem (StoreF mem src));
+  predicate(!((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "strs  $src, $mem\t# float" %}
+
+  ins_encode( aarch64_enc_strs(src, mem) );
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// TODO
+// implement storeImmF0 and storeFImmPacked
+
+// Store Double
+instruct storeD(vRegD src, memory mem)
+%{
+  match(Set mem (StoreD mem src));
+  predicate(!((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "strd  $src, $mem\t# double" %}
+
+  ins_encode( aarch64_enc_strd(src, mem) );
+
+  ins_pipe(pipe_class_memory);
+%}
+
 // Store Compressed Klass Pointer
 instruct storeNKlass(iRegN src, memory mem)
 %{
@@ -4781,16 +5083,348 @@
   ins_pipe(pipe_class_memory);
 %}

+// TODO
+// implement storeImmD0 and storeDImmPacked
+
+// prefetch instructions
+// Must be safe to execute with invalid address (cannot fault).
+
+instruct prefetchr( memory mem ) %{
+  match(PrefetchRead mem);
+
+  format %{ "prfm $mem, PLDL1KEEP\t# Prefetch into level 1 cache read keep" %}
+
+  ins_encode( aarch64_enc_prefetchr(mem) );
+
+  ins_pipe(pipe_class_memory);
+%}
+
+instruct prefetchw( memory mem ) %{
+  match(PrefetchAllocation mem);
+
+  format %{ "prfm $mem, PSTL1KEEP\t# Prefetch into level 1 cache write keep" %}
+
+  ins_encode( aarch64_enc_prefetchw(mem) );
+
+  ins_pipe(pipe_class_memory);
+%}
+
+instruct prefetchnta( memory mem ) %{
+  match(PrefetchWrite mem);
+
+  format %{ "prfm $mem, PSTL1STRM\t# Prefetch into level 1 cache write streaming" %}
+
+  ins_encode( aarch64_enc_prefetchnta(mem) );
+
+  ins_pipe(pipe_class_memory);
+%}
+
+//  ---------------- volatile loads and stores ----------------
+
+// Load Byte (8 bit signed)
+instruct loadB_volatile(iRegINoSp dst, memory mem)
+%{
+  match(Set dst (LoadB mem));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarsb  $dst, $mem\t# byte" %}
+
+  ins_encode(aarch64_enc_ldarsb(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Byte (8 bit signed) into long
+instruct loadB2L_volatile(iRegLNoSp dst, memory mem)
+%{
+  match(Set dst (ConvI2L (LoadB mem)));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarsb  $dst, $mem\t# byte" %}
+
+  ins_encode(aarch64_enc_ldarsb(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Byte (8 bit unsigned)
+instruct loadUB_volatile(iRegINoSp dst, memory mem)
+%{
+  match(Set dst (LoadUB mem));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarb  $dst, $mem\t# byte" %}
+
+  ins_encode(aarch64_enc_ldarb(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Byte (8 bit unsigned) into long
+instruct loadUB2L_volatile(iRegLNoSp dst, memory mem)
+%{
+  match(Set dst (ConvI2L (LoadUB mem)));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarb  $dst, $mem\t# byte" %}
+
+  ins_encode(aarch64_enc_ldarb(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Short (16 bit signed)
+instruct loadS_volatile(iRegINoSp dst, memory mem)
+%{
+  match(Set dst (LoadS mem));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarshw  $dst, $mem\t# short" %}
+
+  ins_encode(aarch64_enc_ldarshw(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+instruct loadUS_volatile(iRegINoSp dst, memory mem)
+%{
+  match(Set dst (LoadUS mem));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarhw  $dst, $mem\t# short" %}
+
+  ins_encode(aarch64_enc_ldarhw(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Short/Char (16 bit unsigned) into long
+instruct loadUS2L_volatile(iRegLNoSp dst, memory mem)
+%{
+  match(Set dst (ConvI2L (LoadUS mem)));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarh  $dst, $mem\t# short" %}
+
+  ins_encode(aarch64_enc_ldarh(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Short/Char (16 bit signed) into long
+instruct loadS2L_volatile(iRegLNoSp dst, memory mem)
+%{
+  match(Set dst (ConvI2L (LoadS mem)));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarh  $dst, $mem\t# short" %}
+
+  ins_encode(aarch64_enc_ldarsh(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Integer (32 bit signed)
+instruct loadI_volatile(iRegINoSp dst, memory mem)
+%{
+  match(Set dst (LoadI mem));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarw  $dst, $mem\t# int" %}
+
+  ins_encode(aarch64_enc_ldarw(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Integer (32 bit unsigned) into long
+instruct loadUI2L_volatile(iRegLNoSp dst, memory mem, immL_32bits mask)
+%{
+  match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarw  $dst, $mem\t# int" %}
+
+  ins_encode(aarch64_enc_ldarw(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Long (64 bit signed)
+instruct loadL_volatile(iRegLNoSp dst, memory mem)
+%{
+  match(Set dst (LoadL mem));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldar  $dst, $mem\t# int" %}
+
+  ins_encode(aarch64_enc_ldar(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Pointer
+instruct load_volatileP(iRegPNoSp dst, memory mem)
+%{
+  match(Set dst (LoadP mem));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldar  $dst, $mem\t# ptr" %}
+
+  ins_encode(aarch64_enc_ldar(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Compressed Pointer
+instruct loadN_volatile(iRegNNoSp dst, memory mem)
+%{
+  match(Set dst (LoadN mem));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldarw  $dst, $mem\t# compressed ptr" %}
+
+  ins_encode(aarch64_enc_ldarw(dst, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Float
+instruct loadF_volatile(vRegF dst, memory mem)
+%{
+  match(Set dst (LoadF mem));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldars  $dst, $mem\t# float" %}
+
+  ins_encode( aarch64_enc_fldars(dst, mem) );
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Load Double
+instruct loadD_volatile(vRegD dst, memory mem)
+%{
+  match(Set dst (LoadD mem));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "ldard  $dst, $mem\t# double" %}
+
+  ins_encode( aarch64_enc_fldard(dst, mem) );
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Store Byte
+instruct storeB_volatile(iRegI src, memory mem)
+%{
+  match(Set mem (StoreB mem src));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "stlrb  $src, $mem\t# byte" %}
+
+  ins_encode(aarch64_enc_stlrb(src, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Store Char/Short
+instruct storeC_volatile(iRegI src, memory mem)
+%{
+  match(Set mem (StoreC mem src));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "stlrh  $src, $mem\t# short" %}
+
+  ins_encode(aarch64_enc_stlrh(src, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Store Integer
+
+instruct storeI_volatile(iRegIorL2I src, memory mem)
+%{
+  match(Set mem(StoreI mem src));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "stlrw  $src, $mem\t# int" %}
+
+  ins_encode(aarch64_enc_stlrw(src, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Store Long (64 bit signed)
+instruct storeL_volatile(iRegL src, memory mem)
+%{
+  match(Set mem (StoreL mem src));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "stlr  $src, $mem\t# int" %}
+
+  ins_encode(aarch64_enc_stlr(src, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Store Pointer
+instruct storeP_volatile(iRegP src, memory mem)
+%{
+  match(Set mem (StoreP mem src));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "stlr  $src, $mem\t# ptr" %}
+
+  ins_encode(aarch64_enc_stlr(src, mem));
+
+  ins_pipe(pipe_class_memory);
+%}
+
+// Store Compressed Pointer
+instruct storeN_volatile(iRegN src, memory mem)
+%{
+  match(Set mem (StoreN mem src));
+  predicate(((MemNode*)n)->is_volatile());
+
+  ins_cost(MEMORY_REF_COST);
+  format %{ "stlrw  $src, $mem\t# compressed ptr" %}
+
+  ins_encode(aarch64_enc_stlrw(src, mem));
+
+  ins_pipe(pipe_class_memory);
+%}

 // Store Float
-instruct storeF(vRegF src, memory mem)
+instruct storeF_volatile(vRegF src, memory mem)
 %{
   match(Set mem (StoreF mem src));
+  predicate(((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
-  format %{ "strs  $src, $mem\t# float" %}
-
-  ins_encode( aarch64_enc_strs(src, mem) );
+  format %{ "stlrs  $src, $mem\t# float" %}
+
+  ins_encode( aarch64_enc_fstlrs(src, mem) );

   ins_pipe(pipe_class_memory);
 %}
@@ -4799,53 +5433,20 @@
 // implement storeImmF0 and storeFImmPacked

 // Store Double
-instruct storeD(vRegD src, memory mem)
+instruct storeD_volatile(vRegD src, memory mem)
 %{
   match(Set mem (StoreD mem src));
+  predicate(((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
-  format %{ "strd  $src, $mem\t# double" %}
-
-  ins_encode( aarch64_enc_strd(src, mem) );
+  format %{ "stlrd  $src, $mem\t# double" %}
+
+  ins_encode( aarch64_enc_fstlrd(src, mem) );

   ins_pipe(pipe_class_memory);
 %}

-// TODO
-// implement storeImmD0 and storeDImmPacked
-
-// prefetch instructions
-// Must be safe to execute with invalid address (cannot fault).
-
-instruct prefetchr( memory mem ) %{
-  match(PrefetchRead mem);
-
-  format %{ "prfm $mem, PLDL1KEEP\t# Prefetch into level 1 cache read keep" %}
-
-  ins_encode( aarch64_enc_prefetchr(mem) );
-
-  ins_pipe(pipe_class_memory);
-%}
-
-instruct prefetchw( memory mem ) %{
-  match(PrefetchAllocation mem);
-
-  format %{ "prfm $mem, PSTL1KEEP\t# Prefetch into level 1 cache write keep" %}
-
-  ins_encode( aarch64_enc_prefetchw(mem) );
-
-  ins_pipe(pipe_class_memory);
-%}
-
-instruct prefetchnta( memory mem ) %{
-  match(PrefetchWrite mem);
-
-  format %{ "prfm $mem, PSTL1STRM\t# Prefetch into level 1 cache write streaming" %}
-
-  ins_encode( aarch64_enc_prefetchnta(mem) );
-
-  ins_pipe(pipe_class_memory);
-%}
+//  ---------------- end of volatile loads and stores ----------------

 // ============================================================================
 // BSWAP Instructions
@@ -4920,7 +5521,7 @@
   format %{ "MEMBAR-acquire\t# ???" %}

   ins_encode %{
-    __ dsb(Assembler::LD);
+    __ block_comment("membar_acquire (elided)");
   %}

   ins_pipe(pipe_class_memory);
@@ -4931,9 +5532,9 @@
   match(MemBarRelease);
   ins_cost(4*MEMORY_REF_COST);

-  format %{ "MEMBAR-release\t# ???" %}
-  ins_encode %{
-    __ dsb(Assembler::SY);
+  format %{ "MEMBAR-release" %}
+  ins_encode %{
+    __ block_comment("membar-release (elided)");
   %}
   ins_pipe(pipe_class_memory);
 %}
@@ -4942,10 +5543,10 @@
   match(MemBarVolatile);
   ins_cost(4*MEMORY_REF_COST);

-  format %{ "MEMBAR-volatile\t# ???" %}
-
-  ins_encode %{
-    __ dsb(Assembler::SY);
+  format %{ "MEMBAR-volatile?" %}
+
+  ins_encode %{
+    __ membar(Assembler::AnyAny);
   %}

   ins_pipe(pipe_class_memory);
@@ -4966,25 +5567,21 @@
   match(MemBarStoreStore);
   ins_cost(4*MEMORY_REF_COST);

-  format %{ "MEMBAR-storestore\t# ???" %}
-
-  ins_encode %{
-    __ dsb(Assembler::ST);
+  ins_encode %{
+    __ membar(Assembler::StoreStore);
   %}

   ins_pipe(pipe_class_memory);
 %}

-// TODO
-// check we are using the correct instruction and barrier type
-
 instruct membar_acquire_lock() %{
   match(MemBarAcquireLock);

   format %{ "MEMBAR-acquire-lock\t# ???" %}

   ins_encode %{
-    __ dsb(Assembler::SY);
+    __ block_comment("membar-acquire-lock");
+    __ membar(Assembler::Membar_mask_bits(Assembler::LoadLoad|Assembler::LoadStore));
   %}

   ins_pipe(pipe_class_memory);
@@ -4996,7 +5593,8 @@
   format %{ "MEMBAR-release-lock\t# ???" %}

   ins_encode %{
-    __ dsb(Assembler::SY);
+    __ block_comment("MEMBAR-release-lock");
+    __ membar(Assembler::Membar_mask_bits(Assembler::StoreStore|Assembler::LoadStore));
   %}

   ins_pipe(pipe_class_memory);
diff -r 5db717e716d9 -r 557a6ed9e5d0 src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Wed Oct 09 10:04:55 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Wed Oct 09 13:32:47 2013 +0100
@@ -1759,6 +1759,8 @@
   // if the memory word differs we return it in oldv and signal a fail
   bind(nope);
   mov(oldv, tmp);
+  // if (fail)
+  //   b(*fail);
   b(fail);
 }

@@ -1785,6 +1787,8 @@
   // if the memory word differs we return it in oldv and signal a fail
   bind(nope);
   mov(oldv, tmp);
+  // if (fail)
+  //   b(*fail);
   b(fail);
 }

diff -r 5db717e716d9 -r 557a6ed9e5d0 src/share/vm/opto/memnode.cpp
--- a/src/share/vm/opto/memnode.cpp	Wed Oct 09 10:04:55 2013 +0100
+++ b/src/share/vm/opto/memnode.cpp	Wed Oct 09 13:32:47 2013 +0100
@@ -55,6 +55,17 @@
   return calculate_adr_type(adr->bottom_type(), cross_check);
 }

+bool MemNode::is_volatile() const {
+#ifndef ASSERT
+  // fake the missing field
+  const TypePtr* _adr_type = NULL;
+  if (in(Address) != NULL)
+    _adr_type = in(Address)->bottom_type()->isa_ptr();
+#endif
+  Compile* C = Compile::current();
+  return C->alias_type(_adr_type)->is_volatile();
+}
+
 #ifndef PRODUCT
 void MemNode::dump_spec(outputStream *st) const {
   if (in(Address) == NULL)  return; // node is dead
diff -r 5db717e716d9 -r 557a6ed9e5d0 src/share/vm/opto/memnode.hpp
--- a/src/share/vm/opto/memnode.hpp	Wed Oct 09 10:04:55 2013 +0100
+++ b/src/share/vm/opto/memnode.hpp	Wed Oct 09 13:32:47 2013 +0100
@@ -125,6 +125,9 @@
   // the given memory state?  (The state may or may not be in(Memory).)
   Node* can_see_stored_value(Node* st, PhaseTransform* phase) const;

+  // True if this memory is volatile
+  bool is_volatile() const;
+
 #ifndef PRODUCT
   static void dump_adr_type(const Node* mem, const TypePtr* adr_type, outputStream *st);
   virtual void dump_spec(outputStream *st) const;


From aph at redhat.com  Wed Oct  9 05:53:15 2013
From: aph at redhat.com (Andrew Haley)
Date: Wed, 09 Oct 2013 13:53:15 +0100
Subject: [aarch64-port-dev ] Allow cmpxchg to fall through when it fails
Message-ID: <525551BB.5090806@redhat.com>

This is a small optimization.

Rather than branching when a cmpxchg fails, we can now optionally fall
through.  This saves a branch in the failure case.

Andrew.



# HG changeset patch
# User aph
# Date 1381322616 -3600
# Node ID 10b833f09e6a617fbc95fb3ca648bf0bc2c9b39e
# Parent  557a6ed9e5d03270183926ca313ea72cce2896cf
Allow cmpxchg to fall through when it fails

diff -r 557a6ed9e5d0 -r 10b833f09e6a src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 09 13:32:47 2013 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 09 13:43:36 2013 +0100
@@ -3192,7 +3192,7 @@
                   /*where=*/oop,
                   /*result=*/tmp,
                   cont,
-                  cas_failed);
+                  /*fail*/NULL);
     assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");

     // If the compare-and-exchange succeeded, then we found an unlocked
@@ -3227,8 +3227,8 @@
                     /*exchange_value=*/rthread,
                     /*where=*/tmp,
                     /*result=*/rscratch1,
-                    next,
-                    next);
+                    /*succeed*/next,
+                    /*fail*/NULL);
       __ bind(next);

       // store a non-null value into the box.
@@ -3310,7 +3310,7 @@
                   /*where=*/oop,
                   /*result=*/tmp,
                   cont,
-                  cas_failed);
+                  /*cas_failed*/NULL);
     assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");

     __ bind(cas_failed);
diff -r 557a6ed9e5d0 -r 10b833f09e6a src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp	Wed Oct 09 13:32:47 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp	Wed Oct 09 13:43:36 2013 +0100
@@ -96,9 +96,8 @@
   // displaced header address in the object header - if it is not the same, get the
   // object header instead
   lea(rscratch2, Address(obj, hdr_offset));
-  cmpxchgptr(hdr, disp_hdr, rscratch2, rscratch1, done, fail);
+  cmpxchgptr(hdr, disp_hdr, rscratch2, rscratch1, done, /*fallthough*/NULL);
   // if the object header was the same, we're done
-  bind(fail);
   // if the object header was not the same, it is now in the hdr register
   // => test if it is a stack pointer into the same stack (recursive locking), i.e.:
   //
@@ -159,9 +158,9 @@
   // we do unlocking via runtime call
   if (hdr_offset) {
     lea(rscratch1, Address(obj, hdr_offset));
-    cmpxchgptr(disp_hdr, hdr, rscratch1, rscratch2, done, slow_case);
+    cmpxchgptr(disp_hdr, hdr, rscratch1, rscratch2, done, &slow_case);
   } else {
-    cmpxchgptr(disp_hdr, hdr, obj, rscratch2, done, slow_case);
+    cmpxchgptr(disp_hdr, hdr, obj, rscratch2, done, &slow_case);
   }
   // done
   bind(done);
diff -r 557a6ed9e5d0 -r 10b833f09e6a src/cpu/aarch64/vm/interp_masm_aarch64.cpp
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Wed Oct 09 13:32:47 2013 +0100
+++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Wed Oct 09 13:43:36 2013 +0100
@@ -635,16 +635,16 @@
     Label fail;
     if (PrintBiasedLockingStatistics) {
       Label fast;
-      cmpxchgptr(swap_reg, lock_reg, obj_reg, rscratch1, fast, fail);
+      cmpxchgptr(swap_reg, lock_reg, obj_reg, rscratch1, fast, &fail);
       bind(fast);
       // cond_inc32(Assembler::zero,
       //            ExternalAddress((address) BiasedLocking::fast_path_entry_count_addr()));
       call_Unimplemented();
       b(done);
+      bind(fail);
     } else {
-      cmpxchgptr(swap_reg, lock_reg, obj_reg, rscratch1, done, fail);
+      cmpxchgptr(swap_reg, lock_reg, obj_reg, rscratch1, done, /*fallthrough*/NULL);
     }
-    bind(fail);

     // Test if the oopMark is an obvious stack pointer, i.e.,
     //  1) (mark & 7) == 0, and
@@ -734,9 +734,7 @@
     cbz(header_reg, done);

     // Atomic swap back the old header
-    Label fail;
-    cmpxchgptr(swap_reg, header_reg, obj_reg, rscratch1, done, fail);
-    bind(fail);
+    cmpxchgptr(swap_reg, header_reg, obj_reg, rscratch1, done, /*fallthrough*/NULL);

     // Call the runtime routine for slow case.
     str(obj_reg, Address(lock_reg, BasicObjectLock::obj_offset_in_bytes())); // restore obj
diff -r 557a6ed9e5d0 -r 10b833f09e6a src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Wed Oct 09 13:32:47 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Wed Oct 09 13:43:36 2013 +0100
@@ -1737,7 +1737,7 @@
 // register+offset Address.

 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
-				Label &succeed, Label &fail) {
+				Label &succeed, Label *fail) {
   // oldv holds comparison value
   // newv holds value to write in exchange
   // addr identifies memory word to compare against/update
@@ -1759,13 +1759,12 @@
   // if the memory word differs we return it in oldv and signal a fail
   bind(nope);
   mov(oldv, tmp);
-  // if (fail)
-  //   b(*fail);
-  b(fail);
+  if (fail)
+    b(*fail);
 }

 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
-				Label &succeed, Label &fail) {
+				Label &succeed, Label *fail) {
   // oldv holds comparison value
   // newv holds value to write in exchange
   // addr identifies memory word to compare against/update
@@ -1787,9 +1786,8 @@
   // if the memory word differs we return it in oldv and signal a fail
   bind(nope);
   mov(oldv, tmp);
-  // if (fail)
-  //   b(*fail);
-  b(fail);
+  if (fail)
+    b(*fail);
 }

 void MacroAssembler::incr_allocated_bytes(Register thread,
diff -r 557a6ed9e5d0 -r 10b833f09e6a src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Wed Oct 09 13:32:47 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Wed Oct 09 13:43:36 2013 +0100
@@ -1061,10 +1061,10 @@
   void cmpptr(Address src1, int32_t src2) { Unimplemented(); }

   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
-		  Label &suceed, Label &fail);
+		  Label &suceed, Label *fail);

   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
-		  Label &suceed, Label &fail);
+		  Label &suceed, Label *fail);

   void imulptr(Register dst, Register src) { Unimplemented(); }

diff -r 557a6ed9e5d0 -r 10b833f09e6a src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp
--- a/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp	Wed Oct 09 13:32:47 2013 +0100
+++ b/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp	Wed Oct 09 13:43:36 2013 +0100
@@ -1827,8 +1827,7 @@

     // src -> dest iff dest == r0 else r0 <- dest
     { Label here;
-      __ cmpxchgptr(r0, lock_reg, obj_reg, rscratch1, lock_done, here);
-      __ bind(here);
+      __ cmpxchgptr(r0, lock_reg, obj_reg, rscratch1, lock_done, /*fallthrough*/NULL);
     }

     // Hmm should this move to the slow path code area???
@@ -2033,7 +2032,7 @@

     // Atomic swap old header if oop still contains the stack lock
     Label succeed;
-    __ cmpxchgptr(r0, old_hdr, obj_reg, rscratch1, succeed, slow_path_unlock);
+    __ cmpxchgptr(r0, old_hdr, obj_reg, rscratch1, succeed, &slow_path_unlock);
     __ bind(succeed);

     // slow path re-enters here
diff -r 557a6ed9e5d0 -r 10b833f09e6a src/cpu/aarch64/vm/templateTable_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp	Wed Oct 09 13:32:47 2013 +0100
+++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp	Wed Oct 09 13:43:36 2013 +0100
@@ -3240,7 +3240,7 @@

     Label succeed;
     // if someone beat us on the allocation, try again, otherwise continue
-    __ cmpxchgptr(r0, r1, RtopAddr, rscratch1, succeed, retry);
+    __ cmpxchgptr(r0, r1, RtopAddr, rscratch1, succeed, &retry);
     __ bind(succeed);
     __ incr_allocated_bytes(rthread, r3, 0, rscratch1);
   }


From aph at redhat.com  Wed Oct  9 06:00:08 2013
From: aph at redhat.com (Andrew Haley)
Date: Wed, 09 Oct 2013 14:00:08 +0100
Subject: [aarch64-port-dev ] Fix order of fcseld operands
Message-ID: <52555358.3000604@redhat.com>

In HotSpot, a CMoveNode is (Condition, IfFalse, IfTrue).
In Aarch64, the corresponding insn is csel(dest, IfTrue, IfFalse, Condition).

This is very confusing.  Fixed thusly.

Andrew.



# HG changeset patch
# User aph
# Date 1381323341 -3600
# Node ID 408a7b0091c5eb62f1a9e48e031a78c6f29e6c15
# Parent  10b833f09e6a617fbc95fb3ca648bf0bc2c9b39e
Fix order of fcseld operands

diff -r 10b833f09e6a -r 408a7b0091c5 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 09 13:43:36 2013 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 09 13:55:41 2013 +0100
@@ -6438,8 +6438,8 @@
   ins_encode %{
     Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
     __ fcsels(as_FloatRegister($dst$$reg),
+              as_FloatRegister($src2$$reg),
               as_FloatRegister($src1$$reg),
-              as_FloatRegister($src2$$reg),
               cond);
   %}

@@ -6456,8 +6456,8 @@
   ins_encode %{
     Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
     __ fcsels(as_FloatRegister($dst$$reg),
+              as_FloatRegister($src2$$reg),
               as_FloatRegister($src1$$reg),
-              as_FloatRegister($src2$$reg),
               cond);
   %}

@@ -6474,8 +6474,8 @@
   ins_encode %{
     Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
     __ fcseld(as_FloatRegister($dst$$reg),
+              as_FloatRegister($src2$$reg),
               as_FloatRegister($src1$$reg),
-              as_FloatRegister($src2$$reg),
               cond);
   %}

@@ -6492,8 +6492,8 @@
   ins_encode %{
     Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
     __ fcseld(as_FloatRegister($dst$$reg),
+              as_FloatRegister($src2$$reg),
               as_FloatRegister($src1$$reg),
-              as_FloatRegister($src2$$reg),
               cond);
   %}



From aph at redhat.com  Wed Oct  9 06:01:47 2013
From: aph at redhat.com (aph at redhat.com)
Date: Wed, 09 Oct 2013 13:01:47 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: 5 new changesets
Message-ID: <20131009130206.9C09562E87@hg.openjdk.java.net>

Changeset: 1b73f7fb6f30
Author:    aph
Date:      2013-10-03 14:33 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/1b73f7fb6f30

Simplify memory barrier generation

! src/cpu/aarch64/vm/assembler_aarch64.hpp
! src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
! src/cpu/aarch64/vm/macroAssembler_aarch64.hpp

Changeset: 5db717e716d9
Author:    aph
Date:      2013-10-09 10:04 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/5db717e716d9

Correct half word types in loads and stores

! src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp

Changeset: 557a6ed9e5d0
Author:    aph
Date:      2013-10-09 13:32 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/557a6ed9e5d0

C2: Handle volatile fields by generating ldar and stlr instructions.
Define instruct patterns for all volatile variants.
Define enc patterns for all variants.
Predicate non-volatile field accesses with !((MemNode*)n)->is_volatile().
Define MemNode::is_volatile() for use in predicates.

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
! src/share/vm/opto/memnode.cpp
! src/share/vm/opto/memnode.hpp

Changeset: 10b833f09e6a
Author:    aph
Date:      2013-10-09 13:43 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/10b833f09e6a

Allow cmpxchg to fall through when it fails

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp
! src/cpu/aarch64/vm/interp_masm_aarch64.cpp
! src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
! src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
! src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp
! src/cpu/aarch64/vm/templateTable_aarch64.cpp

Changeset: 408a7b0091c5
Author:    aph
Date:      2013-10-09 13:55 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/408a7b0091c5

Fix order of fcseld operands

! src/cpu/aarch64/vm/aarch64.ad



From adinn at redhat.com  Thu Oct 10 02:28:29 2013
From: adinn at redhat.com (adinn at redhat.com)
Date: Thu, 10 Oct 2013 09:28:29 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: 7 new changesets
Message-ID: <20131010092850.B832F62ED6@hg.openjdk.java.net>

Changeset: 96d3fd4fc2aa
Author:    adinn
Date:      2013-10-09 13:58 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/96d3fd4fc2aa

rounding of extra stack slots should use slots not bytes as unit

! src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp

Changeset: 901815cb44af
Author:    adinn
Date:      2013-10-09 15:17 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/901815cb44af

added rules matching (StoreXXX mem zero) which use zr directly as the source

previously ws moving zr to a src rgeister and then doing the strx

! src/cpu/aarch64/vm/aarch64.ad

Changeset: 67b98fe19e61
Author:    adinn
Date:      2013-10-09 15:23 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/67b98fe19e61

corrected testN and testP instructions to use cmpw amd cmp. respectively

! src/cpu/aarch64/vm/aarch64.ad

Changeset: 36e0c7438966
Author:    adinn
Date:      2013-10-09 15:43 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/36e0c7438966

opto stubs write thread anchor pc rather than expect ret pc to be on stack

the x86 opto stubs leave their VM callouts ot find their return
address on the stack above the therad anchor sp. this doesn't work on
AArch64 as the C compiler can put the ret pc where it likes. so we
ahve to write the anchor pc fiels form the opto stub. it's baroque but
it works.

! src/cpu/aarch64/vm/aarch64.ad
! src/share/vm/opto/generateOptoStub.cpp

Changeset: 5b062e7d9905
Author:    adinn
Date:      2013-10-09 15:46 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/5b062e7d9905

CMoveN instructions now use cselw, CMoveN/P now name correct type in format

! src/cpu/aarch64/vm/aarch64.ad

Changeset: 04f804c73d4a
Author:    adinn
Date:      2013-10-09 16:59 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/04f804c73d4a

Merge

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp

Changeset: 55c04eeb33b9
Author:    adinn
Date:      2013-10-10 10:27 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/55c04eeb33b9

Locate correct node for volatile test when memnode is nested inside a match

! src/cpu/aarch64/vm/aarch64.ad



From adinn at redhat.com  Thu Oct 10 05:23:52 2013
From: adinn at redhat.com (adinn at redhat.com)
Date: Thu, 10 Oct 2013 12:23:52 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: added missing
	predicates for	non-volatile store rules
Message-ID: <20131010122359.1873E62EEE@hg.openjdk.java.net>

Changeset: f043f9395d36
Author:    adinn
Date:      2013-10-10 13:23 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/f043f9395d36

added missing predicates for non-volatile store rules

rules storeimmX0 for X in {B, C, I, L, P and N) were added in parallel
with the volatile load/store rewrite and so omitted this predicate

rule storeN seems to have had te predicate omitted by oversight

load_volatileP has been renamed to loadP_volatile for consistency

! src/cpu/aarch64/vm/aarch64.ad



From edward.nevill at linaro.org  Thu Oct 10 07:38:08 2013
From: edward.nevill at linaro.org (Edward Nevill)
Date: Thu, 10 Oct 2013 15:38:08 +0100
Subject: [aarch64-port-dev ] C2 error on ARM sim only regardingcall to
 runtime from non-compiled code
In-Reply-To: <524EEF97.3070701@redhat.com>
References: <524EEF97.3070701@redhat.com>
Message-ID: <1381415888.2177.5.camel@localhost.localdomain>

On Fri, 2013-10-04 at 17:40 +0100, Andrew Dinn wrote:
> When running on the ARM sim Ed found that routine check_compiled_frame
> throws an error claiming that a call out to the runtime is occuring from
> a non-compiler generated address. This happens when a stub enters the
> runtime from one fo the optoRuntime stubs (see opto/runtime.cpp). These
> stubs save only the stack pointer in the thread's frame anchor i.e
> _anchor.last_Java_sp==0xfff..... but _anchor.last_Java_fp==0x0 and
> _anchor.last_Java_pc=0x0.

Hi Andrew,

Thanks very much for looking into this and for the fix.

I have tested the server compiler on the RTSM model and it is now 1000% better.

So far I have tested

Dhrystone
CaffeineMark
Grinderbench

and most importantly

Galaxians

All seem to be fully functional.

All the best,
Ed.




From edward.nevill at linaro.org  Fri Oct 11 05:59:29 2013
From: edward.nevill at linaro.org (Edward Nevill)
Date: Fri, 11 Oct 2013 13:59:29 +0100
Subject: [aarch64-port-dev ] Merge up to jdk8-b110
Message-ID: <1381496369.18100.34.camel@localhost.localdomain>

Hi,

The attached changesets merge the aarch64 port up to jdk8-b110 from jdk8-b90. Tag jdk8-b110 is dated Oct 2nd, 2013.

I have built C1 and C2 and tested as follows:-

Cross compilation builds, tested on the RTSM model:-

client/fastdebug/hotspot                333/16/18
server/release/hotspot (*)              323/32/12

(*) This test used client/release as the test harness

Builtin simulator builds:-

client/slowdebug/hotspot-sanity         3/0/0
client/release/hotspot                  323/27/17

There is a known problem with UseCompressedKlassPointers (or UseCompressedClassPointers as they are now known). These were broken somewhere between b104 and b105. I need to go back and see why they are broken, however, I would like to get this mega merge off my desk before I go back and look at this.

I also see sporadic crashes in GC every few hours. However, I also see these with the existing aarch64 tip and they do not seem any more frequent post merge. Again I would like to push this merge before going back to look at these.

Because of the size of the merge changesets (34Mb) I have not posted them inline. Instead I have put them on the web at

http://people.linaro.org/~edward.nevill/b110/corba_diffs
http://people.linaro.org/~edward.nevill/b110/hotspot_diffs
http://people.linaro.org/~edward.nevill/b110/jaxp_diffs
http://people.linaro.org/~edward.nevill/b110/jdk_diffs
http://people.linaro.org/~edward.nevill/b110/jdk8_diffs
http://people.linaro.org/~edward.nevill/b110/langtools_diffs
http://people.linaro.org/~edward.nevill/b110/nashorn_diffs
http://people.linaro.org/~edward.nevill/b110/jaxws_diffs

A gzip file containing all theses diffs may be downloaded from 

http://people.linaro.org/~edward.nevill/b110.tgz

The changesets below are the changes to the aarch64 specific code to bring it in line with the merge up to b110.

OK to push?
Ed.

-- cut here ---
# HG changeset patch
# User Edward Nevill edward.nevill at linaro.org
# Date 1381491246 -3600
#      Fri Oct 11 12:34:06 2013 +0100
# Node ID fb54b96dadd94c5a316ae6d23ff7157642ecfeeb
# Parent  eea63b68cd042c4c7cd0f23b74a105f350cda010
aarch64 specific changes for merge to jdk8-b110

diff -r eea63b68cd04 -r fb54b96dadd9 common/autoconf/build-aux/autoconf-config.guess
--- a/common/autoconf/build-aux/autoconf-config.guess	Fri Oct 11 12:03:26 2013 +0100
+++ b/common/autoconf/build-aux/autoconf-config.guess	Fri Oct 11 12:34:06 2013 +0100
@@ -1021,9 +1021,6 @@
     x86_64:Linux:*:*)
 	echo ${UNAME_MACHINE}-unknown-linux-gnu
 	exit ;;
-    aarch64:Linux:*:*)
-	echo aarch64-unknown-linux-gnu
-	exit ;;
     xtensa*:Linux:*:*)
 	echo ${UNAME_MACHINE}-unknown-linux-gnu
 	exit ;;
diff -r eea63b68cd04 -r fb54b96dadd9 common/autoconf/generated-configure.sh
--- a/common/autoconf/generated-configure.sh	Fri Oct 11 12:03:26 2013 +0100
+++ b/common/autoconf/generated-configure.sh	Fri Oct 11 12:34:06 2013 +0100
@@ -1,6 +1,6 @@
 #! /bin/sh
 # Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.67 for OpenJDK jdk8.
+# Generated by GNU Autoconf 2.69 for OpenJDK jdk8.
 #
 # Report bugs to <build-dev at openjdk.java.net>.
 #
@@ -242,11 +242,18 @@
              # We cannot yet assume a decent shell, so we have to provide a
 # neutralization value for shells without unset; and this also
 # works around shells that cannot unset nonexistent variables.
+# Preserve -v and -x to the replacement shell.
 BASH_ENV=/dev/null
 ENV=/dev/null
 (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV
 case $- in # ((((
-	exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"}
+  *v*x* | *x*v* ) as_opts=-vx ;;
+  *v* ) as_opts=-v ;;
+  *x* ) as_opts=-x ;;
+  * ) as_opts= ;;
+esac
+exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"}
+# Admittedly, this is quite paranoid, since all the known shells bail
 # out after a failed `exec'.
 $as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2
 exit 255
@@ -654,7 +661,6 @@
 X_LIBS
 X_PRE_LIBS
 X_CFLAGS
-XMKMF
 CXXFLAGS_DEBUG_SYMBOLS
 CFLAGS_DEBUG_SYMBOLS
 ZIP_DEBUGINFO_FILES
@@ -1023,7 +1029,6 @@
 with_override_hotspot
 with_override_nashorn
 with_override_jdk
-with_override_nashorn
 with_import_hotspot
 with_msvcr_dll
 with_dxsdk
@@ -1071,7 +1076,6 @@
 OBJCFLAGS
 CPP
 CXXCPP
-XMKMF
 FREETYPE2_CFLAGS
 FREETYPE2_LIBS
 ALSA_CFLAGS
@@ -1778,7 +1782,6 @@
   --with-override-hotspot use this hotspot dir for the build
   --with-override-nashorn use this nashorn dir for the build
   --with-override-jdk     use this jdk dir for the build
-  --with-override-nashorn use this nashorn dir for the build
   --with-import-hotspot   import hotspot binaries from this jdk image or
                           hotspot build dist dir instead of building from
                           source
@@ -1840,7 +1843,6 @@
   OBJCFLAGS   Objective C compiler flags
   CPP         C preprocessor
   CXXCPP      C++ preprocessor
-  XMKMF       Path to xmkmf, Makefile generator for X Window System
   FREETYPE2_CFLAGS
               C compiler flags for FREETYPE2, overriding pkg-config
   FREETYPE2_LIBS
@@ -1919,7 +1921,7 @@
 if $ac_init_version; then
   cat <<\_ACEOF
 OpenJDK configure jdk8
-generated by GNU Autoconf 2.67
+generated by GNU Autoconf 2.69
 
 Copyright (C) 2012 Free Software Foundation, Inc.
 This configure script is free software; the Free Software Foundation
@@ -2615,7 +2617,7 @@
 running configure, to aid debugging if configure makes a mistake.
 
 It was created by OpenJDK $as_me jdk8, which was
-generated by GNU Autoconf 2.67.  Invocation command line was
+generated by GNU Autoconf 2.69.  Invocation command line was
 
   $ $0 $@
 
@@ -2847,7 +2849,6 @@
 # Let the site file select an alternate cache file if it wants to.
 # Prefer an explicitly selected file to automatically selected ones.
 ac_site_file1=NONE
-ac_site_file2=NONE
 if test -n "$CONFIG_SITE"; then
   # We do not want a PATH search for config.site.
   case $CONFIG_SITE in #((
@@ -2855,14 +2856,8 @@
     */*) ac_site_file1=$CONFIG_SITE;;
     *)   ac_site_file1=./$CONFIG_SITE;;
   esac
-elif test "x$prefix" != xNONE; then
-  ac_site_file1=$prefix/share/config.site
-  ac_site_file2=$prefix/etc/config.site
-else
-  ac_site_file1=$ac_default_prefix/share/config.site
-  ac_site_file2=$ac_default_prefix/etc/config.site
-fi
-for ac_site_file in "$ac_site_file1" "$ac_site_file2"
+fi
+for ac_site_file in $ac_site_file1
 do
   test "x$ac_site_file" = xNONE && continue
   if test /dev/null != "$ac_site_file" && test -r "$ac_site_file"; then
@@ -3813,7 +3808,7 @@
 #CUSTOM_AUTOCONF_INCLUDE
 
 # Do not change or remove the following line, it is needed for consistency checks:
-DATE_WHEN_GENERATED=1379504921
+DATE_WHEN_GENERATED=1381411006
 
 ###############################################################################
 #
@@ -5202,7 +5197,6 @@
 
 
 
-if test "${ac_cv_path_THEPWDCMD+set}" = set; then :
     for ac_prog in rm
 do
   # Extract the first word of "$ac_prog", so it can be a program name with args.
@@ -6677,8 +6671,9 @@
 # The aliases save the names the user supplied, while $host etc.
 # will get canonicalized.
 test -n "$target_alias" &&
-  test "$program_prefix$program_suffix$program_transform_name" = \
-    NONENONEs,x,x, &&
+  test "$target_alias" != "$host_alias" &&
+    test "$program_prefix$program_suffix$program_transform_name" = \
+      NONENONEs,x,x, &&
   program_prefix=${target_alias}-
 
 # Figure out the build and target systems. # Note that in autoconf terminology, "build" is obvious, but "target"
@@ -16225,6 +16220,8 @@
   withval=$with_override_jdk;
 fi
 
+
+
 # Check whether --with-override-nashorn was given.
 if test "${with_override_nashorn+set}" = set; then :
   withval=$with_override_nashorn;
@@ -29384,6 +29381,9 @@
     s390)
       ZERO_ARCHFLAG="-m31"
       ;;
+    aarch64)
+      ZERO_ARCHFLAG=""
+      ;;
     *)
       ZERO_ARCHFLAG="-m${OPENJDK_TARGET_CPU_BITS}"
   esac
@@ -29759,85 +29759,9 @@
 else
   # One or both of the vars are not set, and there is no cached value.
 ac_x_includes=no ac_x_libraries=no
-rm -f -r conftest.dir
-if mkdir conftest.dir; then
-  cd conftest.dir
-  cat >Imakefile <<'_ACEOF'
-incroot:
-	@echo incroot='${INCROOT}'
-usrlibdir:
-	@echo usrlibdir='${USRLIBDIR}'
-libdir:
-	@echo libdir='${LIBDIR}'
-_ACEOF
-  if (export CC; ${XMKMF-xmkmf}) >/dev/null 2>/dev/null && test -f Makefile; then
-    # GNU make sometimes prints "make[1]: Entering ...", which would confuse us.
-    for ac_var in incroot usrlibdir libdir; do
-      eval "ac_im_$ac_var=\`\${MAKE-make} $ac_var 2>/dev/null | sed -n 's/^$ac_var=//p'\`"
-    done
-    # Open Windows xmkmf reportedly sets LIBDIR instead of USRLIBDIR.
-    for ac_extension in a so sl dylib la dll; do
-      if test ! -f "$ac_im_usrlibdir/libX11.$ac_extension" &&
-	 test -f "$ac_im_libdir/libX11.$ac_extension"; then
-	ac_im_usrlibdir=$ac_im_libdir; break
-      fi
-    done
-    # Screen out bogus values from the imake configuration.  They are
-    # bogus both because they are the default anyway, and because
-    # using them would break gcc on systems where it needs fixed includes.
-    case $ac_im_incroot in
-	/usr/include) ac_x_includes= ;;
-	*) test -f "$ac_im_incroot/X11/Xos.h" && ac_x_includes=$ac_im_incroot;;
-    esac
-    case $ac_im_usrlibdir in
-	/usr/lib | /usr/lib64 | /lib | /lib64) ;;
-	*) test -d "$ac_im_usrlibdir" && ac_x_libraries=$ac_im_usrlibdir ;;
-    esac
-  fi
-  cd ..
-  rm -f -r conftest.dir
-fi
-
 # Standard set of common directories for X headers.
 # Check X11 before X11Rn because it is often a symlink to the current release.
-ac_x_header_dirs='
-/usr/X11/include
-/usr/X11R7/include
-/usr/X11R6/include
-/usr/X11R5/include
-/usr/X11R4/include
-
-/usr/include/X11
-/usr/include/X11R7
-/usr/include/X11R6
-/usr/include/X11R5
-/usr/include/X11R4
-
-/usr/local/X11/include
-/usr/local/X11R7/include
-/usr/local/X11R6/include
-/usr/local/X11R5/include
-/usr/local/X11R4/include
-
-/usr/local/include/X11
-/usr/local/include/X11R7
-/usr/local/include/X11R6
-/usr/local/include/X11R5
-/usr/local/include/X11R4
-
-/usr/X386/include
-/usr/x386/include
-/usr/XFree86/include/X11
-
-/usr/include
-/usr/local/include
-/usr/unsupported/include
-/usr/athena/include
-/usr/local/x11r5/include
-/usr/lpp/Xamples/include
-
-/usr/openwin/include
-/usr/openwin/share/include'
+ac_x_header_dirs=''
 
 if test "$ac_x_includes" = no; then
   # Guess where to find include files, by looking for Xlib.h.
@@ -33751,7 +33675,7 @@
 # values after options handling.
 ac_log="
 This file was extended by OpenJDK $as_me jdk8, which was
-generated by GNU Autoconf 2.67.  Invocation command line was
+generated by GNU Autoconf 2.69.  Invocation command line was
 
   CONFIG_FILES    = $CONFIG_FILES
   CONFIG_HEADERS  = $CONFIG_HEADERS
@@ -33814,7 +33738,7 @@
 ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
 ac_cs_version="\\
 OpenJDK config.status jdk8
-configured by $0, generated by GNU Autoconf 2.67,
+configured by $0, generated by GNU Autoconf 2.69,
   with options \\"\$ac_cs_config\\"
 
 Copyright (C) 2012 Free Software Foundation, Inc.
--- cut here ---

--- cut here ---
# HG changeset patch
# User Edward Nevill edward.nevill at linaro.org
# Date 1381491589 -3600
#      Fri Oct 11 12:39:49 2013 +0100
# Node ID 0b5e450b23211722398beb850e34f144809152e7
# Parent  a84cf0dd740c1953eca84ae630b5bf18343076ff
aarch64 specific changes for merge to jdk8-b110

diff -r a84cf0dd740c -r 0b5e450b2321 make/linux/makefiles/aarch64.make
--- a/make/linux/makefiles/aarch64.make	Fri Oct 11 12:06:22 2013 +0100
+++ b/make/linux/makefiles/aarch64.make	Fri Oct 11 12:39:49 2013 +0100
@@ -30,7 +30,7 @@
 CFLAGS += -DVM_LITTLE_ENDIAN
 
 ifeq ($(BUILTIN_SIM), true)
-CFLAGS  += -DBUILTIN_SIM
+CFLAGS  += -DBUILTIN_SIM -DALLOW_OPERATOR_NEW_USAGE
 endif
 
 # CFLAGS += -D_LP64=1
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad	Fri Oct 11 12:39:49 2013 +0100
@@ -1408,7 +1408,7 @@
 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 {
   st->print_cr("# MachUEPNode");
-  if (UseCompressedKlassPointers) {
+  if (UseCompressedClassPointers) {
     st->print_cr("\tldrw rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
     if (Universe::narrow_klass_shift() != 0) {
       st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/c1_CodeStubs_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_CodeStubs_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_CodeStubs_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -418,6 +418,10 @@
     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
     reloc_type = relocInfo::oop_type;
     break;
+  case load_appendix_id:
+    target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
+    reloc_type = relocInfo::oop_type;
+    break;
   default: ShouldNotReachHere();
   }
 
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -294,7 +294,7 @@
   Register receiver = FrameMap::receiver_opr->as_register();
   Register ic_klass = IC_Klass;
   const int ic_cmp_size = 4 * 4;
-  const bool do_post_padding = VerifyOops || UseCompressedKlassPointers;
+  const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
   if (!do_post_padding) {
     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
     while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
@@ -337,7 +337,8 @@
 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
   // Allocate a new index in table to hold the object once it's been patched
   int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
-  PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_mirror_id, oop_index);
+//  PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_mirror_id, oop_index);
+  PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
 
   RelocationHolder rspec = oop_Relocation::spec(oop_index);
   address const_ptr = int_constant(-1);
@@ -985,7 +986,7 @@
       // FIXME: OMG this is a horrible kludge.  Any offset from an
       // address that matches klass_offset_in_bytes() will be loaded
       // as a word, not a long.
-      if (UseCompressedKlassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
+      if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
 	__ ldrw(dest->as_register(), as_Address(from_addr));
       } else {
 	__ ldr(dest->as_register(), as_Address(from_addr));
@@ -1032,7 +1033,7 @@
     __ verify_oop(dest->as_register());
   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
 #ifdef _LP64
-    if (UseCompressedKlassPointers) {
+    if (UseCompressedClassPointers) {
       __ decode_klass_not_null(dest->as_register());
     }
 #endif
@@ -1350,7 +1351,7 @@
   } else if (obj == klass_RInfo) {
     klass_RInfo = dst;
   }
-  if (k->is_loaded() && !UseCompressedKlassPointers) {
+  if (k->is_loaded() && !UseCompressedClassPointers) {
     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
   } else {
     Rtmp1 = op->tmp3()->as_register();
@@ -1358,14 +1359,6 @@
   }
 
   assert_different_registers(obj, k_RInfo, klass_RInfo);
-  if (!k->is_loaded()) {
-    klass2reg_with_patching(k_RInfo, op->info_for_patch());
-  } else {
-#ifdef _LP64
-    __ mov_metadata(k_RInfo, k->constant_encoding());
-#endif // _LP64
-  }
-  assert(obj != k_RInfo, "must be different");
 
     if (op->should_profile()) {
       Label not_null;
@@ -1384,6 +1377,13 @@
       __ cbz(obj, *obj_is_null);
     }
 
+  if (!k->is_loaded()) {
+    klass2reg_with_patching(k_RInfo, op->info_for_patch());
+  } else {
+#ifdef _LP64
+    __ mov_metadata(k_RInfo, k->constant_encoding());
+#endif // _LP64
+  }
   __ verify_oop(obj);
 
   if (op->fast_check()) {
@@ -2295,7 +2295,7 @@
     // We don't know the array types are compatible
     if (basic_type != T_OBJECT) {
       // Simple test for basic type arrays
-      if (UseCompressedKlassPointers) {
+      if (UseCompressedClassPointers) {
         __ ldrw(tmp, src_klass_addr);
         __ ldrw(rscratch1, dst_klass_addr);
         __ cmpw(tmp, rscratch1);
@@ -2426,14 +2426,14 @@
     Label known_ok, halt;
     __ mov_metadata(tmp, default_type->constant_encoding());
 #ifdef _LP64
-    if (UseCompressedKlassPointers) {
+    if (UseCompressedClassPointers) {
       __ encode_klass_not_null(tmp);
     }
 #endif
 
     if (basic_type != T_OBJECT) {
 
-      if (UseCompressedKlassPointers) {
+      if (UseCompressedClassPointers) {
 	__ ldrw(rscratch1, dst_klass_addr);
 	__ cmpw(tmp, rscratch1);
       } else {
@@ -2441,7 +2441,7 @@
 	__ cmp(tmp, rscratch1);
       }
       __ br(Assembler::NE, halt);
-      if (UseCompressedKlassPointers) {
+      if (UseCompressedClassPointers) {
 	__ ldrw(rscratch1, src_klass_addr);
 	__ cmpw(tmp, rscratch1);
       } else {
@@ -2450,7 +2450,7 @@
       }
       __ br(Assembler::EQ, known_ok);
     } else {
-      if (UseCompressedKlassPointers) {
+      if (UseCompressedClassPointers) {
 	__ ldrw(rscratch1, dst_klass_addr);
 	__ cmpw(tmp, rscratch1);
       } else {
@@ -2614,6 +2614,9 @@
   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
 }
 
+void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
+  fatal("CRC32 intrinsic is not implemented on this platform");
+}
 
 void LIR_Assembler::align_backward_branch_target() {
 }
@@ -2828,7 +2831,7 @@
       }
       __ verify_oop(dest->as_register());
     } else if (type == T_ADDRESS && from_addr->disp() == oopDesc::klass_offset_in_bytes()) {
-      if (UseCompressedKlassPointers) {
+      if (UseCompressedClassPointers) {
 	__ decode_klass_not_null(dest->as_register());
       }
     }
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -957,6 +957,9 @@
   __ arraycopy(src.result(), src_pos.result(), dst.result(), dst_pos.result(), length.result(), tmp, expected_type, flags, info); // does add_safepoint
 }
 
+void LIRGenerator::do_update_CRC32(Intrinsic* x) {
+  fatal("CRC32 intrinsic is not implemented on this platform");
+}
 
 // _i2l, _i2f, _i2d, _l2i, _l2f, _l2d, _f2i, _f2l, _f2d, _d2i, _d2l, _d2f
 // _i2b, _i2c, _i2s
@@ -1157,7 +1160,7 @@
   }
   LIR_Opr reg = rlock_result(x);
   LIR_Opr tmp3 = LIR_OprFact::illegalOpr;
-  if (!x->klass()->is_loaded() || UseCompressedKlassPointers) {
+  if (!x->klass()->is_loaded() || UseCompressedClassPointers) {
     tmp3 = new_register(objectType);
   }
   __ checkcast(reg, obj.result(), x->klass(),
@@ -1178,7 +1181,7 @@
   }
   obj.load_item();
   LIR_Opr tmp3 = LIR_OprFact::illegalOpr;
-  if (!x->klass()->is_loaded() || UseCompressedKlassPointers) {
+  if (!x->klass()->is_loaded() || UseCompressedClassPointers) {
     tmp3 = new_register(objectType);
   }
   __ instanceof(reg, obj.result(), x->klass(),
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -188,7 +188,7 @@
   }
   str(t1, Address(obj, oopDesc::mark_offset_in_bytes()));
 
-  if (UseCompressedKlassPointers) { // Take care not to kill klass
+  if (UseCompressedClassPointers) { // Take care not to kill klass
     encode_klass_not_null(t1, klass);
     strw(t1, Address(obj, oopDesc::klass_offset_in_bytes()));
   } else {
@@ -197,7 +197,7 @@
 
   if (len->is_valid()) {
     strw(len, Address(obj, arrayOopDesc::length_offset_in_bytes()));
-  } else if (UseCompressedKlassPointers) {
+  } else if (UseCompressedClassPointers) {
     store_klass_gap(obj, zr);
   }
 }
@@ -432,7 +432,7 @@
   b(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
   bind(dont);
   const int ic_cmp_size = 4 * 4;
-  assert(UseCompressedKlassPointers || offset() - start_offset == ic_cmp_size, "check alignment in emit_method_entry");
+  assert(UseCompressedClassPointers || offset() - start_offset == ic_cmp_size, "check alignment in emit_method_entry");
 }
 
 
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -1113,6 +1113,13 @@
       }
       break;
 
+    case load_appendix_patching_id:
+      { StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments);
+        // we should set up register map
+        oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
+      }
+      break;
+
     case handle_exception_nofpu_id:
     case handle_exception_id:
       { StubFrame f(sasm, "handle_exception", dont_gc_arguments);
@@ -1179,10 +1186,10 @@
   Bytecodes::Code code       = field_access.code();
 
   // We must load class, initialize class and resolvethe field
-  FieldAccessInfo result; // initialize class if needed
+  fieldDescriptor result; // initialize class if needed
   constantPoolHandle constants(THREAD, caller->constants());
-  LinkResolver::resolve_field(result, constants, field_access.index(), Bytecodes::java_code(code), false, CHECK_NULL);
-  return result.klass()();
+  LinkResolver::resolve_field_access(result, constants, field_access.index(), Bytecodes::java_code(code), CHECK_NULL);
+  return result.field_holder();
 }
 
 
@@ -1252,7 +1259,7 @@
   KlassHandle init_klass(THREAD, NULL); // klass needed by load_klass_patching code
   KlassHandle load_klass(THREAD, NULL); // klass needed by load_klass_patching code
   Handle mirror(THREAD, NULL);                    // oop needed by load_mirror_patching code
-  FieldAccessInfo result; // initialize class if needed
+  fieldDescriptor result; // initialize class if needed
 
   bool load_klass_or_mirror_patch_id =
     (stub_id == Runtime1::load_klass_patching_id || stub_id == Runtime1::load_mirror_patching_id);
@@ -1260,11 +1267,11 @@
   if (stub_id == Runtime1::access_field_patching_id) {
 
     Bytecode_field field_access(caller_method, bci);
-    FieldAccessInfo result; // initialize class if needed
+    fieldDescriptor result; // initialize class if needed
     Bytecodes::Code code = field_access.code();
     constantPoolHandle constants(THREAD, caller_method->constants());
-    LinkResolver::resolve_field(result, constants, field_access.index(), Bytecodes::java_code(code), false, CHECK);
-    patch_field_offset = result.field_offset();
+    LinkResolver::resolve_field_access(result, constants, field_access.index(), Bytecodes::java_code(code), CHECK);
+    patch_field_offset = result.offset();
 
     // If we're patching a field which is volatile then at compile it
     // must not have been known to be volatile, so the generated code
@@ -1495,6 +1502,25 @@
   return caller_is_deopted();
 }
 
+int Runtime1::move_appendix_patching(JavaThread* thread) {
+//
+// NOTE: we are still in Java
+//
+  Thread* THREAD = thread;
+  debug_only(NoHandleMark nhm;)
+  {
+    // Enter VM mode
+
+    ResetNoHandleMark rnhm;
+    patch_code(thread, load_appendix_patching_id);
+  }
+  // Back in JAVA, use no oops DON'T safepoint
+
+  // Return true if calling code is deoptimized
+
+  return caller_is_deopted();
+}
+
 int Runtime1::move_klass_patching(JavaThread* thread) {
 //
 // NOTE: we are still in Java
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/c1_globals_aarch64.hpp
--- a/src/cpu/aarch64/vm/c1_globals_aarch64.hpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_globals_aarch64.hpp	Fri Oct 11 12:39:49 2013 +0100
@@ -59,8 +59,9 @@
 define_pd_global(intx, ReservedCodeCacheSize,        32*M );
 define_pd_global(bool, ProfileInterpreter,           false);
 define_pd_global(intx, CodeCacheExpansionSize,       32*K );
-define_pd_global(uintx,CodeCacheMinBlockLength,      1);
-define_pd_global(uintx,MetaspaceSize,                     12*M );
+define_pd_global(uintx, CodeCacheMinBlockLength,     1);
+define_pd_global(uintx, CodeCacheMinimumUseSpace,    400*K);
+define_pd_global(uintx, MetaspaceSize,               12*M );
 define_pd_global(bool, NeverActAsServerClassMachine, true );
 define_pd_global(uint64_t,MaxRAM,                    1ULL*G);
 define_pd_global(bool, CICompileOSR,                 true );
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/c2_globals_aarch64.hpp
--- a/src/cpu/aarch64/vm/c2_globals_aarch64.hpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/c2_globals_aarch64.hpp	Fri Oct 11 12:39:49 2013 +0100
@@ -46,7 +46,7 @@
 #else
 define_pd_global(bool, ProfileInterpreter,           true);
 #endif // CC_INTERP
-define_pd_global(bool, TieredCompilation,            false);
+define_pd_global(bool, TieredCompilation,            trueInTiered);
 define_pd_global(intx, CompileThreshold,             10000);
 define_pd_global(intx, BackEdgeThreshold,            100000);
 
@@ -54,6 +54,7 @@
 define_pd_global(intx, ConditionalMoveLimit,         3);
 define_pd_global(intx, FLOATPRESSURE,                30);
 define_pd_global(intx, FreqInlineSize,               325);
+define_pd_global(intx, MinJumpTableSize,             10);
 define_pd_global(intx, INTPRESSURE,                  23);
 define_pd_global(intx, InteriorEntryAlignment,       16);
 define_pd_global(intx, NewSizeThreadIncrease, ScaleForWordSize(4*K));
@@ -74,7 +75,8 @@
 define_pd_global(bool, OptoBundling,                 false);
 
 define_pd_global(intx, ReservedCodeCacheSize,        48*M);
-define_pd_global(uintx,CodeCacheMinBlockLength,      4);
+define_pd_global(uintx, CodeCacheMinBlockLength,     4);
+define_pd_global(uintx, CodeCacheMinimumUseSpace,    400*K);
 
 // Heap related flags
 define_pd_global(uintx,MetaspaceSize,    ScaleForWordSize(16*M));
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/cppInterpreterGenerator_aarch64.hpp
--- a/src/cpu/aarch64/vm/cppInterpreterGenerator_aarch64.hpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/cppInterpreterGenerator_aarch64.hpp	Fri Oct 11 12:39:49 2013 +0100
@@ -46,10 +46,12 @@
 
   void generate_more_monitors();
   void generate_deopt_handling();
+#if 0
   address generate_interpreter_frame_manager(bool synchronized); // C++ interpreter only
   void generate_compute_interpreter_state(const Register state,
                                           const Register prev_state,
                                           const Register sender_sp,
                                           bool native); // C++ interpreter only
+#endif
 
 #endif // CPU_AARCH64_VM_CPPINTERPRETERGENERATOR_AARCH64_HPP
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/frame_aarch64.cpp
--- a/src/cpu/aarch64/vm/frame_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/frame_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -35,6 +35,7 @@
 #include "runtime/handles.inline.hpp"
 #include "runtime/javaCalls.hpp"
 #include "runtime/monitorChunk.hpp"
+#include "runtime/os.hpp"
 #include "runtime/signature.hpp"
 #include "runtime/stubCodeGenerator.hpp"
 #include "runtime/stubRoutines.hpp"
@@ -56,16 +57,22 @@
   address   sp = (address)_sp;
   address   fp = (address)_fp;
   address   unextended_sp = (address)_unextended_sp;
-  // sp must be within the stack
-  bool sp_safe = (sp <= thread->stack_base()) &&
-                 (sp >= thread->stack_base() - thread->stack_size());
+
+  // consider stack guards when trying to determine "safe" stack pointers
+  static size_t stack_guard_size = os::uses_stack_guard_pages() ? (StackYellowPages + StackRedPages) * os::vm_page_size() : 0;
+  size_t usable_stack_size = thread->stack_size() - stack_guard_size;
+
+  // sp must be within the usable part of the stack (not in guards)
+  bool sp_safe = (sp < thread->stack_base()) &&
+                 (sp >= thread->stack_base() - usable_stack_size);
+
 
   if (!sp_safe) {
     return false;
   }
 
   // unextended sp must be within the stack and above or equal sp
-  bool unextended_sp_safe = (unextended_sp <= thread->stack_base()) &&
+  bool unextended_sp_safe = (unextended_sp < thread->stack_base()) &&
                             (unextended_sp >= sp);
 
   if (!unextended_sp_safe) {
@@ -73,7 +80,8 @@
   }
 
   // an fp must be within the stack and above (but not equal) sp
-  bool fp_safe = (fp <= thread->stack_base()) && (fp > sp);
+  // second evaluation on fp+ is added to handle situation where fp is -1
+  bool fp_safe = (fp < thread->stack_base() && (fp > sp) && (((fp + (return_addr_offset * sizeof(void*))) < thread->stack_base())));
 
   // We know sp/unextended_sp are safe only fp is questionable here
 
@@ -88,6 +96,13 @@
     // other generic buffer blobs are more problematic so we just assume they are
     // ok. adapter blobs never have a frame complete and are never ok.
 
+    // check for a valid frame_size, otherwise we are unlikely to get a valid sender_pc
+
+    if (!Interpreter::contains(_pc) && _cb->frame_size() <= 0) {
+      //assert(0, "Invalid frame_size");
+      return false;
+    }
+
     if (!_cb->is_frame_complete_at(_pc)) {
       if (_cb->is_nmethod() || _cb->is_adapter_blob() || _cb->is_runtime_stub()) {
         return false;
@@ -109,7 +124,7 @@
 
       address jcw = (address)entry_frame_call_wrapper();
 
-      bool jcw_safe = (jcw <= thread->stack_base()) && ( jcw > fp);
+      bool jcw_safe = (jcw < thread->stack_base()) && ( jcw > fp);
 
       return jcw_safe;
 
@@ -135,12 +150,6 @@
       sender_pc = (address) *(sender_sp-1);
     }
 
-    // We must always be able to find a recognizable pc
-    CodeBlob* sender_blob = CodeCache::find_blob_unsafe(sender_pc);
-    if (sender_pc == NULL ||  sender_blob == NULL) {
-      return false;
-    }
-
 
     // If the potential sender is the interpreter then we can do some more checking
     if (Interpreter::contains(sender_pc)) {
@@ -150,7 +159,7 @@
       // is really a frame pointer.
 
       intptr_t *saved_fp = (intptr_t*)*(sender_sp - frame::sender_sp_offset);
-      bool saved_fp_safe = ((address)saved_fp <= thread->stack_base()) && (saved_fp > sender_sp);
+      bool saved_fp_safe = ((address)saved_fp < thread->stack_base()) && (saved_fp > sender_sp);
 
       if (!saved_fp_safe) {
         return false;
@@ -164,6 +173,17 @@
 
     }
 
+    // We must always be able to find a recognizable pc
+    CodeBlob* sender_blob = CodeCache::find_blob_unsafe(sender_pc);
+    if (sender_pc == NULL ||  sender_blob == NULL) {
+      return false;
+    }
+
+    // Could be a zombie method
+    if (sender_blob->is_zombie() || sender_blob->is_unloaded()) {
+      return false;
+    }
+
     // Could just be some random pointer within the codeBlob
     if (!sender_blob->code_contains(sender_pc)) {
       return false;
@@ -175,10 +195,9 @@
     }
 
     // Could be the call_stub
-
     if (StubRoutines::returns_to_call_stub(sender_pc)) {
       intptr_t *saved_fp = (intptr_t*)*(sender_sp - frame::sender_sp_offset);
-      bool saved_fp_safe = ((address)saved_fp <= thread->stack_base()) && (saved_fp > sender_sp);
+      bool saved_fp_safe = ((address)saved_fp < thread->stack_base()) && (saved_fp > sender_sp);
 
       if (!saved_fp_safe) {
         return false;
@@ -191,15 +210,24 @@
       // Validate the JavaCallWrapper an entry frame must have
       address jcw = (address)sender.entry_frame_call_wrapper();
 
-      bool jcw_safe = (jcw <= thread->stack_base()) && ( jcw > (address)sender.fp());
+      bool jcw_safe = (jcw < thread->stack_base()) && ( jcw > (address)sender.fp());
 
       return jcw_safe;
     }
 
-    // If the frame size is 0 something is bad because every nmethod has a non-zero frame size
+    if (sender_blob->is_nmethod()) {
+        nmethod* nm = sender_blob->as_nmethod_or_null();
+        if (nm != NULL) {
+            if (nm->is_deopt_mh_entry(sender_pc) || nm->is_deopt_entry(sender_pc)) {
+                return false;
+            }
+        }
+    }
+
+    // If the frame size is 0 something (or less) is bad because every nmethod has a non-zero frame size
     // because the return address counts against the callee's frame.
 
-    if (sender_blob->frame_size() == 0) {
+    if (sender_blob->frame_size() <= 0) {
       assert(!sender_blob->is_nmethod(), "should count return address at least");
       return false;
     }
@@ -209,7 +237,9 @@
     // should not be anything but the call stub (already covered), the interpreter (already covered)
     // or an nmethod.
 
-    assert(sender_blob->is_nmethod(), "Impossible call chain");
+    if (!sender_blob->is_nmethod()) {
+        return false;
+    }
 
     // Could put some more validation for the potential non-interpreted sender
     // frame we'd create by calling sender if I could think of any. Wait for next crash in forte...
@@ -238,8 +268,6 @@
 
 }
 
-
-
 void frame::patch_pc(Thread* thread, address pc) {
   address* pc_addr = &(((address*) sp())[-1]);
   if (TracePcPatching) {
@@ -559,11 +587,9 @@
     return false;
   }
 
-  // validate constantPoolCacheOop
-
+  // validate constantPoolCache*
   ConstantPoolCache* cp = *interpreter_frame_cache_addr();
-
-  if (cp == NULL || !cp->is_metadata()) return false;
+  if (cp == NULL || !cp->is_metaspace_object()) return false;
 
   // validate locals
 
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/frame_aarch64.inline.hpp
--- a/src/cpu/aarch64/vm/frame_aarch64.inline.hpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/frame_aarch64.inline.hpp	Fri Oct 11 12:39:49 2013 +0100
@@ -294,8 +294,8 @@
 
 // Entry frames
 
-inline JavaCallWrapper* frame::entry_frame_call_wrapper() const {
- return (JavaCallWrapper*)at(entry_frame_call_wrapper_offset);
+inline JavaCallWrapper** frame::entry_frame_call_wrapper_addr() const {
+ return (JavaCallWrapper**)addr_at(entry_frame_call_wrapper_offset);
 }
 
 
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/globals_aarch64.hpp
--- a/src/cpu/aarch64/vm/globals_aarch64.hpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/globals_aarch64.hpp	Fri Oct 11 12:39:49 2013 +0100
@@ -69,7 +69,7 @@
 define_pd_global(bool, UseMembar,            true);
 
 // GC Ergo Flags
-define_pd_global(intx, CMSYoungGenPerWorker, 64*M);  // default max size of CMS young gen, per GC worker thread
+define_pd_global(uintx, CMSYoungGenPerWorker, 64*M);  // default max size of CMS young gen, per GC worker thread
 
 // avoid biased locking while we are bootstrapping the aarch64 build
 define_pd_global(bool, UseBiasedLocking, false);
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -339,7 +339,7 @@
   assert(java_thread == rthread, "unexpected register");
 #ifdef ASSERT
   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
-  // if ((UseCompressedOops || UseCompressedKlassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
+  // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
 #endif // ASSERT
 
   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
@@ -1550,7 +1550,7 @@
 #ifdef ASSERT 
 void MacroAssembler::verify_heapbase(const char* msg) {
 #if 0
-  assert (UseCompressedOops || UseCompressedKlassPointers, "should be compressed");
+  assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
   assert (Universe::heap() != NULL, "java heap should be initialized");
   if (CheckCompressedOops) {
     Label ok;
@@ -1641,79 +1641,6 @@
   }
 }
 
-#ifdef ASSERT
-static Register spill_registers[] = {
-  rheapbase,
-  rcpool,
-  rmonitors,
-  rlocals,
-  rmethod
-};
-
-#define spill_msg(_reg) \
-  "register " _reg " invalid after call"
-
-static const char *spill_error_msgs[] = {
-  spill_msg("rheapbase"),
-  spill_msg("rcpool"),
-  spill_msg("rmonitors"),
-  spill_msg("rlocals"),
-  spill_msg("rmethod")
-};
-
-#define SPILL_FRAME_COUNT (sizeof(spill_registers)/sizeof(spill_registers[0]))
-
-#define SPILL_FRAME_BYTESIZE (SPILL_FRAME_COUNT * wordSize)
-
-void MacroAssembler::spill(Register rscratcha, Register rscratchb)
-{
-#if 0
-  Label bumped;
-  // load and bump spill pointer
-  ldr(rscratcha, Address(rthread, JavaThread::spill_stack_offset()));
-  sub(rscratcha, rscratcha, SPILL_FRAME_BYTESIZE);
-  // check for overflow
-  ldr(rscratchb, Address(rthread, JavaThread::spill_stack_limit_offset()));
-  cmp(rscratcha, rscratchb);
-  br(Assembler::GE, bumped);
-  stop("oops! ran out of register spill area");
-  // spill registers
-  bind(bumped);
-  for (int i = 0; i < (int)SPILL_FRAME_COUNT; i++) {
-    Register r = spill_registers[i];
-    assert(r != rscratcha && r != rscratchb, "invalid scratch reg in spill");
-    str(r, Address(rscratcha, (i * wordSize)));
-  }
-  // store new spill pointer
-  str(rscratcha, (Address(rthread, JavaThread::spill_stack_offset())));
-#endif
-}
-
-void MacroAssembler::spillcheck(Register rscratcha, Register rscratchb)
-{
-#if 0
-  // load spill pointer
-  ldr(rscratcha, (Address(rthread, JavaThread::spill_stack_offset())));
-  // check registers
-  for (int i = 0; i < (int)SPILL_FRAME_COUNT; i++) {
-    Register r = spill_registers[i];
-    assert(r != rscratcha && r != rscratchb, "invalid scratch reg in spillcheck");
-    // native code is allowed to modify rcpool
-    Label valid;
-    ldr(rscratchb, Address(rscratcha, (i * wordSize)));
-    cmp(r, rscratchb);
-    br(Assembler::EQ, valid);
-    stop(spill_error_msgs[i]);
-    bind(valid);
-  }
-  // decrement and store new spill pointer
-  add(rscratcha, rscratcha, SPILL_FRAME_BYTESIZE);
-  str(rscratcha, Address(rthread, JavaThread::spill_stack_offset()));
-#endif
-}
-
-#endif // ASSERT
-
 void MacroAssembler::reinit_heapbase()
 {
   if (UseCompressedOops) {
@@ -1994,7 +1921,7 @@
 }
 
 void MacroAssembler::load_klass(Register dst, Register src) {
-  if (UseCompressedKlassPointers) {
+  if (UseCompressedClassPointers) {
     ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
     decode_klass_not_null(dst);
   } else {
@@ -2003,7 +1930,7 @@
 }
 
 void MacroAssembler::store_klass(Register dst, Register src) {
-  if (UseCompressedKlassPointers) {
+  if (UseCompressedClassPointers) {
     encode_klass_not_null(src);
     strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
   } else {
@@ -2012,7 +1939,7 @@
 }
 
 void MacroAssembler::store_klass_gap(Register dst, Register src) {
-  if (UseCompressedKlassPointers) {
+  if (UseCompressedClassPointers) {
     // Store to klass gap in destination
     str(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
   }
@@ -2152,7 +2079,6 @@
 }
 
 void MacroAssembler::encode_klass_not_null(Register r) {
-  assert(Metaspace::is_initialized(), "metaspace should be initialized");
 #ifdef ASSERT
   verify_heapbase("MacroAssembler::encode_klass_not_null: heap base corrupted?");
 #endif
@@ -2166,7 +2092,6 @@
 }
 
 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
-  assert(Metaspace::is_initialized(), "metaspace should be initialized");
 #ifdef ASSERT
   verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
 #endif
@@ -2183,9 +2108,8 @@
 }
 
 void  MacroAssembler::decode_klass_not_null(Register r) {
-  assert(Metaspace::is_initialized(), "metaspace should be initialized");
   // Note: it will change flags
-  assert (UseCompressedKlassPointers, "should only be used for compressed headers");
+  assert (UseCompressedClassPointers, "should only be used for compressed headers");
   // Cannot assert, unverified entry point counts instructions (see .ad file)
   // vtableStubs also counts instructions in pd_code_size_limit.
   // Also do not verify_oop as this is called by verify_oop.
@@ -2202,9 +2126,8 @@
 }
 
 void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
-  assert(Metaspace::is_initialized(), "metaspace should be initialized");
   // Note: it will change flags
-  assert (UseCompressedKlassPointers, "should only be used for compressed headers");
+  assert (UseCompressedClassPointers, "should only be used for compressed headers");
   // Cannot assert, unverified entry point counts instructions (see .ad file)
   // vtableStubs also counts instructions in pd_code_size_limit.
   // Also do not verify_oop as this is called by verify_oop.
@@ -2242,7 +2165,7 @@
 
 
 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
-  assert (UseCompressedKlassPointers, "should only be used for compressed headers");
+  assert (UseCompressedClassPointers, "should only be used for compressed headers");
   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
   mov_metadata(dst, k);
   encode_klass_not_null(dst);
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Fri Oct 11 12:39:49 2013 +0100
@@ -535,14 +535,6 @@
   void enter();
   void leave();
 
-  // debug only support for spilling and restoring/checking callee
-  // save registers around a Java method call
-
-#ifdef ASSERT
-  void spill(Register rscratcha, Register rscratchb);
-  void spillcheck(Register rscratcha, Register rscratchb);
-#endif // ASSERT
-
   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
   // The pointer will be loaded into the thread register.
   void get_thread(Register thread);
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/relocInfo_aarch64.cpp
--- a/src/cpu/aarch64/vm/relocInfo_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/relocInfo_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -58,13 +58,6 @@
   return MacroAssembler::pd_call_destination(addr());
 }
 
-int Relocation::pd_breakpoint_size() { Unimplemented(); return 0; }
-
-void Relocation::pd_swap_in_breakpoint(address x, short* instrs, int instrlen) { Unimplemented(); }
-
-
-void Relocation::pd_swap_out_breakpoint(address x, short* instrs, int instrlen) { Unimplemented(); }
-
 void poll_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
   // fprintf(stderr, "Try to fix poll reloc at %p to %p\n", addr(), dest);
   if (NativeInstruction::maybe_cpool_ref(addr())) {
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -71,7 +71,7 @@
  private:
 
 #ifdef PRODUCT
-#define inc_counter_np(counter) (0)
+#define inc_counter_np(counter) ((void)0)
 #else
   void inc_counter_np_(int& counter) {
     __ lea(rscratch2, ExternalAddress((address)&counter));
@@ -751,7 +751,6 @@
     // make sure klass is 'reasonable', which is not zero.
     __ load_klass(r0, r0);  // get klass
     __ cbz(r0, error);      // if klass is NULL it is broken
-    // TODO: Future assert that klass is lower 4g memory for UseCompressedKlassPointers
 
     // return if everything seems ok
     __ bind(exit);
@@ -1714,6 +1713,47 @@
 
   void generate_math_stubs() { Unimplemented(); }
 
+#ifndef BUILTIN_SIM
+  // Safefetch stubs.
+  void generate_safefetch(const char* name, int size, address* entry,
+                          address* fault_pc, address* continuation_pc) {
+    // safefetch signatures:
+    //   int      SafeFetch32(int*      adr, int      errValue);
+    //   intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue);
+    //
+    // arguments:
+    //   c_rarg0 = adr
+    //   c_rarg1 = errValue
+    //
+    // result:
+    //   PPC_RET  = *adr or errValue
+
+    StubCodeMark mark(this, "StubRoutines", name);
+
+    // Entry point, pc or function descriptor.
+    *entry = __ pc();
+
+    // Load *adr into c_rarg1, may fault.
+    *fault_pc = __ pc();
+    switch (size) {
+      case 4:
+        // int32_t
+	__ ldrw(c_rarg0, Address(c_rarg0, 0));
+        break;
+      case 8:
+        // int64_t
+	__ ldr(c_rarg0, Address(c_rarg0, 0));
+        break;
+      default:
+        ShouldNotReachHere();
+    }
+
+    // return errValue or *adr
+    *continuation_pc = __ pc();
+    __ ret(lr);
+  }
+#endif
+
 #undef __
 #define __ masm->
 
@@ -1917,6 +1957,16 @@
 
     // arraycopy stubs used by compilers
     generate_arraycopy_stubs();
+
+#ifndef BUILTIN_SIM
+    // Safefetch stubs.
+    generate_safefetch("SafeFetch32", sizeof(int),     &StubRoutines::_safefetch32_entry,
+                                                       &StubRoutines::_safefetch32_fault_pc,
+                                                       &StubRoutines::_safefetch32_continuation_pc);
+    generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry,
+                                                       &StubRoutines::_safefetchN_fault_pc,
+                                                       &StubRoutines::_safefetchN_continuation_pc);
+#endif
   }
 
  public:
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -208,9 +208,6 @@
   __ sub(rscratch1, rscratch2, rscratch1, ext::uxtw, 3);
   __ andr(sp, rscratch1, -16);
 
-#ifdef ASSERT
-  __ spillcheck(rscratch1, rscratch2);
-#endif // ASSERT
 #ifndef PRODUCT
   // tell the simulator that the method has been reentered
   if (NotifySimulator) {
@@ -1435,8 +1432,7 @@
     -(frame::interpreter_frame_initial_sp_offset) + entry_size;
 
   const int stub_code = frame::entry_frame_after_call_words;
-  const int extra_stack = Method::extra_stack_entries();
-  const int method_stack = (method->max_locals() + method->max_stack() + extra_stack) *
+  const int method_stack = (method->max_locals() + method->max_stack()) *
                            Interpreter::stackElementWords;
   return (overhead_size + method_stack + stub_code);
 }
@@ -1711,6 +1707,27 @@
   __ str(zr, Address(rthread, JavaThread::popframe_condition_offset()));
   assert(JavaThread::popframe_inactive == 0, "fix popframe_inactive");
 
+#if INCLUDE_JVMTI
+  if (EnableInvokeDynamic) {
+    Label L_done;
+
+    __ ldrb(rscratch1, Address(r13, 0));
+    __ cmpw(r1, Bytecodes::_invokestatic);
+    __ br(Assembler::EQ, L_done);
+
+    // The member name argument must be restored if _invokestatic is re-executed after a PopFrame call.
+    // Detect such a case in the InterpreterRuntime function and return the member name argument, or NULL.
+
+    __ ldr(c_rarg0, Address(rlocals, 0));
+    __ call_VM(r0, CAST_FROM_FN_PTR(address, InterpreterRuntime::member_name_arg_or_null), c_rarg0, rmethod, rscratch1);
+
+    __ cbz(r0, L_done);
+
+    __ str(r0, Address(esp, 0));
+    __ bind(L_done);
+  }
+#endif // INCLUDE_JVMTI
+
   __ dispatch_next(vtos);
   // end of PopFrame support
 
diff -r a84cf0dd740c -r 0b5e450b2321 src/cpu/aarch64/vm/templateTable_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -2955,10 +2955,6 @@
   transition(vtos, vtos);
   assert(byte_no == f2_byte, "use this argument");
 
-#ifdef ASSERT
-  __ spill(rscratch1, rscratch2);
-#endif // ASSERT
-
   prepare_invoke(byte_no, rmethod, noreg, r2, r3);
 
   // rmethod: index (actually a Method*)
@@ -2973,10 +2969,6 @@
   transition(vtos, vtos);
   assert(byte_no == f1_byte, "use this argument");
 
-#ifdef ASSERT
-  __ spill(rscratch1, rscratch2);
-#endif // ASSERT
-
   prepare_invoke(byte_no, rmethod, noreg,  // get f1 Method*
 		 r2);  // get receiver also for null check
   __ verify_oop(r2);
@@ -2991,10 +2983,6 @@
   transition(vtos, vtos);
   assert(byte_no == f1_byte, "use this argument");
 
-#ifdef ASSERT
-  __ spill(rscratch1, rscratch2);
-#endif // ASSERT
-
   prepare_invoke(byte_no, rmethod);  // get f1 Method*
   // do the call
   __ profile_call(r0);
@@ -3010,10 +2998,6 @@
   transition(vtos, vtos);
   assert(byte_no == f1_byte, "use this argument");
 
-#ifdef ASSERT
-  __ spill(rscratch1, rscratch2);
-#endif // ASSERT
-
   prepare_invoke(byte_no, r0, rmethod,  // get f1 Klass*, f2 itable index
 		 r2, r3); // recv, flags
 
diff -r a84cf0dd740c -r 0b5e450b2321 src/os/linux/vm/os_linux.cpp
--- a/src/os/linux/vm/os_linux.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/os/linux/vm/os_linux.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -3325,9 +3325,9 @@
   // format has been changed), we'll use the largest page size supported by
   // the processor.
 
-#if !defined(ZERO)
+#ifndef ZERO
   large_page_size = IA32_ONLY(4 * M) AMD64_ONLY(2 * M) IA64_ONLY(256 * M) SPARC_ONLY(4 * M)
-                       ARM_ONLY(2 * M) PPC_ONLY(4 * M);
+                     ARM_ONLY(2 * M) PPC_ONLY(4 * M) AARCH64_ONLY(2 * M);
 #endif // ZERO
 
   FILE *fp = fopen("/proc/meminfo", "r");
diff -r a84cf0dd740c -r 0b5e450b2321 src/os_cpu/linux_aarch64/vm/linux_aarch64.S
--- a/src/os_cpu/linux_aarch64/vm/linux_aarch64.S	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/os_cpu/linux_aarch64/vm/linux_aarch64.S	Fri Oct 11 12:39:49 2013 +0100
@@ -1,28 +1,4 @@
-        .text
-
-#ifndef BUILTIN_SIM
-
-        .globl SafeFetch32, Fetch32PFI, Fetch32Resume
-        .align  16
-        .type   SafeFetch32, at function
-        // Prototype: int SafeFetch32 (int * Adr, int ErrValue)
-SafeFetch32:
-Fetch32PFI:
-	ldr	w0, [x0]
-Fetch32Resume:
-        ret
-
-        .globl SafeFetchN, FetchNPFI, FetchNResume
-        .align  16
-        .type   SafeFetchN, at function
-        // Prototype: intptr_t SafeFetchN (intptr_t * Adr, intptr_t ErrValue)
-SafeFetchN:
-FetchNPFI:
-	ldr	x0, [x0]
-FetchNResume:
-        ret
-
-#else
+#ifdef BUILTIN_SIM
 
         .globl SafeFetch32, Fetch32PFI, Fetch32Resume
         .align  16
diff -r a84cf0dd740c -r 0b5e450b2321 src/os_cpu/linux_aarch64/vm/os_linux_aarch64.cpp
--- a/src/os_cpu/linux_aarch64/vm/os_linux_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/os_cpu/linux_aarch64/vm/os_linux_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -104,21 +104,6 @@
 }
 
 void os::initialize_thread(Thread *thr) {
-#ifdef ASSERT
-  if (!thr->is_Java_thread()) {
-    // Nothing to do!
-    return;
-  }
-
-  JavaThread *java_thread = (JavaThread *)thr;
-  // spill frames are a fixed size of N (== 6?) saved registers at 8
-  // bytes per register a 64K byte stack allows a call depth of 8K / N
-#define SPILL_STACK_SIZE (1 << 16)
-  // initalise the spill stack so we cna check callee-save registers
-  address spill_stack = new unsigned char[SPILL_STACK_SIZE];
-  java_thread->set_spill_stack(spill_stack + SPILL_STACK_SIZE);
-  java_thread->set_spill_stack_limit(spill_stack);
-#endif // ASSERT
 }
 
 address os::Linux::ucontext_get_pc(ucontext_t * uc) {
@@ -219,10 +204,12 @@
   trap_page_fault = 0xE
 };
 
+#ifdef BUILTIN_SIM
 extern "C" void Fetch32PFI () ;
 extern "C" void Fetch32Resume () ;
 extern "C" void FetchNPFI () ;
 extern "C" void FetchNResume () ;
+#endif
 
 extern "C" JNIEXPORT int
 JVM_handle_linux_signal(int sig,
@@ -233,6 +220,10 @@
 
   Thread* t = ThreadLocalStorage::get_thread_slow();
 
+  // Must do this before SignalHandlerMark, if crash protection installed we will longjmp away
+  // (no destructors can be run)
+  os::WatcherThreadCrashProtection::check_crash_protection(sig, t);
+
   SignalHandlerMark shm(t);
 
   // Note: it's not uncommon that JNI code uses signal/sigset to install
@@ -286,22 +277,31 @@
   if (info != NULL && uc != NULL && thread != NULL) {
     pc = (address) os::Linux::ucontext_get_pc(uc);
 
+#ifdef BUILTIN_SIM
     if (pc == (address) Fetch32PFI) {
-#ifdef BUILTIN_SIM
        uc->uc_mcontext.gregs[REG_PC] = intptr_t(Fetch32Resume) ;
-#else
-       uc->uc_mcontext.pc = intptr_t(Fetch32Resume) ;
-#endif
        return 1 ;
     }
     if (pc == (address) FetchNPFI) {
-#ifdef BUILTIN_SIM
        uc->uc_mcontext.gregs[REG_PC] = intptr_t (FetchNResume) ;
-#else
-       uc->uc_mcontext.pc = intptr_t (FetchNResume) ;
-#endif
        return 1 ;
     }
+#else
+    if (StubRoutines::is_safefetch_fault(pc)) {
+      uc->uc_mcontext.pc = intptr_t(StubRoutines::continuation_for_safefetch_fault(pc));
+      return 1;
+    }
+#endif
+
+#ifndef AMD64
+    // Halt if SI_KERNEL before more crashes get misdiagnosed as Java bugs
+    // This can happen in any running code (currently more frequently in
+    // interpreter code but has been seen in compiled code)
+    if (sig == SIGSEGV && info->si_addr == 0 && info->si_code == SI_KERNEL) {
+      fatal("An irrecoverable SI_KERNEL SIGSEGV has occurred due "
+            "to unstable signal handling in this distribution.");
+    }
+#endif // AMD64
 
     // Handle ALL stack overflow variations here
     if (sig == SIGSEGV) {
diff -r a84cf0dd740c -r 0b5e450b2321 src/os_cpu/linux_aarch64/vm/thread_linux_aarch64.cpp
--- a/src/os_cpu/linux_aarch64/vm/thread_linux_aarch64.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/os_cpu/linux_aarch64/vm/thread_linux_aarch64.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -32,8 +32,15 @@
   void* ucontext, bool isInJava) {
 
   assert(Thread::current() == this, "caller must be current thread");
+  return pd_get_top_frame(fr_addr, ucontext, isInJava);
+}
+
+bool JavaThread::pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext, bool isInJava) {
+  return pd_get_top_frame(fr_addr, ucontext, isInJava);
+}
+
+bool JavaThread::pd_get_top_frame(frame* fr_addr, void* ucontext, bool isInJava) {
   assert(this->is_Java_thread(), "must be JavaThread");
-
   JavaThread* jt = (JavaThread *)this;
 
   // If we have a last_Java_frame, then we should use it even if
diff -r a84cf0dd740c -r 0b5e450b2321 src/os_cpu/linux_aarch64/vm/thread_linux_aarch64.hpp
--- a/src/os_cpu/linux_aarch64/vm/thread_linux_aarch64.hpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/os_cpu/linux_aarch64/vm/thread_linux_aarch64.hpp	Fri Oct 11 12:39:49 2013 +0100
@@ -71,21 +71,15 @@
   bool pd_get_top_frame_for_signal_handler(frame* fr_addr, void* ucontext,
     bool isInJava);
 
+  bool pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext, bool isInJava);
+private:
+  bool pd_get_top_frame(frame* fr_addr, void* ucontext, bool isInJava);
+public:
+
   // These routines are only used on cpu architectures that
   // have separate register stacks (Itanium).
   static bool register_stack_overflow() { return false; }
   static void enable_register_stack_guard() {}
   static void disable_register_stack_guard() {}
 
-#ifdef ASSERT
-  void    set_spill_stack(address base) { _spill_stack = _spill_stack_base = base; }
-  void    set_spill_stack_limit(address limit)  { _spill_stack_limit = limit; }
-  static ByteSize spill_stack_offset() {
-    return byte_offset_of(JavaThread, _spill_stack) ;
-  };
-  static ByteSize spill_stack_limit_offset() {
-    return byte_offset_of(JavaThread, _spill_stack_limit) ;
-  };
-#endif
-
 #endif // OS_CPU_LINUX_AARCH64_VM_THREAD_LINUX_AARCH64_HPP
diff -r a84cf0dd740c -r 0b5e450b2321 src/share/tools/hsdis/hsdis.c
--- a/src/share/tools/hsdis/hsdis.c	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/share/tools/hsdis/hsdis.c	Fri Oct 11 12:39:49 2013 +0100
@@ -28,7 +28,6 @@
 */
 
 #include <config.h>
-#endif
 #include <libiberty.h>
 #include <bfd.h>
 #include <dis-asm.h>
diff -r a84cf0dd740c -r 0b5e450b2321 src/share/vm/c1/c1_Compilation.cpp
--- a/src/share/vm/c1/c1_Compilation.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/share/vm/c1/c1_Compilation.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -343,8 +343,10 @@
     // 3 bytes per character.  We concatenate three such strings.
     // Yes, I know this is ridiculous, but it's debug code and glibc
     // allocates large arrays very efficiently.
-    size_t len = (65536 * 3) * 3;
-    char *name = new char[len];
+//    size_t len = (65536 * 3) * 3;
+//    char *name = new char[len];
+    size_t len = 1024;
+    char name[1024];
 
     strncpy(name, _method->holder()->name()->as_utf8(), len);
     strncat(name, ".", len);
@@ -352,7 +354,7 @@
     strncat(name, _method->signature()->as_symbol()->as_utf8(), len);
     unsigned char *base = code()->insts()->start();
     AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck)->notifyCompile(name, base);
-    delete[] name;
+//    delete[] name;
   }
 #endif
 
diff -r a84cf0dd740c -r 0b5e450b2321 src/share/vm/c1/c1_Runtime1.cpp
--- a/src/share/vm/c1/c1_Runtime1.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/share/vm/c1/c1_Runtime1.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -235,8 +235,10 @@
                                                  sasm->must_gc_arguments());
 #ifdef BUILTIN_SIM
   if (NotifySimulator) {
-    size_t len = 65536;
-    char *name = new char[len];
+//    size_t len = 65536;
+//    char *name = new char[len];
+    size_t len = 1024;
+    char name[1024];
 
     // tell the sim about the new stub code
     AArch64Simulator *simulator = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck);
@@ -249,7 +251,7 @@
     simulator->notifyCompile(name, base);
     // code does not get relocated so just pass offset 0 and the code is live
     simulator->notifyRelocate(base, 0);
-    delete[] name;
+//    delete[] name;
   }
 #endif
   // install blob
@@ -1067,7 +1069,7 @@
           ShouldNotReachHere();
         }
 
-#if defined(SPARC) || defined(PPC) || defined(TARGET_ARCH_aarch64)
+#if defined(SPARC) || defined(PPC) || defined(AARCH64)
         if (load_klass_or_mirror_patch_id ||
             stub_id == Runtime1::load_appendix_patching_id) {
           // Update the location in the nmethod with the proper
@@ -1139,7 +1141,9 @@
           ICache::invalidate_range(instr_pc, *byte_count);
           NativeGeneralJump::replace_mt_safe(instr_pc, copy_buff);
 
-          if (load_klass_or_mirror_patch_id) {
+          if (load_klass_or_mirror_patch_id
+              || stub_id == Runtime1::load_appendix_patching_id
+	      || stub_id == Runtime1::access_field_patching_id) {
             relocInfo::relocType rtype;
 	    switch(stub_id) {
 	    case Runtime1::load_klass_patching_id:
diff -r a84cf0dd740c -r 0b5e450b2321 src/share/vm/runtime/arguments.cpp
--- a/src/share/vm/runtime/arguments.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/share/vm/runtime/arguments.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -1459,7 +1459,6 @@
 #endif // ZERO
 }
 
-
 // NOTE: set_use_compressed_klass_ptrs() must be called after calling
 // set_use_compressed_oops().
 void Arguments::set_use_compressed_klass_ptrs() {
@@ -1472,10 +1471,13 @@
     }
     FLAG_SET_DEFAULT(UseCompressedClassPointers, false);
   } else {
+// ECN: FIXME - UseCompressedClassPointers is temporarily broken
+#ifndef AARCH64
     // Turn on UseCompressedClassPointers too
     if (FLAG_IS_DEFAULT(UseCompressedClassPointers)) {
       FLAG_SET_ERGO(bool, UseCompressedClassPointers, true);
     }
+#endif
     // Check the CompressedClassSpaceSize to make sure we use compressed klass ptrs.
     if (UseCompressedClassPointers) {
       if (CompressedClassSpaceSize > KlassEncodingMetaspaceMax) {
diff -r a84cf0dd740c -r 0b5e450b2321 src/share/vm/runtime/os.hpp
--- a/src/share/vm/runtime/os.hpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/share/vm/runtime/os.hpp	Fri Oct 11 12:39:49 2013 +0100
@@ -959,5 +959,9 @@
 // It'd also be eligible for inlining on many platforms.
 
 extern "C" int SpinPause();
+#ifdef BUILTIN_SIM
+extern "C" int SafeFetch32(int * adr, int errValue) ;
+extern "C" intptr_t SafeFetchN(intptr_t * adr, intptr_t errValue) ;
+#endif
 
 #endif // SHARE_VM_RUNTIME_OS_HPP
diff -r a84cf0dd740c -r 0b5e450b2321 src/share/vm/runtime/reflection.cpp
--- a/src/share/vm/runtime/reflection.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/share/vm/runtime/reflection.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -374,8 +374,9 @@
   }
   klass = klass->array_klass(dim, CHECK_NULL);
   oop obj = ArrayKlass::cast(klass)->multi_allocate(len, dimensions, CHECK_NULL);
-  // obj may be NULL is one of the dimensions is 0
-  assert(obj == NULL || obj->is_array(), "just checking");
+  // ECN: obj may be NULL if one of the dimensions is 0?
+  assert(obj != NULL, "can obj be NULL here?");
+  assert(obj->is_array(), "just checking");
   return arrayOop(obj);
 }
 
diff -r a84cf0dd740c -r 0b5e450b2321 src/share/vm/runtime/stubRoutines.cpp
--- a/src/share/vm/runtime/stubRoutines.cpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/share/vm/runtime/stubRoutines.cpp	Fri Oct 11 12:39:49 2013 +0100
@@ -136,12 +136,14 @@
 double (* StubRoutines::_intrinsic_cos   )(double) = NULL;
 double (* StubRoutines::_intrinsic_tan   )(double) = NULL;
 
+#ifndef BUILTIN_SIM
 address StubRoutines::_safefetch32_entry                 = NULL;
 address StubRoutines::_safefetch32_fault_pc              = NULL;
 address StubRoutines::_safefetch32_continuation_pc       = NULL;
 address StubRoutines::_safefetchN_entry                  = NULL;
 address StubRoutines::_safefetchN_fault_pc               = NULL;
 address StubRoutines::_safefetchN_continuation_pc        = NULL;
+#endif
 
 // Initialization
 //
diff -r a84cf0dd740c -r 0b5e450b2321 src/share/vm/runtime/stubRoutines.hpp
--- a/src/share/vm/runtime/stubRoutines.hpp	Fri Oct 11 12:06:22 2013 +0100
+++ b/src/share/vm/runtime/stubRoutines.hpp	Fri Oct 11 12:39:49 2013 +0100
@@ -227,6 +227,7 @@
   static double (*_intrinsic_cos)(double);
   static double (*_intrinsic_tan)(double);
 
+#ifndef BUILTIN_SIM
   // Safefetch stubs.
   static address _safefetch32_entry;
   static address _safefetch32_fault_pc;
@@ -234,6 +235,7 @@
   static address _safefetchN_entry;
   static address _safefetchN_fault_pc;
   static address _safefetchN_continuation_pc;
+#endif
 
  public:
   // Initialization/Testing
@@ -395,10 +397,10 @@
     return _intrinsic_tan(d);
   }
 
+#ifndef BUILTIN_SIM
   //
   // Safefetch stub support
   //
-
   typedef int      (*SafeFetch32Stub)(int*      adr, int      errValue);
   typedef intptr_t (*SafeFetchNStub) (intptr_t* adr, intptr_t errValue);
 
@@ -422,6 +424,7 @@
     ShouldNotReachHere();
     return NULL;
   }
+#endif
 
   //
   // Default versions of the above arraycopy functions for platforms which do
@@ -442,6 +445,7 @@
   static void arrayof_oop_copy_uninit(HeapWord* src, HeapWord* dest, size_t count);
 };
 
+#ifndef BUILTIN_SIM
 // Safefetch allows to load a value from a location that's not known
 // to be valid. If the load causes a fault, the error value is returned.
 inline int SafeFetch32(int* adr, int errValue) {
@@ -452,5 +456,6 @@
   assert(StubRoutines::SafeFetchN_stub(), "stub not yet generated");
   return StubRoutines::SafeFetchN_stub()(adr, errValue);
 }
+#endif
 
 #endif // SHARE_VM_RUNTIME_STUBROUTINES_HPP
diff -r a84cf0dd740c -r 0b5e450b2321 test/gc/metaspace/TestPerfCountersAndMemoryPools.java
--- a/test/gc/metaspace/TestPerfCountersAndMemoryPools.java	Fri Oct 11 12:06:22 2013 +0100
+++ b/test/gc/metaspace/TestPerfCountersAndMemoryPools.java	Fri Oct 11 12:39:49 2013 +0100
@@ -31,14 +31,14 @@
  * @bug 8023476
  * @summary Tests that a MemoryPoolMXBeans and PerfCounters for metaspace
  *          report the same data.
- * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:-UseCompressedOops -XX:-UseCompressedKlassPointers -XX:+UseSerialGC -XX:+UsePerfData TestPerfCountersAndMemoryPools
- * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:+UseCompressedOops -XX:+UseCompressedKlassPointers -XX:+UseSerialGC -XX:+UsePerfData TestPerfCountersAndMemoryPools
+ * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:-UseCompressedOops -XX:-UseCompressedClassPointers -XX:+UseSerialGC -XX:+UsePerfData TestPerfCountersAndMemoryPools
+ * @run main/othervm -XX:+IgnoreUnrecognizedVMOptions -XX:+UseCompressedOops -XX:+UseCompressedClassPointers -XX:+UseSerialGC -XX:+UsePerfData TestPerfCountersAndMemoryPools
  */
 public class TestPerfCountersAndMemoryPools {
     public static void main(String[] args) throws Exception {
         checkMemoryUsage("Metaspace", "sun.gc.metaspace");
 
-        if (InputArguments.contains("-XX:+UseCompressedKlassPointers") && Platform.is64bit()) {
+        if (InputArguments.contains("-XX:+UseCompressedClassPointers") && Platform.is64bit()) {
             checkMemoryUsage("Compressed Class Space", "sun.gc.compressedclassspace");
         }
     }
--- cut here ---




From aph at redhat.com  Fri Oct 11 09:31:07 2013
From: aph at redhat.com (Andrew Haley)
Date: Fri, 11 Oct 2013 17:31:07 +0100
Subject: [aarch64-port-dev ] Merge up to jdk8-b110
In-Reply-To: <1381496369.18100.34.camel@localhost.localdomain>
References: <1381496369.18100.34.camel@localhost.localdomain>
Message-ID: <525827CB.9080804@redhat.com>


On 10/11/2013 01:59 PM, Edward Nevill wrote: There is a known problem
> with UseCompressedKlassPointers (or UseCompressedClassPointers as
> they are now known). These were broken somewhere between b104 and
> b105. I need to go back and see why they are broken, however, I
> would like to get this mega merge off my desk before I go back and
> look at this.

Sure, that's the right thing to do.  OK.

Andrew.


From ed at camswl.com  Fri Oct 11 10:55:30 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 11 Oct 2013 17:55:30 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8: 103 new changesets
Message-ID: <20131011175542.E418262F8E@hg.openjdk.java.net>

Changeset: 83b519cafa68
Author:    katleman
Date:      2013-05-16 12:13 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/83b519cafa68

Added tag jdk8-b90 for changeset 69b773a221b9

! .hgtags

Changeset: e2eb6bc06621
Author:    mduigou
Date:      2013-05-08 21:42 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/e2eb6bc06621

8014269: Add missing .PHONY targets to Main.gmk
Reviewed-by: mchung, tbell

! common/makefiles/Main.gmk

Changeset: 49ea9293fa49
Author:    lana
Date:      2013-05-09 14:23 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/49ea9293fa49

Merge


Changeset: 40bba0507f76
Author:    lana
Date:      2013-05-17 10:06 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/40bba0507f76

Merge


Changeset: eea249c1ecee
Author:    erikj
Date:      2013-05-21 13:18 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/eea249c1ecee

8014508: Fix log levels in make
Reviewed-by: tbell

! NewMakefile.gmk
! common/autoconf/spec.gmk.in

Changeset: e83abb0a04ab
Author:    katleman
Date:      2013-05-21 12:51 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/e83abb0a04ab

Merge


Changeset: cb51fb4789ac
Author:    andrew
Date:      2013-05-22 13:49 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/cb51fb4789ac

8015087: Provide debugging information for programs
Summary: Enable debugging info on programs in OpenJDK builds
Reviewed-by: erikj

! common/makefiles/NativeCompilation.gmk

Changeset: f089df41bff5
Author:    katleman
Date:      2013-05-23 10:47 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/f089df41bff5

Added tag jdk8-b91 for changeset cb51fb4789ac

! .hgtags

Changeset: e247ee3924d5
Author:    erikj
Date:      2013-05-22 17:26 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/e247ee3924d5

8014514: Fix jvm args for sjavac
Reviewed-by: tbell

! common/autoconf/basics.m4
! common/autoconf/build-performance.m4
! common/autoconf/generated-configure.sh

Changeset: e7c09a983c3c
Author:    erikj
Date:      2013-05-28 08:50 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/e7c09a983c3c

8007129: build-infra Add configure --with-jtreg option for location of JTREG
Reviewed-by: tbell

! common/autoconf/basics.m4
! common/autoconf/generated-configure.sh
! common/autoconf/spec.gmk.in
! common/autoconf/toolchain.m4

Changeset: 3a36c926a7aa
Author:    katleman
Date:      2013-05-28 17:57 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/3a36c926a7aa

Merge


Changeset: 46be9eb242d1
Author:    katleman
Date:      2013-05-30 10:57 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/46be9eb242d1

Added tag jdk8-b92 for changeset 3a36c926a7aa

! .hgtags

Changeset: 78852ce176db
Author:    jqzuo
Date:      2013-05-28 20:03 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/78852ce176db

8014762: Add JMC configure option mapping to Jprt.gmk
Summary: Need to add the mapping between JPRT env var and configure flag for JMC, from ALT_JMC_ZIP_DIR to --with-jmc-zip-dir (same pattern as for Javafx)
Reviewed-by: tbell, erikj
Contributed-by: klara.ward at oracle.com

! common/autoconf/generated-configure.sh
! common/makefiles/Jprt.gmk

Changeset: c22d59e3f06e
Author:    pbhat
Date:      2013-05-29 11:02 -0400
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/c22d59e3f06e

Merge


Changeset: ea6f3bf82903
Author:    jqzuo
Date:      2013-06-04 00:12 -0400
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/ea6f3bf82903

Merge

! common/autoconf/generated-configure.sh

Changeset: 33b6df33a2b7
Author:    erikj
Date:      2013-05-29 13:58 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/33b6df33a2b7

8013920: Configure sets JOBS to 0 if memory is too low.
Reviewed-by: tbell

! common/autoconf/build-performance.m4
! common/autoconf/generated-configure.sh

Changeset: 03e60e87d92a
Author:    erikj
Date:      2013-05-29 14:01 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/03e60e87d92a

8013489: New build system does not run codesign on SA-related launchers on OS X
Reviewed-by: sla, tbell

! common/autoconf/basics.m4
! common/autoconf/generated-configure.sh
! common/autoconf/spec.gmk.in
! common/makefiles/MakeBase.gmk
! common/makefiles/NativeCompilation.gmk

Changeset: c31e9dc1fe3d
Author:    erikj
Date:      2013-05-31 14:07 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/c31e9dc1fe3d

8014003: New build does not handle symlinks in workspace path
Reviewed-by: tbell

! common/autoconf/basics.m4
! common/autoconf/basics_windows.m4
! common/autoconf/generated-configure.sh

Changeset: 44259699e0b5
Author:    erikj
Date:      2013-06-04 10:23 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/44259699e0b5

8015784: Add configure parameter --with-update-version
Reviewed-by: tbell, katleman, erikj
Contributed-by: tristan.yan at oracle.com

! common/autoconf/generated-configure.sh
! common/autoconf/jdk-options.m4

Changeset: db3144e1f89b
Author:    mduigou
Date:      2013-06-04 10:36 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/db3144e1f89b

8015510: (s) Improve JTReg location detection and provide location to test/Makefile
Reviewed-by: erikj

! common/autoconf/generated-configure.sh
! common/autoconf/toolchain.m4
! common/makefiles/Main.gmk

Changeset: 9b8e8098172c
Author:    katleman
Date:      2013-06-04 11:02 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/9b8e8098172c

Merge


Changeset: f55734874c4f
Author:    katleman
Date:      2013-06-04 15:54 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/f55734874c4f

Merge

! common/autoconf/generated-configure.sh

Changeset: 27c51c6e31c1
Author:    katleman
Date:      2013-06-05 15:20 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/27c51c6e31c1

6983966: remove lzma and upx from repository JDK8
Reviewed-by: tbell, paulk, ngthomas

! common/autoconf/generated-configure.sh
! common/makefiles/Jprt.gmk
! make/deploy-rules.gmk

Changeset: 8dfb6ee04114
Author:    katleman
Date:      2013-06-06 09:54 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/8dfb6ee04114

Added tag jdk8-b93 for changeset 27c51c6e31c1

! .hgtags

Changeset: 198d25db45da
Author:    erikj
Date:      2013-06-11 13:08 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/198d25db45da

8008707: build-infra: Closed (deploy) can't be built using environment from SDK SetEnv.cmd
Reviewed-by: tbell

! common/autoconf/generated-configure.sh
! common/autoconf/toolchain_windows.m4

Changeset: 3cbcc2b6ba41
Author:    erikj
Date:      2013-06-11 13:25 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/3cbcc2b6ba41

8010785: JDK 8 build on Linux fails with new build mechanism
Reviewed-by: dholmes, tbell

! common/autoconf/generated-configure.sh
! common/autoconf/jdk-options.m4

Changeset: 50d2bde060f2
Author:    erikj
Date:      2013-06-12 10:33 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/50d2bde060f2

Merge


Changeset: 6337f652e71f
Author:    katleman
Date:      2013-06-13 09:48 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/6337f652e71f

Added tag jdk8-b94 for changeset 50d2bde060f2

! .hgtags

Changeset: c961c8972485
Author:    erikj
Date:      2013-06-13 14:04 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/c961c8972485

8014231: --with-alsa configuration options don't add include or lib directories to proper flags
Reviewed-by: tbell

! common/autoconf/spec.gmk.in

Changeset: 0c540b1505e3
Author:    erikj
Date:      2013-06-14 13:30 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/0c540b1505e3

8016520: jdk native build does not fail on compilation error on windows
Reviewed-by: tbell

! common/makefiles/NativeCompilation.gmk

Changeset: 0d1e8518c722
Author:    erikj
Date:      2013-06-18 11:29 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/0d1e8518c722

8014404: Debug flag not added to jdk native compile when --enable-debug is set
Reviewed-by: tbell

! common/autoconf/generated-configure.sh
! common/autoconf/toolchain.m4

Changeset: c0fa87863427
Author:    erikj
Date:      2013-06-18 11:30 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/c0fa87863427

8015377: Support using compiler devkits on Linux
Reviewed-by: tbell, dholmes

! common/autoconf/basics.m4
! common/autoconf/build-performance.m4
! common/autoconf/generated-configure.sh
! common/autoconf/libraries.m4
+ common/makefiles/devkit/Makefile
+ common/makefiles/devkit/Tools.gmk

Changeset: 785d07fe3890
Author:    katleman
Date:      2013-06-18 15:32 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/785d07fe3890

Merge


Changeset: 794cceb5dc82
Author:    katleman
Date:      2013-06-20 10:16 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/794cceb5dc82

Added tag jdk8-b95 for changeset 785d07fe3890

! .hgtags

Changeset: f8770fe60d53
Author:    mduigou
Date:      2013-06-17 09:41 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/f8770fe60d53

8016572: Pass CONCURRENCY=$(JOBS) to test/Makefile
Reviewed-by: alanb, erikj

! common/makefiles/Main.gmk

Changeset: b9587f41fd55
Author:    smarks
Date:      2013-06-18 17:18 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/b9587f41fd55

8016780: README-builds.html misses crucial requirement on bootstrap JDK
Reviewed-by: dholmes, chegar

! README-builds.html

Changeset: d72e765a9fbe
Author:    lana
Date:      2013-06-19 17:59 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/d72e765a9fbe

Merge


Changeset: f1010ef2f451
Author:    lana
Date:      2013-06-24 14:26 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/f1010ef2f451

Merge


Changeset: ebcd79fc658d
Author:    erikj
Date:      2013-06-25 09:37 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/ebcd79fc658d

8012564: The SOURCE value in release file of JDK 8 doesn't contain valid changesets for some OS since b74
Reviewed-by: alanb, tbell

! common/makefiles/Main.gmk

Changeset: c156084add48
Author:    katleman
Date:      2013-06-25 13:47 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/c156084add48

Merge

! common/makefiles/Main.gmk

Changeset: 4c363b94ea2a
Author:    katleman
Date:      2013-06-27 13:40 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/4c363b94ea2a

Added tag jdk8-b96 for changeset c156084add48

! .hgtags

Changeset: f5eb23490e6a
Author:    erikj
Date:      2013-06-27 09:27 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/f5eb23490e6a

8017047: Can't use --with-java-devtools and --with-devkit at the same time
Reviewed-by: tbell

! common/autoconf/basics.m4
! common/autoconf/generated-configure.sh
! common/autoconf/toolchain.m4

Changeset: e5cf1735638c
Author:    erikj
Date:      2013-06-28 11:55 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/e5cf1735638c

8016605: New files dont apear in src.zip
Reviewed-by: tbell

! common/makefiles/JavaCompilation.gmk

Changeset: 0871b5799149
Author:    erikj
Date:      2013-06-28 11:58 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/0871b5799149

8019229: Build Configuration Fail in Windows Platform
Reviewed-by: chegar, tbell, dxu

! common/autoconf/generated-configure.sh
! common/autoconf/toolchain.m4

Changeset: 0e533ceee717
Author:    erikj
Date:      2013-06-28 12:00 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/0e533ceee717

8016303: make CONF= isn't working
Reviewed-by: tbell

! NewMakefile.gmk

Changeset: 78aaf5d3314d
Author:    erikj
Date:      2013-06-28 12:02 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/78aaf5d3314d

8010385: build with LOG=trace broken on mac
Reviewed-by: dholmes, tbell, prr

! common/autoconf/basics.m4
! common/autoconf/generated-configure.sh
! common/autoconf/spec.gmk.in
! common/makefiles/MakeBase.gmk

Changeset: dd3b314f4471
Author:    erikj
Date:      2013-07-01 15:40 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/dd3b314f4471

8009744: build-infra: REGRESSION: Publisher was NOT set for some JDK files
Reviewed-by: tbell

! common/autoconf/generated-configure.sh
! common/autoconf/toolchain.m4

Changeset: b2b87e9e8683
Author:    erikj
Date:      2013-07-02 15:07 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/b2b87e9e8683

8019537: jdk8-build prebuild fails in source bundle generation, The path of TOOLS_DIR ... is not found
Reviewed-by: tbell

! common/autoconf/basics.m4
! common/autoconf/generated-configure.sh

Changeset: a1c1e8bf71f3
Author:    katleman
Date:      2013-07-02 15:55 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/a1c1e8bf71f3

Merge


Changeset: 99ad803f8c4e
Author:    cl
Date:      2013-07-04 01:00 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/99ad803f8c4e

Added tag jdk8-b97 for changeset a1c1e8bf71f3

! .hgtags

Changeset: 0d0c983a817b
Author:    tbell
Date:      2013-07-09 08:35 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/0d0c983a817b

8009315: F# on PATH breaks Cygwin tools (mkdir, echo, mktemp ...)
Reviewed-by: erikj

! common/autoconf/generated-configure.sh
! common/autoconf/toolchain_windows.m4

Changeset: 59dc9da81379
Author:    katleman
Date:      2013-07-11 10:13 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/59dc9da81379

Added tag jdk8-b98 for changeset 0d0c983a817b

! .hgtags

Changeset: d2dcb110e9db
Author:    cl
Date:      2013-07-18 03:37 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/d2dcb110e9db

Added tag jdk8-b99 for changeset 59dc9da81379

! .hgtags

Changeset: 9f74a220677d
Author:    cl
Date:      2013-07-25 03:18 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/9f74a220677d

Added tag jdk8-b100 for changeset d2dcb110e9db

! .hgtags

Changeset: 5eb3c1dc348f
Author:    cl
Date:      2013-08-01 04:56 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/5eb3c1dc348f

Added tag jdk8-b101 for changeset 9f74a220677d

! .hgtags

Changeset: b7e64be81c8a
Author:    cl
Date:      2013-08-08 10:10 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/b7e64be81c8a

Added tag jdk8-b102 for changeset 5eb3c1dc348f

! .hgtags

Changeset: ceefd94ef326
Author:    cl
Date:      2013-08-15 09:25 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/ceefd94ef326

Added tag jdk8-b103 for changeset b7e64be81c8a

! .hgtags

Changeset: 4fb877dfe5c4
Author:    erikj
Date:      2013-08-15 17:14 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/4fb877dfe5c4

8020411: lin32 - JDK 8 build for Linux-i586 on Oracle Linux 6.4 64-bit machines does not generate the bundles directory in the build directory
Reviewed-by: tbell

! common/autoconf/generated-configure.sh
! common/autoconf/platform.m4
! common/autoconf/spec.gmk.in

Changeset: f10f673d9b17
Author:    igerasim
Date:      2013-08-16 14:43 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/f10f673d9b17

8023156: make dist-clean should remove javacservers directory
Reviewed-by: erikj

! common/makefiles/Main.gmk

Changeset: dadf49495ab4
Author:    erikj
Date:      2013-08-19 10:31 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/dadf49495ab4

8021430: 64 bit JDK build fails on windows 7 due to missing corba source files
Reviewed-by: tbell, katleman

! common/makefiles/IdlCompilation.gmk

Changeset: 96c1b9b7524b
Author:    katleman
Date:      2013-08-20 15:42 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/96c1b9b7524b

Merge


Changeset: c3b5197f2851
Author:    cl
Date:      2013-08-22 09:09 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/c3b5197f2851

Added tag jdk8-b104 for changeset 96c1b9b7524b

! .hgtags

Changeset: 00dcfaa6bc01
Author:    aefimov
Date:      2013-08-16 18:40 +0400
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/00dcfaa6bc01

8021820: Number of opened files used in select() is limited to 1024 [macosx]
Reviewed-by: alanb, chegar, tbell, smarks

! common/autoconf/generated-configure.sh
! common/autoconf/toolchain.m4

Changeset: e8a3edda1f60
Author:    lana
Date:      2013-08-20 17:40 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/e8a3edda1f60

Merge


Changeset: 056398db9dcb
Author:    lana
Date:      2013-08-23 14:09 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/056398db9dcb

Merge

! common/autoconf/generated-configure.sh

Changeset: f8405a0fa69c
Author:    erikj
Date:      2013-08-26 13:43 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/f8405a0fa69c

8023216: Feedback on README-builds.html
Reviewed-by: anthony, robilad, tbell

! README-builds.html

Changeset: 5166118c5917
Author:    katleman
Date:      2013-08-26 17:34 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/5166118c5917

Merge


Changeset: 246cdbaa6c62
Author:    cl
Date:      2013-08-29 09:41 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/246cdbaa6c62

Added tag jdk8-b105 for changeset 5166118c5917

! .hgtags

Changeset: c8da1b6a9762
Author:    mduigou
Date:      2013-08-20 17:44 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/c8da1b6a9762

8023433: Improve 'make help'
Reviewed-by: tbell

! NewMakefile.gmk

Changeset: f643fee2b40f
Author:    mduigou
Date:      2013-08-26 10:09 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/f643fee2b40f

8023491: Remove target names from test/Makefile and defer to sub-repo makefiles.
Reviewed-by: erikj

! common/makefiles/Main.gmk
! test/Makefile

Changeset: 163091288aeb
Author:    lana
Date:      2013-08-26 14:49 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/163091288aeb

Merge

! common/makefiles/Main.gmk

Changeset: 51a61778a99d
Author:    mduigou
Date:      2013-08-29 16:04 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/51a61778a99d

8023892: test/Makefile shouldn't try to tell langtools/test/Makefile where to put output.
Reviewed-by: erikj, vromero, henryjen

! test/Makefile

Changeset: 4ac867c44467
Author:    lana
Date:      2013-08-29 16:18 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/4ac867c44467

Merge


Changeset: 21198f51bc7e
Author:    erikj
Date:      2013-08-29 15:47 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/21198f51bc7e

8003162: build-infra: Improve suggestions for missing packages on linux
Reviewed-by: tbell, omajid

! common/autoconf/generated-configure.sh
! common/autoconf/help.m4
! common/autoconf/libraries.m4

Changeset: 92facce22941
Author:    erikj
Date:      2013-08-30 10:13 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/92facce22941

8023957: Lock down version of autoconf
Reviewed-by: chegar, dsamersoff, tbell, dholmes

! README-builds.html
! common/autoconf/autogen.sh
! common/autoconf/configure.ac
! common/autoconf/generated-configure.sh

Changeset: 2aacc7080d36
Author:    katleman
Date:      2013-09-03 13:48 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/2aacc7080d36

Merge


Changeset: 0f6dde6231bd
Author:    ihse
Date:      2013-09-04 10:15 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/0f6dde6231bd

8024155: Fix 'make CONF= <target>'
Reviewed-by: erikj, tbell

! NewMakefile.gmk
! common/makefiles/Main.gmk

Changeset: 8e7b4d9fb00f
Author:    erikj
Date:      2013-09-04 10:37 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/8e7b4d9fb00f

Merge

! NewMakefile.gmk
! common/makefiles/Main.gmk

Changeset: 58f1b6f32b47
Author:    cl
Date:      2013-09-05 02:45 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/58f1b6f32b47

Added tag jdk8-b106 for changeset 8e7b4d9fb00f

! .hgtags

Changeset: 0874bb4707b7
Author:    omajid
Date:      2013-09-11 12:08 -0400
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/0874bb4707b7

8024320: Add s390(x) detection to platform.m4
Reviewed-by: erikj, ihse, dsamersoff

! common/autoconf/generated-configure.sh
! common/autoconf/platform.m4

Changeset: 14fe208b657c
Author:    cl
Date:      2013-09-12 11:08 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/14fe208b657c

Added tag jdk8-b107 for changeset 0874bb4707b7

! .hgtags

Changeset: 6d7f27953da6
Author:    mduigou
Date:      2013-09-03 15:23 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/6d7f27953da6

8024200: handle hg wrapper with space after #!
Reviewed-by: tbell

! common/bin/hgforest.sh

Changeset: 73355c4c1bc8
Author:    lana
Date:      2013-09-06 14:15 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/73355c4c1bc8

Merge


Changeset: 67f64101616e
Author:    mduigou
Date:      2013-09-13 12:06 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/67f64101616e

8024201: Update bugdatabase url
Reviewed-by: wetmore

! make/scripts/webrev.ksh

Changeset: 4bf059350c51
Author:    lana
Date:      2013-09-17 08:08 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/4bf059350c51

Merge


Changeset: 8dadd26c2a58
Author:    ihse
Date:      2013-09-12 10:38 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/8dadd26c2a58

8024467: Update autoconf-config.guess to autoconf 2.69
Reviewed-by: erikj

! common/autoconf/build-aux/autoconf-config.guess

Changeset: 64f52ef175a4
Author:    ihse
Date:      2013-09-12 10:42 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/64f52ef175a4

8010185: Build should support --with-override-nashorn
Reviewed-by: erikj

! common/autoconf/generated-configure.sh
! common/autoconf/source-dirs.m4

Changeset: b1e9396fb8af
Author:    vadim
Date:      2013-09-12 12:12 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/b1e9396fb8af

8008022: Upgrade Direct X SDK used to build JDK
Reviewed-by: erikj, prr, ihse

! Makefile
! README-builds.html
! common/autoconf/generated-configure.sh
! common/autoconf/spec.gmk.in
! common/autoconf/toolchain.m4
! common/autoconf/toolchain_windows.m4

Changeset: 69da99676239
Author:    ihse
Date:      2013-09-13 13:07 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/69da99676239

8024620: config.log does not end up in corresponding configuration
Reviewed-by: erikj

! common/autoconf/configure
! common/autoconf/configure.ac
! common/autoconf/generated-configure.sh

Changeset: ac3f5137f84d
Author:    ihse
Date:      2013-09-13 14:59 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/ac3f5137f84d

8024665: Move open changes for JDK-8020411 to closed source
Reviewed-by: erikj

! common/autoconf/generated-configure.sh
! common/autoconf/platform.m4
! common/autoconf/spec.gmk.in

Changeset: aab351790498
Author:    katleman
Date:      2013-09-17 13:41 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/aab351790498

Merge


Changeset: 59d6af7422af
Author:    katleman
Date:      2013-09-17 19:06 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/59d6af7422af

Merge


Changeset: 7697621037fd
Author:    ihse
Date:      2013-09-18 12:37 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/7697621037fd

8024815: Make --with-dxsdk and friends deprecated
Reviewed-by: erikj

! common/autoconf/basics.m4
! common/autoconf/generated-configure.sh
! common/autoconf/toolchain.m4

Changeset: 9286a6e61291
Author:    ihse
Date:      2013-09-18 13:49 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/9286a6e61291

8024849: Don't remove upper case letters from username when setting USER_RELEASE_SUFFIX
Reviewed-by: erikj

! common/autoconf/basics_windows.m4
! common/autoconf/generated-configure.sh
! common/autoconf/jdk-options.m4

Changeset: d4762f463fe0
Author:    cl
Date:      2013-09-19 09:36 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/d4762f463fe0

Added tag jdk8-b108 for changeset 9286a6e61291

! .hgtags

Changeset: 91f47e8da5c6
Author:    tbell
Date:      2013-09-25 12:21 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/91f47e8da5c6

8025411: JPRT to switch to the new Win platforms for JDK8 builds this week
Reviewed-by: ksrini, katleman

! make/jprt.properties

Changeset: 0cc21882d2f6
Author:    cl
Date:      2013-09-26 10:43 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/0cc21882d2f6

Added tag jdk8-b109 for changeset 91f47e8da5c6

! .hgtags

Changeset: 5ec3c4948863
Author:    ksrini
Date:      2013-09-27 16:27 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/5ec3c4948863

8023495: [infra] create 64-bit solaris bits with symlinks
Reviewed-by: ihse, tbell, erikj

! common/makefiles/Jprt.gmk
! common/makefiles/Main.gmk

Changeset: 72c2495c86c9
Author:    katleman
Date:      2013-10-01 12:43 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/72c2495c86c9

Merge


Changeset: 0f704e36bc5d
Author:    ihse
Date:      2013-10-01 10:58 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/0f704e36bc5d

8006661: Use LC_ALL=C instead of LANG=C compare.sh
Reviewed-by: tbell

! common/bin/compare.sh

Changeset: 4faa09c7fe55
Author:    erikj
Date:      2013-10-02 15:08 +0200
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/4faa09c7fe55

Merge


Changeset: eea63b68cd04
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-11 12:03 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/eea63b68cd04

Merg up to jdk8-b110

! .hgtags
! common/autoconf/build-aux/autoconf-config.guess
! common/autoconf/generated-configure.sh
! common/autoconf/jdk-options.m4
! common/autoconf/libraries.m4
! common/autoconf/platform.m4
! common/autoconf/source-dirs.m4
! common/autoconf/spec.gmk.in
! common/autoconf/toolchain.m4
! common/bin/hgforest.sh
! common/makefiles/NativeCompilation.gmk

Changeset: fb54b96dadd9
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-11 12:34 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/fb54b96dadd9

aarch64 specific changes for merge to jdk8-b110

! common/autoconf/build-aux/autoconf-config.guess
! common/autoconf/generated-configure.sh



From ed at camswl.com  Fri Oct 11 10:57:02 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 11 Oct 2013 17:57:02 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/corba: 41 new changesets
Message-ID: <20131011175732.299ED62F8F@hg.openjdk.java.net>

Changeset: 8f7ffb296385
Author:    katleman
Date:      2013-05-16 12:14 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/8f7ffb296385

Added tag jdk8-b90 for changeset c8286839d0df

! .hgtags

Changeset: 717aa26f8e0a
Author:    katleman
Date:      2013-05-23 10:47 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/717aa26f8e0a

Added tag jdk8-b91 for changeset 8f7ffb296385

! .hgtags

Changeset: 8dc9d7ccbb2d
Author:    katleman
Date:      2013-05-30 10:57 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/8dc9d7ccbb2d

Added tag jdk8-b92 for changeset 717aa26f8e0a

! .hgtags

Changeset: 22f5d7f261d9
Author:    katleman
Date:      2013-06-06 09:54 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/22f5d7f261d9

Added tag jdk8-b93 for changeset 8dc9d7ccbb2d

! .hgtags

Changeset: 2cf36f43df36
Author:    katleman
Date:      2013-06-13 09:48 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/2cf36f43df36

Added tag jdk8-b94 for changeset 22f5d7f261d9

! .hgtags

Changeset: c68c35f50413
Author:    katleman
Date:      2013-06-20 10:16 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/c68c35f50413

Added tag jdk8-b95 for changeset 2cf36f43df36

! .hgtags

Changeset: 5845df371e25
Author:    alanb
Date:      2013-06-10 17:15 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/5845df371e25

8016218: Warnings building corba repo due to missing hashCode methods
Reviewed-by: chegar, coffeys, dfuchs

! src/share/classes/com/sun/corba/se/impl/javax/rmi/CORBA/StubDelegateImpl.java
! src/share/classes/com/sun/corba/se/impl/orb/ParserTable.java
! src/share/classes/com/sun/corba/se/impl/orbutil/RepIdDelegator.java
! src/share/classes/sun/rmi/rmic/iiop/CompoundType.java

Changeset: 0fac0a9d9545
Author:    lana
Date:      2013-06-16 22:30 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/0fac0a9d9545

Merge


Changeset: 39d15bbb5741
Author:    coffeys
Date:      2013-04-08 23:12 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/39d15bbb5741

8001032: Restrict object access
Summary: Restrict object access; fix reviewed also by Alexander Fomin
Reviewed-by: alanb, ahgross

! make/com/sun/corba/minclude/com_sun_corba_se_impl_orbutil.jmk
! src/share/classes/com/sun/corba/se/impl/activation/ServerManagerImpl.java
! src/share/classes/com/sun/corba/se/impl/interceptors/PIHandlerImpl.java
! src/share/classes/com/sun/corba/se/impl/interceptors/RequestInfoImpl.java
! src/share/classes/com/sun/corba/se/impl/io/ValueUtility.java
! src/share/classes/com/sun/corba/se/impl/javax/rmi/CORBA/Util.java
! src/share/classes/com/sun/corba/se/impl/orb/ORBDataParserImpl.java
! src/share/classes/com/sun/corba/se/impl/orb/ORBImpl.java
! src/share/classes/com/sun/corba/se/impl/orb/ParserTable.java
- src/share/classes/com/sun/corba/se/impl/orbutil/ORBClassLoader.java
! src/share/classes/com/sun/corba/se/impl/orbutil/ORBUtility.java
! src/share/classes/com/sun/corba/se/impl/protocol/giopmsgheaders/LocateReplyMessage_1_2.java
! src/share/classes/com/sun/corba/se/impl/protocol/giopmsgheaders/MessageBase.java
! src/share/classes/com/sun/corba/se/impl/protocol/giopmsgheaders/ReplyMessage_1_0.java
! src/share/classes/com/sun/corba/se/impl/protocol/giopmsgheaders/ReplyMessage_1_1.java
! src/share/classes/com/sun/corba/se/spi/orb/ORB.java
! src/share/classes/com/sun/corba/se/spi/orb/OperationFactory.java
! src/share/classes/sun/corba/JavaCorbaAccess.java

Changeset: 978818df41b9
Author:    chegar
Date:      2013-04-24 10:17 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/978818df41b9

Merge


Changeset: 68d407e4d204
Author:    chegar
Date:      2013-04-28 08:15 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/68d407e4d204

Merge


Changeset: 80161c61aa68
Author:    coffeys
Date:      2013-04-30 11:53 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/80161c61aa68

8000642: Better handling of objects for transportation
Reviewed-by: alanb, mchung, skoivu

! src/share/classes/com/sun/corba/se/impl/corba/AnyImpl.java
! src/share/classes/com/sun/corba/se/impl/corba/TypeCodeImpl.java
! src/share/classes/com/sun/corba/se/impl/encoding/IDLJavaSerializationOutputStream.java
! src/share/classes/com/sun/corba/se/impl/encoding/TypeCodeOutputStream.java
! src/share/classes/com/sun/corba/se/impl/interceptors/CDREncapsCodec.java
! src/share/classes/com/sun/corba/se/impl/interceptors/RequestInfoImpl.java
! src/share/classes/com/sun/corba/se/impl/io/IIOPInputStream.java
! src/share/classes/com/sun/corba/se/impl/io/IIOPOutputStream.java
! src/share/classes/com/sun/corba/se/impl/io/InputStreamHook.java
! src/share/classes/com/sun/corba/se/impl/io/OutputStreamHook.java
! src/share/classes/com/sun/corba/se/impl/ior/EncapsulationUtility.java
! src/share/classes/com/sun/corba/se/impl/ior/GenericTaggedProfile.java
! src/share/classes/com/sun/corba/se/impl/ior/IORImpl.java
! src/share/classes/com/sun/corba/se/impl/ior/ObjectKeyImpl.java
! src/share/classes/com/sun/corba/se/impl/ior/TaggedComponentFactoryFinderImpl.java
! src/share/classes/com/sun/corba/se/impl/ior/iiop/IIOPProfileImpl.java
! src/share/classes/com/sun/corba/se/impl/ior/iiop/IIOPProfileTemplateImpl.java
! src/share/classes/com/sun/corba/se/impl/orb/ORBImpl.java
! src/share/classes/com/sun/corba/se/impl/orb/ORBSingleton.java
! src/share/classes/com/sun/corba/se/impl/protocol/CorbaMessageMediatorImpl.java
! src/share/classes/com/sun/corba/se/impl/transport/CorbaContactInfoBase.java
! src/share/classes/com/sun/corba/se/impl/transport/SharedCDRContactInfoImpl.java
! src/share/classes/com/sun/corba/se/impl/transport/SocketOrChannelAcceptorImpl.java
! src/share/classes/com/sun/corba/se/impl/transport/SocketOrChannelConnectionImpl.java
! src/share/classes/com/sun/corba/se/spi/ior/TaggedComponentBase.java
! src/share/classes/com/sun/corba/se/spi/servicecontext/ServiceContext.java
! src/share/classes/org/omg/CORBA_2_3/portable/OutputStream.java
+ src/share/classes/sun/corba/OutputStreamFactory.java

Changeset: 4fe1edbec7bc
Author:    chegar
Date:      2013-05-08 10:09 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/4fe1edbec7bc

Merge


Changeset: e9c924d3475c
Author:    chegar
Date:      2013-05-16 11:39 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/e9c924d3475c

Merge


Changeset: 216cb38dce0a
Author:    chegar
Date:      2013-05-23 12:41 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/216cb38dce0a

Merge


Changeset: 25e68d232c20
Author:    chegar
Date:      2013-05-31 10:26 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/25e68d232c20

Merge


Changeset: c1f80e733eb0
Author:    chegar
Date:      2013-06-17 11:11 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/c1f80e733eb0

Merge

! src/share/classes/com/sun/corba/se/impl/orb/ParserTable.java

Changeset: d406edd4f6fd
Author:    mfang
Date:      2013-06-18 20:52 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/d406edd4f6fd

8015657: jdk8 l10n resource file translation update 3
Reviewed-by: yhuang

! src/share/classes/com/sun/corba/se/impl/orbutil/resources/sunorb_ko.properties
! src/share/classes/com/sun/tools/corba/se/idl/idl_zh_CN.prp
! src/share/classes/com/sun/tools/corba/se/idl/toJavaPortable/toJavaPortable_ja.prp

Changeset: 3357c2776431
Author:    lana
Date:      2013-06-24 14:26 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/3357c2776431

Merge


Changeset: 469995a8e974
Author:    katleman
Date:      2013-06-27 13:40 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/469995a8e974

Added tag jdk8-b96 for changeset 3357c2776431

! .hgtags

Changeset: 3370fb6146e4
Author:    cl
Date:      2013-07-04 01:00 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/3370fb6146e4

Added tag jdk8-b97 for changeset 469995a8e974

! .hgtags

Changeset: 3f67804ab613
Author:    katleman
Date:      2013-07-11 10:13 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/3f67804ab613

Added tag jdk8-b98 for changeset 3370fb6146e4

! .hgtags

Changeset: 8d492f1dfd1b
Author:    cl
Date:      2013-07-18 03:37 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/8d492f1dfd1b

Added tag jdk8-b99 for changeset 3f67804ab613

! .hgtags

Changeset: a013024b0747
Author:    cl
Date:      2013-07-25 03:18 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/a013024b0747

Added tag jdk8-b100 for changeset 8d492f1dfd1b

! .hgtags

Changeset: 528c7e76eaee
Author:    cl
Date:      2013-08-01 04:56 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/528c7e76eaee

Added tag jdk8-b101 for changeset a013024b0747

! .hgtags

Changeset: f8ed09af1df6
Author:    cl
Date:      2013-08-08 10:10 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/f8ed09af1df6

Added tag jdk8-b102 for changeset 528c7e76eaee

! .hgtags

Changeset: cc11a0efb4f9
Author:    aefimov
Date:      2013-08-01 14:59 +0400
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/cc11a0efb4f9

8015987: The corba repo contains unneeded .sjava files
Reviewed-by: alanb, chegar, coffeys

- src/share/classes/com/sun/corba/se/impl/copyobject/JavaInputStream.sjava
- src/share/classes/com/sun/corba/se/impl/copyobject/JavaOutputStream.sjava
- src/share/classes/com/sun/corba/se/impl/interceptors/ThreadCurrentStack.sjava
- src/share/classes/com/sun/corba/se/impl/orbutil/DefineWrapper.sjava
- src/share/classes/com/sun/corba/se/impl/presentation/rmi/IDLNameTranslatorImpl_save.sjava
- src/share/classes/com/sun/corba/se/impl/presentation/rmi/IDLTypesUtil_save.sjava
- src/share/classes/com/sun/corba/se/impl/protocol/oldlocal/LocalClientRequestImpl.sjava
- src/share/classes/com/sun/corba/se/impl/protocol/oldlocal/LocalClientResponseImpl.sjava
- src/share/classes/com/sun/corba/se/impl/protocol/oldlocal/LocalServerRequestImpl.sjava
- src/share/classes/com/sun/corba/se/impl/protocol/oldlocal/LocalServerResponseImpl.sjava
- src/share/classes/com/sun/corba/se/impl/transport/BufferConnectionImpl.sjava

Changeset: 342a954b68f3
Author:    lana
Date:      2013-08-06 16:54 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/342a954b68f3

Merge


Changeset: 49c4a777fdfd
Author:    lana
Date:      2013-08-13 10:34 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/49c4a777fdfd

Merge


Changeset: d411c60a8c2f
Author:    cl
Date:      2013-08-15 09:25 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/d411c60a8c2f

Added tag jdk8-b103 for changeset 49c4a777fdfd

! .hgtags

Changeset: 4e38de7c767e
Author:    cl
Date:      2013-08-22 09:09 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/4e38de7c767e

Added tag jdk8-b104 for changeset d411c60a8c2f

! .hgtags

Changeset: 2e3a056c84a7
Author:    cl
Date:      2013-08-29 09:41 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/2e3a056c84a7

Added tag jdk8-b105 for changeset 4e38de7c767e

! .hgtags

Changeset: 23fc34133152
Author:    cl
Date:      2013-09-05 02:45 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/23fc34133152

Added tag jdk8-b106 for changeset 2e3a056c84a7

! .hgtags

Changeset: 260f00a95705
Author:    cl
Date:      2013-09-12 11:08 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/260f00a95705

Added tag jdk8-b107 for changeset 23fc34133152

! .hgtags

Changeset: af8e5bc3a150
Author:    coffeys
Date:      2013-09-03 22:35 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/af8e5bc3a150

8017195: Introduce option to setKeepAlive parameter on CORBA sockets
Reviewed-by: chegar, msheppar

! src/share/classes/com/sun/corba/se/impl/transport/DefaultSocketFactoryImpl.java

Changeset: 4853dc082c7d
Author:    lana
Date:      2013-09-06 14:15 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/4853dc082c7d

Merge


Changeset: a4bb3b450016
Author:    lana
Date:      2013-09-17 08:08 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/a4bb3b450016

Merge


Changeset: c1eb93f57603
Author:    cl
Date:      2013-09-19 09:36 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/c1eb93f57603

Added tag jdk8-b108 for changeset a4bb3b450016

! .hgtags

Changeset: 428428cf5e06
Author:    tbell
Date:      2013-09-25 12:22 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/428428cf5e06

8025411: JPRT to switch to the new Win platforms for JDK8 builds this week
Reviewed-by: ksrini, katleman

! make/jprt.properties

Changeset: 3d2b7ce93c5c
Author:    cl
Date:      2013-09-26 10:43 -0700
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/3d2b7ce93c5c

Added tag jdk8-b109 for changeset 428428cf5e06

! .hgtags

Changeset: 4540fc0b8d8d
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-11 12:05 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/4540fc0b8d8d

Merge up to jdk8-b110

! .hgtags
- src/share/classes/com/sun/corba/se/impl/copyobject/JavaInputStream.sjava
- src/share/classes/com/sun/corba/se/impl/copyobject/JavaOutputStream.sjava
- src/share/classes/com/sun/corba/se/impl/interceptors/ThreadCurrentStack.sjava
- src/share/classes/com/sun/corba/se/impl/orbutil/DefineWrapper.sjava
- src/share/classes/com/sun/corba/se/impl/orbutil/ORBClassLoader.java
- src/share/classes/com/sun/corba/se/impl/presentation/rmi/IDLNameTranslatorImpl_save.sjava
- src/share/classes/com/sun/corba/se/impl/presentation/rmi/IDLTypesUtil_save.sjava
- src/share/classes/com/sun/corba/se/impl/protocol/oldlocal/LocalClientRequestImpl.sjava
- src/share/classes/com/sun/corba/se/impl/protocol/oldlocal/LocalClientResponseImpl.sjava
- src/share/classes/com/sun/corba/se/impl/protocol/oldlocal/LocalServerRequestImpl.sjava
- src/share/classes/com/sun/corba/se/impl/protocol/oldlocal/LocalServerResponseImpl.sjava
- src/share/classes/com/sun/corba/se/impl/transport/BufferConnectionImpl.sjava



From ed at camswl.com  Mon Oct 14 02:50:07 2013
From: ed at camswl.com (ed at camswl.com)
Date: Mon, 14 Oct 2013 09:50:07 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8: Added tag preview_rc1
	for changeset	60ddcc7923e7
Message-ID: <20131014095007.7129262364@hg.openjdk.java.net>

Changeset: 997c77161e47
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-14 09:47 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/997c77161e47

Added tag preview_rc1 for changeset 60ddcc7923e7

! .hgtags



From ed at camswl.com  Mon Oct 14 02:50:31 2013
From: ed at camswl.com (ed at camswl.com)
Date: Mon, 14 Oct 2013 09:50:31 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/corba: Added tag
	preview_rc1 for changeset	9e3acfd57153
Message-ID: <20131014095034.9EF9C62365@hg.openjdk.java.net>

Changeset: 70092fae1c15
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-14 09:50 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/70092fae1c15

Added tag preview_rc1 for changeset 9e3acfd57153

! .hgtags



From ed at camswl.com  Mon Oct 14 02:51:41 2013
From: ed at camswl.com (ed at camswl.com)
Date: Mon, 14 Oct 2013 09:51:41 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: Added tag
	preview_rc1 for changeset	f043f9395d36
Message-ID: <20131014095210.644DD62366@hg.openjdk.java.net>

Changeset: a99f56e36ea4
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-14 09:52 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/a99f56e36ea4

Added tag preview_rc1 for changeset f043f9395d36

! .hgtags



From ed at camswl.com  Mon Oct 14 02:53:23 2013
From: ed at camswl.com (ed at camswl.com)
Date: Mon, 14 Oct 2013 09:53:23 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/jaxp: Added tag
	preview_rc1 for changeset	e27c35e24ebe
Message-ID: <20131014095339.5A95862367@hg.openjdk.java.net>

Changeset: 415bce95f1a6
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-14 09:58 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/jaxp/rev/415bce95f1a6

Added tag preview_rc1 for changeset e27c35e24ebe

! .hgtags



From ed at camswl.com  Mon Oct 14 02:55:06 2013
From: ed at camswl.com (ed at camswl.com)
Date: Mon, 14 Oct 2013 09:55:06 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/jdk: Added tag
	preview_rc1 for changeset	48a5df5ce99c
Message-ID: <20131014095600.7CE496236A@hg.openjdk.java.net>

Changeset: e14d4b60b2c1
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-14 10:49 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/jdk/rev/e14d4b60b2c1

Added tag preview_rc1 for changeset 48a5df5ce99c

! .hgtags



From ed at camswl.com  Mon Oct 14 02:56:39 2013
From: ed at camswl.com (ed at camswl.com)
Date: Mon, 14 Oct 2013 09:56:39 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/langtools: Added tag
	preview_rc1 for changeset	9afeb870a2c1
Message-ID: <20131014095700.6AD686236B@hg.openjdk.java.net>

Changeset: 2c196e6bfa2a
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-14 10:05 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/langtools/rev/2c196e6bfa2a

Added tag preview_rc1 for changeset 9afeb870a2c1

! .hgtags



From ed at camswl.com  Mon Oct 14 02:57:48 2013
From: ed at camswl.com (ed at camswl.com)
Date: Mon, 14 Oct 2013 09:57:48 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/nashorn: Added tag
	preview_rc1 for changeset	4d291109480a
Message-ID: <20131014095756.0B3D06236C@hg.openjdk.java.net>

Changeset: b35e0d2e2a24
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-14 10:07 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/nashorn/rev/b35e0d2e2a24

Added tag preview_rc1 for changeset 4d291109480a

! .hgtags



From ed at camswl.com  Mon Oct 14 02:54:22 2013
From: ed at camswl.com (ed at camswl.com)
Date: Mon, 14 Oct 2013 09:54:22 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/jaxws: Added tag
	preview_rc1 for changeset	fb717aa8c6bb
Message-ID: <20131014095433.D48A862368@hg.openjdk.java.net>

Changeset: bbe175d5e634
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-14 10:03 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/jaxws/rev/bbe175d5e634

Added tag preview_rc1 for changeset fb717aa8c6bb

! .hgtags



From adinn at redhat.com  Tue Oct 15 07:12:56 2013
From: adinn at redhat.com (Andrew Dinn)
Date: Tue, 15 Oct 2013 15:12:56 +0100
Subject: [aarch64-port-dev ] Whether or not to revert of checkcast_arraycopy
 stub to generate return value expected by generic C2 code
Message-ID: <525D4D68.2060907@redhat.com>

The AArch64 checkcast_arraycopy stub has been implemented to employ a
different semantics for the return value to that employed by x86 and
this is running afoul of the expectations built into the generis layer
of C2.

Specifically, on x86 the return value is

  0 : if all values were copied
  -1^K : if a partial copy of K values occurred -- equivalently, -(k+1)

On aarch64 the return value is

  0 : if all values were copied
  K : if there are K values uncopied

(yes that first rule is really redundant)

The problem is that the generic code in the C2 compiler implements the
stub by generating ideal code which assumes the former return value
semantics i.e. it constructs a test node

  (If (Cmp res zero) cr)

to test the return value and then in the false branch generates

  (Set copied (XorI res -1))

and uses the result to feed some arithmetic nodes

  (SubI length copied)
  (AddI srcpos copied)
  (AddI dstpos copied)

which it then passes into a runtime call

  (CallRuntime "OptoRuntime::slow_arraycopy_Type")

So, we have two options here: revert the stub so it returns 0 or -1^K or
edit the generic layer code to include an AArch64-specific compilation
path which expects the semantics adopted for C1.

I have implemented the changes needed to revert the behaviour of the
stub and the diff is attached below.

Changing the generic code is not complex. It requires planting the same
branch

  (If (Cmp res zero) cr)

replacing the XorINode with

  (set copied (SubI length res))

and feeding this into the same 3 arithmetic nodes

  (SubI length copied)
  (AddI srcpos copied)
  (AddI dstpos copied)

The issue is whether we want to introduce an AARCH64 conditional
compilation path into the generic layer. If we avoid that and retain the
original semantics then that adds a tad more overhead when running the
stub (but not much). The difference in the calling code is trivial and
zero-cost in both the C1 and C2 case (change an eonw for either a mov or
a sub).

regards,


Andrew Dinn
-----------
diff -r 75997cf311bb src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Tue Oct 15 14:16:04
2013 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Tue Oct 15 14:30:27
2013 +0100
@@ -2223,10 +2223,12 @@
     __ ldr(src,              Address(sp, 4*BytesPerWord));

     if (copyfunc_addr != NULL) {
-      __ subw(rscratch1, length, r0); // Number of oops actually copied
+      // r0 is -1^K where K == partial copied count
+      __ eonw(rscratch1, r0, 0);
+      // adjust length down and src/end pos up by partial copied count
+      __ subw(length, length, rscratch1);
       __ addw(src_pos, src_pos, rscratch1);
       __ addw(dst_pos, dst_pos, rscratch1);
-      __ mov(length, r0); // Number of oops left to copy
     }
     __ b(*stub->entry());

@@ -2401,10 +2403,12 @@
 	__ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
 	__ ldr(src,              Address(sp, 4*BytesPerWord));

-	__ subw(rscratch1, length, r0); // Number of oops actually copied
+        // return value is -1^K where K is partial copied count
+        __ eonw(rscratch1, r0, zr);
+        // adjust length down and src/end pos up by partial copied count
+	__ subw(length, length, rscratch1);
 	__ addw(src_pos, src_pos, rscratch1);
 	__ addw(dst_pos, dst_pos, rscratch1);
-	__ mov(length, r0); // Number of oops left to copy
       }

       __ b(*stub->entry());
diff -r 75997cf311bb src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Tue Oct 15 14:16:04
2013 +0100
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Tue Oct 15 14:30:27
2013 +0100
@@ -1447,21 +1447,23 @@
   //    c_rarg4   - oop ckval (super_klass)
   //
   //  Output:
-  //    r0        -  count of oops remaining to copy
+  //    r0 ==  0  -  success
+  //    r0 == -1^K - failure, where K is partial transfer count
   //
   address generate_checkcast_copy(const char *name, address *entry,
                                   bool dest_uninitialized = false) {

-    Label L_load_element, L_store_element, L_do_card_marks, L_done;
+    Label L_load_element, L_store_element, L_do_card_marks, L_setup,
L_cleanup, L_done;

     // Input registers (after setup_arg_regs)
     const Register from        = c_rarg0;   // source array address
     const Register to          = c_rarg1;   // destination array address
-    const Register count       = c_rarg2;   // elementscount
+    const Register count_orig  = c_rarg2;   // orig elements count
     const Register ckoff       = c_rarg3;   // super_check_offset
     const Register ckval       = c_rarg4;   // super_klass

     // Registers used as temps (r18, r19, r20 are save-on-entry)
+    const Register count       = r21;       // loop counter
     const Register start_to    = r20;       // destination array start
address
     const Register copied_oop  = r18;       // actual oop copied
     const Register r19_klass   = r19;       // oop._klass
@@ -1473,8 +1475,8 @@
     // of the source type.  Each element must be separately
     // checked.

-    assert_different_registers(from, to, count, ckoff, ckval, start_to,
-			       copied_oop, r19_klass);
+    assert_different_registers(from, to, count_orig, ckoff, ckval,
start_to,
+			       copied_oop, r19_klass, count);

     __ align(CodeEntryAlignment);
     StubCodeMark mark(this, "StubRoutines", name);
@@ -1498,10 +1500,13 @@
       BLOCK_COMMENT("Entry:");
     }

-    // Empty array:  Nothing to do.
-    __ cbz(count, L_done);
+    __ cbnz(count_orig, L_setup);

-    __ push(r18->bit() | r19->bit() | r20->bit(), sp);
+    __ mov(r0, zr);
+    __ b(L_done);
+
+    __ bind(L_setup);
+    __ push(r18->bit() | r19->bit() | r20->bit() | r21->bit(), sp);

 #ifdef ASSERT
     BLOCK_COMMENT("assert consistent ckoff/ckval");
@@ -1517,6 +1522,9 @@
     }
 #endif //ASSERT

+    // the loop counts up from -count_orig to zero
+    __ sub(count, zr, count_orig);
+
     // Copy from low to high addresses
     __ mov(start_to, to);              // Save destination array start
address
     __ b(L_load_element);
@@ -1524,7 +1532,7 @@
     // ======== begin loop ========
     // (Loop is rotated; its entry is L_load_element.)
     // Loop control:
-    //   for (; count != 0; count--) {
+    //   for (count=-length; count != 0; count++) {
     //     copied_oop = load_heap_oop(from++);
     //     ... generate_type_check ...;
     //     store_heap_oop(to++, copied_oop);
@@ -1533,7 +1541,7 @@

     __ BIND(L_store_element);
     __ store_heap_oop(__ post(to, UseCompressedOops ? 4 : 8),
copied_oop);  // store the oop
-    __ sub(count, count, 1);
+    __ add(count, count, 1);
     __ cbz(count, L_do_card_marks);

     // ======== loop entry is here ========
@@ -1545,23 +1553,30 @@
     generate_type_check(r19_klass, ckoff, ckval, L_store_element);
     // ======== end loop ========

+    // exit point for failure
     // It was a real error; we must depend on the caller to finish the job.
-    // Register r0 = number of *remaining* oops
+    // Register count = -1 * remaining oops, count_save = total oops.
     // Emit GC store barriers for the oops we have copied and report
     // their number to the caller.

-    DEBUG_ONLY(__ nop());
+    __ add(to, to, -heapOopSize);         // make an inclusive end pointer
+    gen_write_ref_array_post_barrier(start_to, to, rscratch1);
+    __ add(r0, count_orig, count);        // K = partially copied oop count
+    __ eon(r0, r0, zr);                   // report (-1^K) to caller
+    __ b(L_cleanup);

-    // Common exit point (success or failure).
+    // exit point for success.
     __ BIND(L_do_card_marks);
     __ add(to, to, -heapOopSize);         // make an inclusive end pointer
     gen_write_ref_array_post_barrier(start_to, to, rscratch1);

-    __ pop(r18->bit() | r19->bit() | r20->bit(), sp);
+    __ mov(r0, 0);
+    // exit cleanup for success and failure
+    __ bind(L_cleanup);
+    __ pop(r18->bit() | r19->bit() | r20->bit()| r21->bit(), sp);
     inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr);

     __ bind(L_done);
-    __ mov(r0, count);                    // report count remaining to
caller
     __ leave();
     __ ret(lr);




From aph at redhat.com  Tue Oct 15 07:36:47 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 15 Oct 2013 15:36:47 +0100
Subject: [aarch64-port-dev ] Whether or not to revert of
 checkcast_arraycopy stub to generate return value expected by generic C2
 code
In-Reply-To: <525D4D68.2060907@redhat.com>
References: <525D4D68.2060907@redhat.com>
Message-ID: <525D52FF.6090204@redhat.com>

On 10/15/2013 03:12 PM, Andrew Dinn wrote:
> The AArch64 checkcast_arraycopy stub has been implemented to employ a
> different semantics for the return value to that employed by x86 and
> this is running afoul of the expectations built into the generis layer
> of C2.
> 
> Specifically, on x86 the return value is
> 
>   0 : if all values were copied
>   -1^K : if a partial copy of K values occurred -- equivalently, -(k+1)
> 
> On aarch64 the return value is
> 
>   0 : if all values were copied
>   K : if there are K values uncopied
> 
> (yes that first rule is really redundant)
> 
> The problem is that the generic code in the C2 compiler implements the
> stub by generating ideal code which assumes the former return value
> semantics i.e. it constructs a test node
> 
>   (If (Cmp res zero) cr)
> 
> to test the return value and then in the false branch generates
> 
>   (Set copied (XorI res -1))
> 
> and uses the result to feed some arithmetic nodes
> 
>   (SubI length copied)
>   (AddI srcpos copied)
>   (AddI dstpos copied)
> 
> which it then passes into a runtime call
> 
>   (CallRuntime "OptoRuntime::slow_arraycopy_Type")
> 
> So, we have two options here: revert the stub so it returns 0 or -1^K or
> edit the generic layer code to include an AArch64-specific compilation
> path which expects the semantics adopted for C1.
> 
> I have implemented the changes needed to revert the behaviour of the
> stub and the diff is attached below.

There's a better solution: keep the stub as it is, but if the copy
fails return -1^K.  I will make that change if you like.  It's much
better than the rather nightmarish code we had before.

Andrew.



From adinn at redhat.com  Tue Oct 15 07:47:56 2013
From: adinn at redhat.com (Andrew Dinn)
Date: Tue, 15 Oct 2013 15:47:56 +0100
Subject: [aarch64-port-dev ] Whether or not to revert of
 checkcast_arraycopy stub to generate return value expected by generic C2
 code
In-Reply-To: <525D52FF.6090204@redhat.com>
References: <525D4D68.2060907@redhat.com> <525D52FF.6090204@redhat.com>
Message-ID: <525D559C.7060803@redhat.com>

On 15/10/13 15:36, Andrew Haley wrote:
>> I have implemented the changes needed to revert the behaviour of the
>> stub and the diff is attached below.
> 
> There's a better solution: keep the stub as it is, but if the copy
> fails return -1^K.  I will make that change if you like.  It's much
> better than the rather nightmarish code we had before.

Well, that's actually what I have done. I didn't rewrite the code based
on what Intel does I merely rewrote your code to return -1^K.
Specifically, this required:

i) a skip at the start to allow posting 0 into rax when the input length
is zero length input case. This could be improved if we planted the mov
r0, zr and ret out of line.

ii) an extra register saved in the push and pop so we can keep the
original count -- needed to compute K (== count_orig - count) n.b. this
is essentially free because one of the stps is using zr.

iii) variant code in the fail case to compute -1^K and do its own card
marking

iv) an extra label L_cleanup and extra branch to it after the fail case
so as to skip the move of 0 into r0 and card marking done in the success
case but still do the pop in both cases.

Looking at it again I think the duplication of the card marking code
could be avoided by moving it after L_cleanup

regards,


Andrew Dinn
-----------
Principal Software Engineer
Red Hat UK Ltd
Registered in UK and Wales under Company Registration No. 3798903
Directors: Michael Cunningham (USA), Matt Parson (USA), Charlie Peters
(USA), Paul Hickey (Ireland)


From adinn at redhat.com  Tue Oct 15 08:22:04 2013
From: adinn at redhat.com (Andrew Dinn)
Date: Tue, 15 Oct 2013 16:22:04 +0100
Subject: [aarch64-port-dev ] Whether or not to revert of
 checkcast_arraycopy stub to generate return value expected by generic C2
 code
In-Reply-To: <525D559C.7060803@redhat.com>
References: <525D4D68.2060907@redhat.com> <525D52FF.6090204@redhat.com>
	<525D559C.7060803@redhat.com>
Message-ID: <525D5D9C.4060100@redhat.com>

Hmm, yes but I did borrow the counting up from negative from the Intel
code and also ended up adding code to the zero, success, fail cases that
is merged in your original. Here's a proper rewrite based more closely
on your code which avoids a lot of the redundancy in my original
version. It really just adds the save of the original count and the
compute of -1^K so the extra cost is minimal.

regards,


Andrew Dinn
-----------


diff -r 75997cf311bb src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Tue Oct 15 14:16:04
2013 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Tue Oct 15 16:17:45
2013 +0100
@@ -2223,10 +2223,12 @@
     __ ldr(src,              Address(sp, 4*BytesPerWord));

     if (copyfunc_addr != NULL) {
-      __ subw(rscratch1, length, r0); // Number of oops actually copied
+      // r0 is -1^K where K == partial copied count
+      __ eonw(rscratch1, r0, 0);
+      // adjust length down and src/end pos up by partial copied count
+      __ subw(length, length, rscratch1);
       __ addw(src_pos, src_pos, rscratch1);
       __ addw(dst_pos, dst_pos, rscratch1);
-      __ mov(length, r0); // Number of oops left to copy
     }
     __ b(*stub->entry());

@@ -2401,10 +2403,12 @@
 	__ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
 	__ ldr(src,              Address(sp, 4*BytesPerWord));

-	__ subw(rscratch1, length, r0); // Number of oops actually copied
+        // return value is -1^K where K is partial copied count
+        __ eonw(rscratch1, r0, zr);
+        // adjust length down and src/end pos up by partial copied count
+	__ subw(length, length, rscratch1);
 	__ addw(src_pos, src_pos, rscratch1);
 	__ addw(dst_pos, dst_pos, rscratch1);
-	__ mov(length, r0); // Number of oops left to copy
       }

       __ b(*stub->entry());
diff -r 75997cf311bb src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Tue Oct 15 14:16:04
2013 +0100
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Tue Oct 15 16:17:45
2013 +0100
@@ -1447,7 +1447,8 @@
   //    c_rarg4   - oop ckval (super_klass)
   //
   //  Output:
-  //    r0        -  count of oops remaining to copy
+  //    r0 ==  0  -  success
+  //    r0 == -1^K - failure, where K is partial transfer count
   //
   address generate_checkcast_copy(const char *name, address *entry,
                                   bool dest_uninitialized = false) {
@@ -1462,6 +1463,7 @@
     const Register ckval       = c_rarg4;   // super_klass

     // Registers used as temps (r18, r19, r20 are save-on-entry)
+    const Register count_save  = r21;       // orig elementscount
     const Register start_to    = r20;       // destination array start
address
     const Register copied_oop  = r18;       // actual oop copied
     const Register r19_klass   = r19;       // oop._klass
@@ -1474,7 +1476,7 @@
     // checked.

     assert_different_registers(from, to, count, ckoff, ckval, start_to,
-			       copied_oop, r19_klass);
+			       copied_oop, r19_klass, count_save);

     __ align(CodeEntryAlignment);
     StubCodeMark mark(this, "StubRoutines", name);
@@ -1498,10 +1500,10 @@
       BLOCK_COMMENT("Entry:");
     }

-    // Empty array:  Nothing to do.
+     // Empty array:  Nothing to do.
     __ cbz(count, L_done);

-    __ push(r18->bit() | r19->bit() | r20->bit(), sp);
+    __ push(r18->bit() | r19->bit() | r20->bit() | r21->bit(), sp);

 #ifdef ASSERT
     BLOCK_COMMENT("assert consistent ckoff/ckval");
@@ -1517,6 +1519,9 @@
     }
 #endif //ASSERT

+    // save the original count
+    __ mov(count_save, count);
+
     // Copy from low to high addresses
     __ mov(start_to, to);              // Save destination array start
address
     __ b(L_load_element);
@@ -1546,22 +1551,22 @@
     // ======== end loop ========

     // It was a real error; we must depend on the caller to finish the job.
-    // Register r0 = number of *remaining* oops
+    // Register count = remaining oops, count_orig = total oops.
     // Emit GC store barriers for the oops we have copied and report
     // their number to the caller.

-    DEBUG_ONLY(__ nop());
+    __ sub(count, count_save, count);     // K = partially copied oop count
+    __ eon(count, count, zr);                   // report (-1^K) to caller

-    // Common exit point (success or failure).
     __ BIND(L_do_card_marks);
     __ add(to, to, -heapOopSize);         // make an inclusive end pointer
     gen_write_ref_array_post_barrier(start_to, to, rscratch1);

-    __ pop(r18->bit() | r19->bit() | r20->bit(), sp);
+    __ pop(r18->bit() | r19->bit() | r20->bit()| r21->bit(), sp);
     inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr);

     __ bind(L_done);
-    __ mov(r0, count);                    // report count remaining to
caller
+    __ mov(r0, count);
     __ leave();
     __ ret(lr);


From aph at redhat.com  Tue Oct 15 08:32:20 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 15 Oct 2013 16:32:20 +0100
Subject: [aarch64-port-dev ] Whether or not to revert of
 checkcast_arraycopy stub to generate return value expected by generic C2
 code
In-Reply-To: <525D5D9C.4060100@redhat.com>
References: <525D4D68.2060907@redhat.com> <525D52FF.6090204@redhat.com>
	<525D559C.7060803@redhat.com> <525D5D9C.4060100@redhat.com>
Message-ID: <525D6004.1060402@redhat.com>

On 10/15/2013 04:22 PM, Andrew Dinn wrote:
> Hmm, yes but I did borrow the counting up from negative from the Intel
> code and also ended up adding code to the zero, success, fail cases that
> is merged in your original. Here's a proper rewrite based more closely
> on your code which avoids a lot of the redundancy in my original
> version. It really just adds the save of the original count and the
> compute of -1^K so the extra cost is minimal.

That looks right.

Andrew.



From adinn at redhat.com  Tue Oct 15 08:37:55 2013
From: adinn at redhat.com (Andrew Dinn)
Date: Tue, 15 Oct 2013 16:37:55 +0100
Subject: [aarch64-port-dev ] Whether or not to revert of
 checkcast_arraycopy stub to generate return value expected by generic C2
 code
In-Reply-To: <525D6004.1060402@redhat.com>
References: <525D4D68.2060907@redhat.com> <525D52FF.6090204@redhat.com>
	<525D559C.7060803@redhat.com> <525D5D9C.4060100@redhat.com>
	<525D6004.1060402@redhat.com>
Message-ID: <525D6153.4030204@redhat.com>

On 15/10/13 16:32, Andrew Haley wrote:
> On 10/15/2013 04:22 PM, Andrew Dinn wrote:
>> Hmm, yes but I did borrow the counting up from negative from the Intel
>> code and also ended up adding code to the zero, success, fail cases that
>> is merged in your original. Here's a proper rewrite based more closely
>> on your code which avoids a lot of the redundancy in my original
>> version. It really just adds the save of the original count and the
>> compute of -1^K so the extra cost is minimal.
> 
> That looks right.

Ok, I'll check this in.


regards,


Andrew Dinn
-----------



From adinn at redhat.com  Tue Oct 15 09:11:35 2013
From: adinn at redhat.com (adinn at redhat.com)
Date: Tue, 15 Oct 2013 16:11:35 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: 4 new changesets
Message-ID: <20131015161150.B4D68623F0@hg.openjdk.java.net>

Changeset: 658ead2379ef
Author:    adinn
Date:      2013-10-15 14:08 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/658ead2379ef

modify C1 to notify method names with . not / as package separator

this means that when you simbreak a method you can use the same format
as when printed out by TraceCompilation  and hsdis. This also makes it
uniform with C2 so a given breakpoint works with both compilers.

! src/share/vm/c1/c1_Compilation.cpp

Changeset: 5075a0ca6a07
Author:    adinn
Date:      2013-10-15 14:12 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/5075a0ca6a07

ensure iRegP_R0 outputs can be matched with general iRegP inputs

! src/cpu/aarch64/vm/aarch64.ad

Changeset: 75997cf311bb
Author:    adinn
Date:      2013-10-15 14:16 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/75997cf311bb

implement instructons matching CmpF3 and CmpD3 ideal nodes

i.e. cmp two floats/doubles and generate -1 / 0 / 1 for LTU / EQ / GT

! src/cpu/aarch64/vm/aarch64.ad

Changeset: 965b63104307
Author:    adinn
Date:      2013-10-15 17:10 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/965b63104307

reverted checkcast_arraycopy stub to return -1 ^ num_left_to_copy if copy fails

the generic code in C2 expects this result and its better to avoid the
maintenance/integration issues which arise from changing generic code
if we don't have a compelling performance reason

! src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
! src/cpu/aarch64/vm/stubGenerator_aarch64.cpp



From adinn at redhat.com  Tue Oct 15 09:21:46 2013
From: adinn at redhat.com (Andrew Dinn)
Date: Tue, 15 Oct 2013 17:21:46 +0100
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: 4 new
	changesets
In-Reply-To: <20131015161150.B4D68623F0@hg.openjdk.java.net>
References: <20131015161150.B4D68623F0@hg.openjdk.java.net>
Message-ID: <525D6B9A.6030800@redhat.com>

Just wanted to note that with these changes (which are *on top* of Ed's
upgrade to jdk8-b110) javac now runs to completion again (array index
error was due to the arraycopy issue) and I manage to run eclipse with
-Xcomp for about 30 minutes on my machine (i.e. probably about 10
minutes on Andrew's hot box) before it breaks with a register allocator
error. javac has a problem if you don't provide -XX:-TieredCompilation
which I still need to investigate but overall this is great progress.

Once again, many thanks to Ed for making the merge so clean!

regards,

Andrew Dinn
-----------

On 15/10/13 17:11, adinn at redhat.com wrote:
> Changeset: 658ead2379ef
> Author:    adinn
> Date:      2013-10-15 14:08 +0100
> URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/658ead2379ef
> 
> modify C1 to notify method names with . not / as package separator
> 
> this means that when you simbreak a method you can use the same format
> as when printed out by TraceCompilation  and hsdis. This also makes it
> uniform with C2 so a given breakpoint works with both compilers.
> 
> ! src/share/vm/c1/c1_Compilation.cpp
> 
> Changeset: 5075a0ca6a07
> Author:    adinn
> Date:      2013-10-15 14:12 +0100
> URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/5075a0ca6a07
> 
> ensure iRegP_R0 outputs can be matched with general iRegP inputs
> 
> ! src/cpu/aarch64/vm/aarch64.ad
> 
> Changeset: 75997cf311bb
> Author:    adinn
> Date:      2013-10-15 14:16 +0100
> URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/75997cf311bb
> 
> implement instructons matching CmpF3 and CmpD3 ideal nodes
> 
> i.e. cmp two floats/doubles and generate -1 / 0 / 1 for LTU / EQ / GT
> 
> ! src/cpu/aarch64/vm/aarch64.ad
> 
> Changeset: 965b63104307
> Author:    adinn
> Date:      2013-10-15 17:10 +0100
> URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/965b63104307
> 
> reverted checkcast_arraycopy stub to return -1 ^ num_left_to_copy if copy fails
> 
> the generic code in C2 expects this result and its better to avoid the
> maintenance/integration issues which arise from changing generic code
> if we don't have a compelling performance reason
> 
> ! src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
> ! src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
> 
> 


From edward.nevill at linaro.org  Wed Oct 16 04:17:45 2013
From: edward.nevill at linaro.org (Edward Nevill)
Date: Wed, 16 Oct 2013 12:17:45 +0100
Subject: [aarch64-port-dev ] RFR: Fix for UseCompressedClassPointers
Message-ID: <1381922265.8150.19.camel@localhost.localdomain>

Hi,

The following patch fixes UseCompressedClassPointers for C1 and C2 and re-enables them by default for C2.

Basically the change is that there are now 2 narrow bases, narrow_klass_base and narrow_oop_base. narrow_oop_base is kept in rheapbase as before.

This means that in encode_klass and decode_klass we must add/sub narrow_klass_base and we do not have it conveniently in a register.

Unfortunately rscratch1 and rscratch2 are variously used by callers of encode_klass and decode_klass. So what I do is use rheapbase as a scratch register if necessary, and then call reinit_heapbase afterwards to restore it. This mirrors what is done on x86.

It is not possible to call add(...) to simply add/sub either the narrow_klass_base or the delta between the narrow_klass_base and the narrow_oop_base because of the following in MacroAssembler::wrap_add_sub_imm_insn(...)

...
       assert_different_registers(Rd, Rn);
       mov(Rd, (uint64_t)imm);
       (this->*insn2)(Rd, Rn, Rd, LSL, 0);
...

Because of the limited range of add/sub handled on aarch64 (+/- 1<<24) we cannot use add/sub unless we can guarantee that the src and dst registers are different which leads to us needing a scratch register so we are back where we started.

I have also made a change in aarch64.ad to fix a case where encode_heap_oop_not_null was in fact being called with a null constant. Also I remove some bogus guarantees from nativeInst_aarch64 to make it work for C2.

I know the above solution is not ideal and we would prefer a more optimal solution, however it is at least correct so I would like to push it and look at ways of optimising later.

Possible optimisation is to add an additional arg to encode/decode klass which is the scratch register to be used. Then the callers can either pass in rscratch1, rscratch2, or rheapbase if they genuinely do not have a free scratch register.

Ok to push?
Ed.

--- CUT HERE ---
exporting patch:
# HG changeset patch
# User Edward Nevill edward.nevill at linaro.org
# Date 1381920878 -3600
#      Wed Oct 16 11:54:38 2013 +0100
# Node ID 778fdde3772e321c55fefa3df6f22c3e7d49cd33
# Parent  a99f56e36ea4ad581c901c44a27906919485e30c
Fix UseCompressedClassPointers

diff -r a99f56e36ea4 -r 778fdde3772e src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Mon Oct 14 09:52:17 2013 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 16 11:54:38 2013 +0100
@@ -2375,7 +2375,7 @@
     // need to do this the hard way until we can manage relocs
     // for 32 bit constants
     __ movoop(rscratch2, (jobject)con);
-    __ encode_heap_oop_not_null(rscratch2);
+    if (con) __ encode_heap_oop_not_null(rscratch2);
     if (index == -1) {
       __ strw(rscratch2, Address(base, disp));
     } else {
@@ -2621,7 +2621,7 @@
       // need to do this the hard way until we can manage relocs
       // for 32 bit constants
       __ movoop(rscratch2, (jobject)con);
-      __ encode_heap_oop_not_null(rscratch2);
+      if (con) __ encode_heap_oop_not_null(rscratch2);
     }
     MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
 		 rscratch1, stlrw);
@@ -2634,8 +2634,9 @@
       // need to do this the hard way until we can manage relocs
       // for 32 bit constants
       __ movoop(rscratch2, (jobject)con);
-      __ encode_heap_oop_not_null(rscratch2);
-      __ encode_klass_not_null(rscratch2);
+      // Either it is a heap oop or a klass pointer? It can't be both?
+      // __ encode_heap_oop_not_null(rscratch2);
+      if (con) __ encode_klass_not_null(rscratch2);
     }
     MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
 		 rscratch1, stlrw);
diff -r a99f56e36ea4 -r 778fdde3772e src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Mon Oct 14 09:52:17 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Wed Oct 16 11:54:38 2013 +0100
@@ -1644,8 +1644,8 @@
 void MacroAssembler::reinit_heapbase()
 {
   if (UseCompressedOops) {
-    lea(rscratch1, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
-    ldr(rheapbase, Address(rscratch1));
+    lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
+    ldr(rheapbase, Address(rheapbase));
   }
 }
 
@@ -2078,73 +2078,46 @@
   }
 }
 
-void MacroAssembler::encode_klass_not_null(Register r) {
-#ifdef ASSERT
-  verify_heapbase("MacroAssembler::encode_klass_not_null: heap base corrupted?");
-#endif
-  if (Universe::narrow_klass_base() != NULL) {
-    sub(r, r, rheapbase);
-  }
-  if (Universe::narrow_klass_shift() != 0) {
-    assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
-    lsr(r, r, LogKlassAlignmentInBytes);
-  }
-}
-
-void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
-#ifdef ASSERT
-  verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
-#endif
-  if (dst != src) {
-    mov(dst, src);
-  }
-  if (Universe::narrow_klass_base() != NULL) {
-    sub(dst, dst, rheapbase);
-  }
-  if (Universe::narrow_klass_shift() != 0) {
-    assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
-    lsr(dst, dst, LogKlassAlignmentInBytes);
-  }
-}
-
-void  MacroAssembler::decode_klass_not_null(Register r) {
-  // Note: it will change flags
-  assert (UseCompressedClassPointers, "should only be used for compressed headers");
-  // Cannot assert, unverified entry point counts instructions (see .ad file)
-  // vtableStubs also counts instructions in pd_code_size_limit.
-  // Also do not verify_oop as this is called by verify_oop.
-  if (Universe::narrow_klass_shift() != 0) {
-    assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
-    if (Universe::narrow_klass_base() != NULL) {
-      add(r, rheapbase, r, Assembler::LSL, LogKlassAlignmentInBytes);
-    } else {
-      add(r, zr, r, Assembler::LSL, LogKlassAlignmentInBytes);
-    }
-  } else {
-    assert (Universe::narrow_klass_base() == NULL, "sanity");
-  }
-}
-
-void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
-  // Note: it will change flags
-  assert (UseCompressedClassPointers, "should only be used for compressed headers");
-  // Cannot assert, unverified entry point counts instructions (see .ad file)
-  // vtableStubs also counts instructions in pd_code_size_limit.
-  // Also do not verify_oop as this is called by verify_oop.
-  if (Universe::narrow_klass_shift() != 0) {
-    assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
-    if (Universe::narrow_klass_base() != NULL) {
-      add(dst, rheapbase, src, Assembler::LSL, LogKlassAlignmentInBytes);
-    } else {
-      add(dst, zr, src, Assembler::LSL, LogKlassAlignmentInBytes);
-    }
-  } else {
-    assert (Universe::narrow_klass_base() == NULL, "sanity");
-    if (dst != src) {
-      mov(dst, src);
-    }
-  }
-}
+void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 
+  Register rbase = dst; 
+#ifdef ASSERT 
+  verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?"); 
+#endif 
+  if (dst == src) rbase = rheapbase; 
+  mov(rbase, (uint64_t)Universe::narrow_klass_base()); 
+  sub(dst, src, rbase); 
+  if (Universe::narrow_klass_shift() != 0) { 
+    assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 
+    lsr(dst, dst, LogKlassAlignmentInBytes); 
+  } 
+  if (dst == src) reinit_heapbase(); 
+} 
+ 
+void MacroAssembler::encode_klass_not_null(Register r) { 
+  encode_klass_not_null(r, r); 
+} 
+ 
+void  MacroAssembler::decode_klass_not_null(Register dst, Register src) { 
+  Register rbase = dst; 
+  assert(Universe::narrow_klass_base() != NULL, "Base should be initialized"); 
+  assert (UseCompressedClassPointers, "should only be used for compressed headers"); 
+  // Cannot assert, unverified entry point counts instructions (see .ad file) 
+  // vtableStubs also counts instructions in pd_code_size_limit. 
+  // Also do not verify_oop as this is called by verify_oop. 
+  if (dst == src) rbase = rheapbase; 
+  mov(rbase, (uint64_t)Universe::narrow_klass_base()); 
+  if (Universe::narrow_klass_shift() != 0) { 
+    assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 
+    add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes); 
+  } else { 
+    add(dst, rbase, src); 
+  } 
+  if (dst == src) reinit_heapbase(); 
+} 
+ 
+void  MacroAssembler::decode_klass_not_null(Register r) { 
+  decode_klass_not_null(r, r); 
+} 
 
 // TODO
 //
diff -r a99f56e36ea4 -r 778fdde3772e src/cpu/aarch64/vm/nativeInst_aarch64.cpp
--- a/src/cpu/aarch64/vm/nativeInst_aarch64.cpp	Mon Oct 14 09:52:17 2013 +0100
+++ b/src/cpu/aarch64/vm/nativeInst_aarch64.cpp	Wed Oct 16 11:54:38 2013 +0100
@@ -143,19 +143,6 @@
 void NativeJump::insert(address code_pos, address entry) { Unimplemented(); }
 
 void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) {
-  // Patching to not_entrant can happen while activations of the method are
-  // in use. The patching in that instance must happen only when certain
-  // alignment restrictions are true. These guarantees check those
-  // conditions.
-  const int linesize = 64;
-
-  // Must be wordSize aligned
-  guarantee(((uintptr_t) verified_entry & (wordSize -1)) == 0,
-            "illegal address for code patching 2");
-  // First 5 bytes must be within the same cache line - 4827828
-  guarantee((uintptr_t) verified_entry / linesize ==
-            ((uintptr_t) verified_entry + 4) / linesize,
-            "illegal address for code patching 3");
 }
 
 
diff -r a99f56e36ea4 -r 778fdde3772e src/share/vm/runtime/arguments.cpp
--- a/src/share/vm/runtime/arguments.cpp	Mon Oct 14 09:52:17 2013 +0100
+++ b/src/share/vm/runtime/arguments.cpp	Wed Oct 16 11:54:38 2013 +0100
@@ -1471,13 +1471,10 @@
     }
     FLAG_SET_DEFAULT(UseCompressedClassPointers, false);
   } else {
-// ECN: FIXME - UseCompressedClassPointers is temporarily broken
-#ifndef AARCH64
     // Turn on UseCompressedClassPointers too
     if (FLAG_IS_DEFAULT(UseCompressedClassPointers)) {
       FLAG_SET_ERGO(bool, UseCompressedClassPointers, true);
     }
-#endif
     // Check the CompressedClassSpaceSize to make sure we use compressed klass ptrs.
     if (UseCompressedClassPointers) {
       if (CompressedClassSpaceSize > KlassEncodingMetaspaceMax) {
--- CUT HERE ---




From aph at redhat.com  Wed Oct 16 08:08:07 2013
From: aph at redhat.com (Andrew Haley)
Date: Wed, 16 Oct 2013 16:08:07 +0100
Subject: [aarch64-port-dev ] RFR: Fix for UseCompressedClassPointers
In-Reply-To: <1381922265.8150.19.camel@localhost.localdomain>
References: <1381922265.8150.19.camel@localhost.localdomain>
Message-ID: <525EABD7.1090505@redhat.com>

On 10/16/2013 12:17 PM, Edward Nevill wrote:
> Ok to push?

OK, thanks.

Andrew.



From ed at camswl.com  Wed Oct 16 08:20:39 2013
From: ed at camswl.com (ed at camswl.com)
Date: Wed, 16 Oct 2013 15:20:39 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: Fix
	UseCompressedClassPointers
Message-ID: <20131016152052.7540262463@hg.openjdk.java.net>

Changeset: adaa8a971059
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-16 16:19 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/adaa8a971059

Fix UseCompressedClassPointers

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
! src/cpu/aarch64/vm/nativeInst_aarch64.cpp
! src/share/vm/runtime/arguments.cpp



From edward.nevill at linaro.org  Thu Oct 17 06:33:54 2013
From: edward.nevill at linaro.org (Edward Nevill)
Date: Thu, 17 Oct 2013 14:33:54 +0100
Subject: [aarch64-port-dev ] RFR: Turn TieredCompilation off by default
Message-ID: <1382016834.18229.6.camel@localhost.localdomain>

Hi,

In the recent merge I accidentally enabled TieredCompilation as a run time default.

This was due to a misconception om my part where I believed that if one wrote

--with-jvm-variants=server

one got a C2 compiler and

--with-jvm-variants=client

one got a C1 compiler and

--with-jvm-variants=tiered

one got a tiered C1/C2 compiler.

Sadly, this is not the case.

The following patch reverts the default.

Regards,
Ed.

--- CUT HERE ---
exporting patch:
# HG changeset patch
# User Edward Nevill edward.nevill at linaro.org
# Date 1382016264 -3600
#      Thu Oct 17 14:24:24 2013 +0100
# Node ID 970503d686f07cf9f82326d0dda7ad730b690433
# Parent  adaa8a9710598fa47b7eccefdc421a22e1333f80
Fix mismerge, turn TieredCompilation off by default, as it was before the merge

diff -r adaa8a971059 -r 970503d686f0 src/cpu/aarch64/vm/c2_globals_aarch64.hpp
--- a/src/cpu/aarch64/vm/c2_globals_aarch64.hpp	Wed Oct 16 16:19:35 2013 +0100
+++ b/src/cpu/aarch64/vm/c2_globals_aarch64.hpp	Thu Oct 17 14:24:24 2013 +0100
@@ -46,7 +46,7 @@
 #else
 define_pd_global(bool, ProfileInterpreter,           true);
 #endif // CC_INTERP
-define_pd_global(bool, TieredCompilation,            trueInTiered);
+define_pd_global(bool, TieredCompilation,            false);
 define_pd_global(intx, CompileThreshold,             10000);
 define_pd_global(intx, BackEdgeThreshold,            100000);
 
--- CUT HERE ---




From ed at camswl.com  Thu Oct 17 06:35:23 2013
From: ed at camswl.com (ed at camswl.com)
Date: Thu, 17 Oct 2013 13:35:23 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: Fix mismerge,
	turn TieredCompilation off by default, as it was before the merge
Message-ID: <20131017133543.9FF3A624B3@hg.openjdk.java.net>

Changeset: 970503d686f0
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-17 14:24 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/970503d686f0

Fix mismerge, turn TieredCompilation off by default, as it was before the merge

! src/cpu/aarch64/vm/c2_globals_aarch64.hpp



From aph at redhat.com  Thu Oct 17 08:59:09 2013
From: aph at redhat.com (Andrew Haley)
Date: Thu, 17 Oct 2013 16:59:09 +0100
Subject: [aarch64-port-dev ] Use XOR encoding for compressed class pointers
Message-ID: <5260094D.9030200@redhat.com>

The new encoding for compressed class pointers generates fugly code on AArch64.

Like this for method entry:

  0x00007fffe123f9a0: ldr	wscratch1, [x1,#8]  ;   {no_reloc}
  0x00007fffe122f784: orr	xheapbase, xzr, #0x800000000
  0x00007fffe122f788: add	xscratch1, xheapbase, xscratch1
  ;; 0x7FFFF7DA3BC8
  0x00007fffe122f78c: movz	xheapbase, #0x3bc8  ;   {external_word}
  0x00007fffe122f790: movk	xheapbase, #0xf7da, lsl #16
  0x00007fffe122f794: movk	xheapbase, #0x7fff, lsl #32
  0x00007fffe122f798: movk	xheapbase, #0x0, lsl #48
  0x00007fffe122f79c: ldr	xheapbase, [xheapbase]
  0x00007fffe122f7a0: cmp	xscratch2, xscratch1
  0x00007fffe122f7a4: b.eq	0x00007fffe122f7b0

This patch takes advantage of the fact that the default base for
compressed classes is 0x800000000, which allows us to compress and
decompress class pointers simply by flipping an address bit.  So the
above code becomes:

  0x00007fffe122e280: ldr	wscratch1, [x1,#8]
  0x00007fffe122e284: eor	xscratch1, xscratch1, #0x800000000
  0x00007fffe122e288: cmp	xscratch2, xscratch1
  0x00007fffe122e28c: b.eq	0x00007fffe122e298

When ENcoding, it's not clear to me that any work is needed at all,
because we'll be storing a 32-bit word.  However, just to be on the
safe side I'm clearing bit 0x800000000 anyway; at some point in the
future we could delete this code.

Andrew.


# HG changeset patch
# User aph
# Date 1382024809 -3600
# Node ID 7ad16844c57ec14065f6354b1d8e75f965489ab4
# Parent  03f55b66e8cf056deef588742f64ed4c8c5eb0ef
Use XOR encoding for compressed class pointers.

diff -r 03f55b66e8cf -r 7ad16844c57e src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Thu Oct 17 16:33:03 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Thu Oct 17 16:46:49 2013 +0100
@@ -2079,10 +2079,21 @@
 }

 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
-  Register rbase = dst;
+  if (use_XOR_for_compressed_class_base) {
+    if (Universe::narrow_klass_shift() != 0) {
+      eor(dst, src, (uint64_t)Universe::narrow_klass_base());
+      lsr(dst, dst, LogKlassAlignmentInBytes);
+    } else {
+      eor(dst, src, (uint64_t)Universe::narrow_klass_base());
+    }
+    return;
+  }
+
 #ifdef ASSERT
   verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
 #endif
+
+  Register rbase = dst;
   if (dst == src) rbase = rheapbase;
   mov(rbase, (uint64_t)Universe::narrow_klass_base());
   sub(dst, src, rbase);
@@ -2101,6 +2112,17 @@
   Register rbase = dst;
   assert(Universe::narrow_klass_base() != NULL, "Base should be initialized");
   assert (UseCompressedClassPointers, "should only be used for compressed headers");
+
+  if (use_XOR_for_compressed_class_base) {
+    if (Universe::narrow_klass_shift() != 0) {
+      lsl(dst, src, LogKlassAlignmentInBytes);
+      eor(dst, dst, (uint64_t)Universe::narrow_klass_base());
+    } else {
+      eor(dst, src, (uint64_t)Universe::narrow_klass_base());
+    }
+    return;
+  }
+
   // Cannot assert, unverified entry point counts instructions (see .ad file)
   // vtableStubs also counts instructions in pd_code_size_limit.
   // Also do not verify_oop as this is called by verify_oop.
diff -r 03f55b66e8cf -r 7ad16844c57e src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Thu Oct 17 16:33:03 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Thu Oct 17 16:46:49 2013 +0100
@@ -90,10 +90,16 @@
   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);

   // Maximum size of class area in Metaspace when compressed
-  uint64_t useBoolForCompressedClassEncoding;
+  uint64_t use_XOR_for_compressed_class_base;

  public:
-  MacroAssembler(CodeBuffer* code) : Assembler(code) {}
+  MacroAssembler(CodeBuffer* code) : Assembler(code) {
+    use_XOR_for_compressed_class_base
+      = (operand_valid_for_logical_immediate(false /*is32*/,
+					     (uint64_t)Universe::narrow_klass_base())
+	 && ((uint64_t)Universe::narrow_klass_base()
+	     > (1u << log2_intptr(CompressedClassSpaceSize))));
+  }

   // Biased locking support
   // lock_reg and obj_reg must be loaded up with the appropriate values.


From aph at redhat.com  Thu Oct 17 11:02:28 2013
From: aph at redhat.com (Andrew Haley)
Date: Thu, 17 Oct 2013 19:02:28 +0100
Subject: [aarch64-port-dev ] C1: Restore LR for use by C2 runtime
Message-ID: <52602634.8030800@redhat.com>

C1 doesn't bother to restore the link register when throwing an exception
because its runtime doesn't care.  The C2 runtime does care, however, so
we need to restore it because we might be throwing back to C2-compiled
code.

Andrew.


# HG changeset patch
# User aph
# Date 1382032180 -3600
# Node ID 0fdfde0445496891b057f34c3fce74f9ca3dd3ce
# Parent  7ad16844c57ec14065f6354b1d8e75f965489ab4
Restore LR for use by C2 runtime

diff -r 7ad16844c57e -r 0fdfde044549 src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp	Thu Oct 17 16:46:49 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp	Thu Oct 17 18:49:40 2013 +0100
@@ -509,7 +509,8 @@

   // get throwing pc (= return address).
   // lr has been destroyed by the call
-  __ ldp(r3, exception_oop, Address(__ post(sp, 2 * wordSize)));
+  __ ldp(lr, exception_oop, Address(__ post(sp, 2 * wordSize)));
+  __ mov(r3, lr);

   __ verify_not_null_oop(exception_oop);



From ed at camswl.com  Fri Oct 18 07:10:08 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 18 Oct 2013 14:10:08 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: 2 new changesets
Message-ID: <20131018141018.B55D662521@hg.openjdk.java.net>

Changeset: b0ade87641c2
Author:    aph
Date:      2013-10-17 16:46 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/b0ade87641c2

Use XOR encoding for compressed class pointers.

! src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
! src/cpu/aarch64/vm/macroAssembler_aarch64.hpp

Changeset: 33029403ab59
Author:    aph
Date:      2013-10-17 18:49 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/33029403ab59

Restore LR for use by C2 runtime

! src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp



From ed at camswl.com  Fri Oct 18 07:13:19 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 18 Oct 2013 14:13:19 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8: Added tag preview_rc2
	for changeset	997c77161e47
Message-ID: <20131018141319.9FC0462522@hg.openjdk.java.net>

Changeset: 2a5d28175646
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-18 15:11 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/rev/2a5d28175646

Added tag preview_rc2 for changeset 997c77161e47

! .hgtags



From ed at camswl.com  Fri Oct 18 07:14:50 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 18 Oct 2013 14:14:50 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: Added tag
	preview_rc2 for changeset	33029403ab59
Message-ID: <20131018141453.2D44162524@hg.openjdk.java.net>

Changeset: c04eaee39c1b
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-18 15:11 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/c04eaee39c1b

Added tag preview_rc2 for changeset 33029403ab59

! .hgtags



From ed at camswl.com  Fri Oct 18 07:14:10 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 18 Oct 2013 14:14:10 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/corba: Added tag
	preview_rc2 for changeset	70092fae1c15
Message-ID: <20131018141413.E759462523@hg.openjdk.java.net>

Changeset: 17382eea5933
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-18 15:11 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/corba/rev/17382eea5933

Added tag preview_rc2 for changeset 70092fae1c15

! .hgtags



From ed at camswl.com  Fri Oct 18 07:15:37 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 18 Oct 2013 14:15:37 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/jaxp: Added tag
	preview_rc2 for changeset	415bce95f1a6
Message-ID: <20131018141546.2E5AD62525@hg.openjdk.java.net>

Changeset: dbc67ffb0dbf
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-18 15:11 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/jaxp/rev/dbc67ffb0dbf

Added tag preview_rc2 for changeset 415bce95f1a6

! .hgtags



From ed at camswl.com  Fri Oct 18 07:17:21 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 18 Oct 2013 14:17:21 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/jdk: Added tag
	preview_rc2 for changeset	e14d4b60b2c1
Message-ID: <20131018141759.7ACDB62529@hg.openjdk.java.net>

Changeset: 445cf19d4a9b
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-18 15:12 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/jdk/rev/445cf19d4a9b

Added tag preview_rc2 for changeset e14d4b60b2c1

! .hgtags



From ed at camswl.com  Fri Oct 18 07:19:24 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 18 Oct 2013 14:19:24 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/langtools: Added tag
	preview_rc2 for changeset	2c196e6bfa2a
Message-ID: <20131018141937.DFFEB6252A@hg.openjdk.java.net>

Changeset: 433d7a320998
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-18 15:12 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/langtools/rev/433d7a320998

Added tag preview_rc2 for changeset 2c196e6bfa2a

! .hgtags



From ed at camswl.com  Fri Oct 18 07:20:53 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 18 Oct 2013 14:20:53 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/nashorn: Added tag
	preview_rc2 for changeset	b35e0d2e2a24
Message-ID: <20131018142055.EFA956252B@hg.openjdk.java.net>

Changeset: fbe82fef2548
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-18 15:12 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/nashorn/rev/fbe82fef2548

Added tag preview_rc2 for changeset b35e0d2e2a24

! .hgtags



From ed at camswl.com  Fri Oct 18 07:16:15 2013
From: ed at camswl.com (ed at camswl.com)
Date: Fri, 18 Oct 2013 14:16:15 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/jaxws: Added tag
	preview_rc2 for changeset	bbe175d5e634
Message-ID: <20131018141624.E244662526@hg.openjdk.java.net>

Changeset: ba76cfeddfda
Author:    Edward Nevill edward.nevill at linaro.org
Date:      2013-10-18 15:11 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/jaxws/rev/ba76cfeddfda

Added tag preview_rc2 for changeset bbe175d5e634

! .hgtags



From thuhc at yahoo.com  Sat Oct 19 08:43:33 2013
From: thuhc at yahoo.com (Cao Hoang Thu)
Date: Sat, 19 Oct 2013 08:43:33 -0700 (PDT)
Subject: [aarch64-port-dev ] Missing some classes
In-Reply-To: <1380596029.96713.YahooMailNeo@web164606.mail.gq1.yahoo.com>
References: <20130927170421.9F5D162B91@hg.openjdk.java.net>	<F8079344-8FC7-4B14-8DA3-999EABED2E3C@yahoo.com>	<1380531319.7194.4.camel@localhost.localdomain>
	<1380596029.96713.YahooMailNeo@web164606.mail.gq1.yahoo.com>
Message-ID: <1382197413.42433.YahooMailNeo@web164604.mail.gq1.yahoo.com>

This issue still happened with current source (my build:?JRE version: OpenJDK Runtime Environment (8.0) (build 1.8.0-internal-thcao_2013_10_19_21_54-b00)


Regards,
Thu Cao

________________________________
 From: Cao Hoang Thu <thuhc at yahoo.com>
To: "aarch64-port-dev at openjdk.java.net" <aarch64-port-dev at openjdk.java.net> 
Sent: Tuesday, October 1, 2013 9:53 AM
Subject: [aarch64-port-dev ] Missing some classes
 

Hi all,

I got new source (merge up to jdk8-b90):?OpenJDK Runtime Environment (build 1.8.0-internal-thcao_2013_09_28_14_23-b00)

#java -Xmx1024m -jar dacapo-9.12-bach.jar eclipse
Unzip workspace?
===== DaCapo 9.12 eclipse starting =====
Initialize workspace ...................
Index workspace .....................
Build workspace Unexpected ERROR marker(s):
org.eclipse.update.configurator:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
SiteEntry.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
org.eclipse.text:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
UndoEdit.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
org.eclipse.team.core:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
StringMatcher.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
ValidateEditChecker.java:
? ? ? ? The import java.util.Arrays cannot be resolved
ValidateEditChecker.java:
? ? ? ? Arrays cannot be resolved
ParticipantExtensionPoint.java:
? ? ? ? Arrays cannot be resolved
ParticipantExtensionPoint.java:
? ? ? ? The import java.util.Arrays cannot be resolved
TextChange.java:
? ? ? ? The import java.util.Arrays cannot be resolved
TextChange.java:
? ? ? ? Arrays cannot be resolved
TextChange.java:
? ? ? ? Arrays cannot be resolved
TextChange.java:
? ? ? ? Arrays cannot be resolved
DocumentChange.java:
? ? ? ? Cannot reduce the visibility of the inherited method from TextChange
DocumentChange.java:
? ? ? ? Cannot reduce the visibility of the inherited method from TextChange
DocumentChange.java:
? ? ? ? Cannot reduce the visibility of the inherited method from TextChange
DocumentChange.java:
? ? ? ? Cannot reduce the visibility of the inherited method from TextChange
org.eclipse.jdt.core:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
JDTCompilerAdapter.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
org.eclipse.core.variables:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
StringSubstitutionEngine.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
org.eclipse.core.runtime.compatibility:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
PluginActivator.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
org.eclipse.core.runtime:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
MultiRule.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
org.eclipse.core.resources:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
ElementTreeIterator.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
org.eclipse.core.filebuffers:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
ResourceTextFileBuffer.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
org.eclipse.core.expressions:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
TypeExtensionManager.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
org.eclipse.ant.core:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
AntRunner.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files
org.apache.lucene:
? ? ? ? The project was not built since its build path is incomplete. Cannot find the class file for java.lang.CharSequence. Fix the build path then try building this project
TokenMgrError.java:
? ? ? ? The type java.lang.CharSequence cannot be resolved. It is indirectly referenced from required .class files

Old-version:?OpenJDK Runtime Environment (build 1.8.0-internal-thcao_2013_09_23_09_46-b00)
#java -Xmx1024m -jar dacapo-9.12-bach.jar eclipse
Unzip workspace?
===== DaCapo 9.12 eclipse starting =====
Initialize workspace ...................
Index workspace .....................
Build workspace?
Search .. 4,207 references for default constructor in workspace
? ? ? ?.. 1,957 references for method 'equals' in workspace
Type hierarchy tests?
AST tests?
Completion tests .........
Format tests ..............
Model tests ................
===== DaCapo 9.12 eclipse PASSED in 72643 msec =====
Delete workspace?

Regards,

Thu Cao

From adinn at redhat.com  Mon Oct 21 03:04:34 2013
From: adinn at redhat.com (adinn at redhat.com)
Date: Mon, 21 Oct 2013 10:04:34 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: 2 new changesets
Message-ID: <20131021100513.91C60625AE@hg.openjdk.java.net>

Changeset: ae24d902de20
Author:    adinn
Date:      2013-10-21 11:00 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/ae24d902de20

remove erroneous match for FP register

! src/cpu/aarch64/vm/aarch64.ad

Changeset: ce478bc4a9a5
Author:    adinn
Date:      2013-10-21 11:03 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/ce478bc4a9a5

Merge

! src/cpu/aarch64/vm/aarch64.ad



From trivikram at iitj.ac.in  Wed Oct 23 23:24:13 2013
From: trivikram at iitj.ac.in (Trivikram Chowdary)
Date: Thu, 24 Oct 2013 11:54:13 +0530
Subject: [aarch64-port-dev ] Porting Material
Message-ID: <CAK-ChhueoFc1si=ZrR9_DJY02r7EJN2Rav5QFJbnkSBRM4Mf6Q@mail.gmail.com>

Can anyone give me or suggest some reading material to start porting of JVM?

Thank You.


From aph at redhat.com  Thu Oct 24 03:04:55 2013
From: aph at redhat.com (Andrew Haley)
Date: Thu, 24 Oct 2013 11:04:55 +0100
Subject: [aarch64-port-dev ] Porting Material
In-Reply-To: <CAK-ChhueoFc1si=ZrR9_DJY02r7EJN2Rav5QFJbnkSBRM4Mf6Q@mail.gmail.com>
References: <CAK-ChhueoFc1si=ZrR9_DJY02r7EJN2Rav5QFJbnkSBRM4Mf6Q@mail.gmail.com>
Message-ID: <5268F0C7.6060306@redhat.com>

On 10/24/2013 07:24 AM, Trivikram Chowdary wrote:
> Can anyone give me or suggest some reading material to start porting of JVM?

https://wiki.openjdk.java.net/display/HotSpot/Main

Andrew.



From aph at redhat.com  Fri Oct 25 01:32:24 2013
From: aph at redhat.com (Andrew Haley)
Date: Fri, 25 Oct 2013 09:32:24 +0100
Subject: [aarch64-port-dev ] Ideal Graph Visualizer
Message-ID: <526A2C98.5060106@redhat.com>

This is a fairly nice way to browse C2 Ideal Graphs.

Its page is at http://ssw.jku.at/General/Staff/TW/igv.html

Download link is at http://ssw.jku.at/General/Staff/PH/igv_latest.zip

There is a version in the HotSpot tree but it doesn't work.

Andrew.


From bernhard.urban at jku.at  Fri Oct 25 01:53:48 2013
From: bernhard.urban at jku.at (Bernhard Urban)
Date: Fri, 25 Oct 2013 10:53:48 +0200
Subject: [aarch64-port-dev ] Ideal Graph Visualizer
Message-ID: <CAAr_hs7qdsjDf37vOAD5o9JB7VjLja7nb1ciKfkydrjNypVCfQ@mail.gmail.com>

you find a slightly more recent version in the graal repository [1],
however with graal specific modifications.  So I don't know if the version
from graal will still work with C2, but I think it's worth a try.


Bernhard

[1] http://hg.openjdk.java.net/graal/graal/summary


On Fri, Oct 25, 2013 at 10:32 AM, Andrew Haley <aph at redhat.com> wrote:

> This is a fairly nice way to browse C2 Ideal Graphs.
>
> Its page is at http://ssw.jku.at/General/Staff/TW/igv.html
>
> Download link is at http://ssw.jku.at/General/Staff/PH/igv_latest.zip
>
> There is a version in the HotSpot tree but it doesn't work.
>
> Andrew.
>


From aph at redhat.com  Fri Oct 25 01:57:10 2013
From: aph at redhat.com (Andrew Haley)
Date: Fri, 25 Oct 2013 09:57:10 +0100
Subject: [aarch64-port-dev ] Ideal Graph Visualizer
In-Reply-To: <CAAr_hs7qdsjDf37vOAD5o9JB7VjLja7nb1ciKfkydrjNypVCfQ@mail.gmail.com>
References: <CAAr_hs7qdsjDf37vOAD5o9JB7VjLja7nb1ciKfkydrjNypVCfQ@mail.gmail.com>
Message-ID: <526A3266.9010907@redhat.com>

On 10/25/2013 09:53 AM, Bernhard Urban wrote:
> you find a slightly more recent version in the graal repository [1],
> however with graal specific modifications.  So I don't know if the version
> from graal will still work with C2, but I think it's worth a try.

> [1] http://hg.openjdk.java.net/graal/graal/summary

I've tried it, and it's fine.  It's not obviously better than the
downloaded version, though, and it has to be built.

Andrew.



From aph at redhat.com  Fri Oct 25 09:37:21 2013
From: aph at redhat.com (Andrew Haley)
Date: Fri, 25 Oct 2013 17:37:21 +0100
Subject: [aarch64-port-dev ] A rather large patch to aarch64.ad
Message-ID: <526A9E41.3080002@redhat.com>

This is a substantial rewrite of the AArch64 patterns for arithmetic
and memory access.  The idea is to make use of the more complex
AArch64 instructions wherever possible, so that e.g. we use UBFX
rather than a series of shifts and masks, and LDR Xd, [Xn, Wn, sxtw #3]
for array loads.

The patch itself is hard to follow because of the reorganization I had
to do.  I apologize for that.  However, the resulting aarch64.ad isn't
so bad.

I have checked many of these patterns and HotSpot really does generate
the fast AArch64 instructions.

Comments?

Andrew.


diff -ur hs-tmp/src/cpu/aarch64/vm/aarch64.ad /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/aarch64.ad
--- hs-tmp/src/cpu/aarch64/vm/aarch64.ad	2013-10-25 16:34:20.464632075 +0100
+++ /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/aarch64.ad	2013-10-25 16:27:40.436100824 +0100
@@ -1772,8 +1772,63 @@
     }									\
     __ INSN(REG, SCRATCH);						\
   }
+
+typedef void (MacroAssembler::* mem_insn)(Register Rt, const Address &adr);
+typedef void (MacroAssembler::* mem_float_insn)(FloatRegister Rt, const Address &adr);
+
+  // Used for all non-volatile memory accesses.  The use of
+  // $mem->opcode() to discover whether this pattern uses sign-extended
+  // offsets is something of a kludge.
+  static void loadStore(MacroAssembler masm, mem_insn insn,
+			 Register reg, int opcode,
+			 Register base, int index, int size, int disp)
+  {
+    Address::extend scale;
+    if (opcode == INDINDEXSCALEDOFFSETI2L
+	|| opcode == INDINDEXSCALEDI2L)
+      scale = Address::sxtw(size);
+    else
+      scale = Address::lsl(size);
+
+    if (index == -1) {
+      (masm.*insn)(reg, Address(base, disp));
+    } else {
+      if (disp == 0) {
+	(masm.*insn)(reg, Address(base, as_Register(index), scale));
+      } else {
+	masm.lea(rscratch1, Address(base, disp));
+	(masm.*insn)(reg, Address(rscratch1, as_Register(index), scale));
+      }
+    }
+  }
+
+  static void loadStore(MacroAssembler masm, mem_float_insn insn,
+			 FloatRegister reg, int opcode,
+			 Register base, int index, int size, int disp)
+  {
+    Address::extend scale;
+    if (opcode == INDINDEXSCALEDOFFSETI2L
+	|| opcode == INDINDEXSCALEDI2L)
+      scale = Address::sxtw(size);
+    else
+      scale = Address::lsl(size);
+
+    if (index == -1) {
+      (masm.*insn)(reg, Address(base, disp));
+    } else {
+      if (disp == 0) {
+	(masm.*insn)(reg, Address(base, as_Register(index), scale));
+      } else {
+	masm.lea(rscratch1, Address(base, disp));
+	(masm.*insn)(reg, Address(rscratch1, as_Register(index), scale));
+      }
+    }
+  }
+
 %}

+
+
 //----------ENCODING BLOCK-----------------------------------------------------
 // This block specifies the encoding classes used by the compiler to
 // output byte streams.  Encoding classes are parameterized macros
@@ -1815,452 +1870,184 @@
     __ unimplemented("C2 catch all");
   %}

+  // BEGIN Non-volatile memory access
+
   enc_class aarch64_enc_ldrsbw(iRegI dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrsbw(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrsbw(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrsbw(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsbw, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

-  enc_class aarch64_enc_ldrsb(iRegL dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
+  enc_class aarch64_enc_ldrsb(iRegI dst, memory mem) %{
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrsb(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrsb(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrsb(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsb, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

-  enc_class aarch64_enc_ldrbw(iRegI dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
+  enc_class aarch64_enc_ldrb(iRegI dst, memory mem) %{
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrb(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrb(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrb(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrb, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_ldrb(iRegL dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrb(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrb(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrb(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrb, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_ldrshw(iRegI dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrshw(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrshw(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrshw(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrshw, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

-  enc_class aarch64_enc_ldrsh(iRegL dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
+  enc_class aarch64_enc_ldrsh(iRegI dst, memory mem) %{
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrsh(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrsh(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrsh(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsh, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

-  enc_class aarch64_enc_ldrhw(iRegI dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
+  enc_class aarch64_enc_ldrh(iRegI dst, memory mem) %{
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrh(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrh(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrh(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrh, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_ldrh(iRegL dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrh(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrh(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrh(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrh, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_ldrw(iRegI dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrw(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrw(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrw(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_ldrw(iRegL dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrw(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrw(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrw(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_ldrsw(iRegL dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrsw(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrsw(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrsw(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrsw, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_ldr(iRegL dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     Register dst_reg = as_Register($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldr(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldr(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldr(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_ldrs(vRegF dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     FloatRegister dst_reg = as_FloatRegister($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrs(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrs(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrs(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrs, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_ldrd(vRegD dst, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     FloatRegister dst_reg = as_FloatRegister($dst$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ ldrd(dst_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ ldrd(dst_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ ldrd(dst_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrd, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_strb(iRegI src, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     Register src_reg = as_Register($src$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ strb(src_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ strb(src_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ strb(src_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::strb, src_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_strb0(memory mem) %{
     MacroAssembler _masm(&cbuf);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ strb(zr, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ strb(zr, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ strb(zr, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(_masm, &MacroAssembler::strb, zr, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_strh(iRegI src, memory mem) %{
-    MacroAssembler _masm(&cbuf);
     Register src_reg = as_Register($src$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ strh(src_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ strh(src_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ strh(src_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::strh, src_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_strh0(memory mem) %{
     MacroAssembler _masm(&cbuf);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ strh(zr, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ strh(zr, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ strh(zr, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(_masm, &MacroAssembler::strh, zr, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_strw(iRegI src, memory mem) %{
+    Register src_reg = as_Register($src$$reg);
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::strw, src_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
+  %}
+
+  enc_class aarch64_enc_strw0(memory mem) %{
     MacroAssembler _masm(&cbuf);
+    loadStore(_masm, &MacroAssembler::strw, zr, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
+  %}
+
+  enc_class aarch64_enc_str(iRegL src, memory mem) %{
     Register src_reg = as_Register($src$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ strw(src_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ strw(src_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ strw(src_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
-  %}
-
-  enc_class aarch64_enc_strw0(memory mem) %{
-    MacroAssembler _masm(&cbuf);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ strw(zr, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ strw(zr, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ strw(zr, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
-  %}
-
-  enc_class aarch64_enc_str(iRegL src, memory mem) %{
-    MacroAssembler _masm(&cbuf);
-    Register src_reg = as_Register($src$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-
     // we sometimes get asked to store the stack pointer into the
     // current thread -- we cannot do that directly on AArch64
-
     if (src_reg == r31_sp) {
-      assert(base == rthread, "unexpected store for sp");
+      MacroAssembler _masm(&cbuf);
+      assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
       __ mov(rscratch2, sp);
       src_reg = rscratch2;
     }
-    if (index == -1) {
-      __ str(src_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ str(src_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ str(src_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

   enc_class aarch64_enc_str0(memory mem) %{
     MacroAssembler _masm(&cbuf);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
+    loadStore(_masm, &MacroAssembler::str, zr, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
+  %}

-    if (index == -1) {
-      __ str(zr, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ str(zr, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ str(zr, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
+  enc_class aarch64_enc_strs(vRegF src, memory mem) %{
+    FloatRegister src_reg = as_FloatRegister($src$$reg);
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::strs, src_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
+  %}
+
+  enc_class aarch64_enc_strd(vRegD src, memory mem) %{
+    FloatRegister src_reg = as_FloatRegister($src$$reg);
+    loadStore(MacroAssembler(&cbuf), &MacroAssembler::strd, src_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
   %}

+  enc_class aarch64_enc_strw_immn(immN src, memory mem) %{
+    MacroAssembler _masm(&cbuf);
+    address con = (address)$src$$constant;
+    // need to do this the hard way until we can manage relocs
+    // for 32 bit constants
+    __ movoop(rscratch2, (jobject)con);
+    if (con) __ encode_heap_oop_not_null(rscratch2);
+    loadStore(_masm, &MacroAssembler::strw, rscratch2, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
+  %}
+
+  enc_class aarch64_enc_strw_immnk(immN src, memory mem) %{
+    MacroAssembler _masm(&cbuf);
+    address con = (address)$src$$constant;
+    // need to do this the hard way until we can manage relocs
+    // for 32 bit constants
+    __ movoop(rscratch2, (jobject)con);
+    __ encode_klass_not_null(rscratch2);
+    loadStore(_masm, &MacroAssembler::strw, rscratch2, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
+  %}
+
+  // END Non-volatile memory access
+
   // this encoding writes the address of the first instruction in the
   // call sequence for the runtime call into the anchor pc slot. this
   // address allows the runtime to i) locate the code buffer for the
@@ -2325,94 +2112,6 @@
     __ str(rscratch1, Address(rthread, field_offset));
   %}

-  enc_class aarch64_enc_strs(vRegF src, memory mem) %{
-    MacroAssembler _masm(&cbuf);
-    FloatRegister src_reg = as_FloatRegister($src$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ strs(src_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ strs(src_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ strs(src_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
-  %}
-
-  enc_class aarch64_enc_strd(vRegD src, memory mem) %{
-    MacroAssembler _masm(&cbuf);
-    FloatRegister src_reg = as_FloatRegister($src$$reg);
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    if (index == -1) {
-      __ strd(src_reg, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ strd(src_reg, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ strd(src_reg, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
-  %}
-
-  enc_class aarch64_enc_strw_immn(immN src, memory mem) %{
-    MacroAssembler _masm(&cbuf);
-    address con = (address)$src$$constant;
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    // need to do this the hard way until we can manage relocs
-    // for 32 bit constants
-    __ movoop(rscratch2, (jobject)con);
-    if (con) __ encode_heap_oop_not_null(rscratch2);
-    if (index == -1) {
-      __ strw(rscratch2, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ strw(rscratch2, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ strw(rscratch2, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
-  %}
-
-  enc_class aarch64_enc_strw_immnk(immN src, memory mem) %{
-    MacroAssembler _masm(&cbuf);
-    address con = (address)$src$$constant;
-    Register base = as_Register($mem$$base);
-    int index = $mem$$index;
-    int scale = $mem$$scale;
-    int disp = $mem$$disp;
-    // need to do this the hard way until we can manage relocs
-    // for 32 bit constants
-    __ movoop(rscratch2, (jobject)con);
-    __ encode_klass_not_null(rscratch2);
-    if (index == -1) {
-      __ strw(rscratch2, Address(base, disp));
-    } else {
-      Register index_reg = as_Register(index);
-      if (disp == 0) {
-        __ strw(rscratch2, Address(base, index_reg, Address::lsl(scale)));
-      } else {
-        __ lea(rscratch1, Address(base, disp));
-	__ strw(rscratch2, Address(rscratch1, index_reg, Address::lsl(scale)));
-      }
-    }
-  %}
-
   // volatile loads and stores

   enc_class aarch64_enc_ldarsbw(iRegI dst, memory mem) %{
@@ -3719,103 +3418,99 @@
   interface(CONST_INTER);
 %}

-// Scale values for scaled offset addressing modes (up to long but not quad)
-operand immIScale()
+operand immI_8()
 %{
-  predicate(0 <= n->get_int() && (n->get_int() <= 3));
+  predicate(n->get_int() == 8);
   match(ConI);

+  op_cost(0);
   format %{ %}
   interface(CONST_INTER);
 %}

-// 26 bit signed offset -- for pc-relative branches
-operand immI26()
+operand immI_16()
 %{
-  predicate(((-(1 << 25)) <= n->get_int()) && (n->get_int() < (1 << 25)));
+  predicate(n->get_int() == 16);
   match(ConI);

+  op_cost(0);
   format %{ %}
   interface(CONST_INTER);
 %}

-// 19 bit signed offset -- for pc-relative loads
-operand immI19()
+operand immI_24()
 %{
-  predicate(((-(1 << 18)) <= n->get_int()) && (n->get_int() < (1 << 18)));
+  predicate(n->get_int() == 24);
   match(ConI);

+  op_cost(0);
   format %{ %}
   interface(CONST_INTER);
 %}

-// 12 bit unsigned offset -- for base plus immediate loads
-operand immIU12()
+operand immI_32()
 %{
-  predicate((0 <= n->get_int()) && (n->get_int() < (1 << 12)));
+  predicate(n->get_int() == 32);
   match(ConI);

+  op_cost(0);
   format %{ %}
   interface(CONST_INTER);
 %}

-// Valid 9 bit unsigned offset
-operand immI9()
+operand immI_48()
 %{
-  predicate(((-(1 << 8)) <= n->get_int()) && (n->get_int() < (1 << 8)));
+  predicate(n->get_int() == 48);
   match(ConI);

+  op_cost(0);
   format %{ %}
   interface(CONST_INTER);
 %}

-// 32 bit integer valid for add sub immediate
-operand immIAddSub()
+operand immI_56()
 %{
-  predicate(Assembler::operand_valid_for_add_sub_immediate((long)n->get_int()));
+  predicate(n->get_int() == 56);
   match(ConI);
+
   op_cost(0);
   format %{ %}
   interface(CONST_INTER);
 %}

-// 32 bit unsigned integer valid for logical immediate
-// TODO -- check this is right when e.g the mask is 0x80000000
-operand immILog()
+operand immI_255()
 %{
-  predicate(Assembler::operand_valid_for_logical_immediate(true, (unsigned long)n->get_int()));
+  predicate(n->get_int() == 255);
   match(ConI);
+
   op_cost(0);
   format %{ %}
   interface(CONST_INTER);
 %}

-// Integer operands 64 bit
-// 64 bit immediate
-operand immL()
+operand immI_65535()
 %{
-  match(ConL);
+  predicate(n->get_int() == 65535);
+  match(ConI);

-  op_cost(20);
+  op_cost(0);
   format %{ %}
   interface(CONST_INTER);
 %}

-// 64 bit zero
-operand immL0()
+operand immL_255()
 %{
-  predicate(n->get_long() == 0);
-  match(ConL);
+  predicate(n->get_int() == 255);
+  match(ConI);

   op_cost(0);
   format %{ %}
   interface(CONST_INTER);
 %}

-// 64 bit unit increment
-operand immL_1()
+operand immL_65535()
 %{
-  predicate(n->get_long() == 1);
+  predicate(n->get_long() == 65535L);
   match(ConL);

   op_cost(0);
@@ -3823,10 +3518,9 @@
   interface(CONST_INTER);
 %}

-// 64 bit unit decrement
-operand immL_M1()
+operand immL_4294967295()
 %{
-  predicate(n->get_long() == 1);
+  predicate(n->get_long() == 4294967295L);
   match(ConL);

   op_cost(0);
@@ -3834,12 +3528,10 @@
   interface(CONST_INTER);
 %}

-// 32 bit offset of pc in thread anchor
-
-operand immL_pc_off()
+operand immL_bitmask()
 %{
-  predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
-                             in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
+  predicate(((n->get_long() & 0xc000000000000000l) == 0)
+	    && is_power_of_2(n->get_long() + 1));
   match(ConL);

   op_cost(0);
@@ -3847,61 +3539,200 @@
   interface(CONST_INTER);
 %}

-// 64 bit integer valid for add sub immediate
-operand immLAddSub()
+operand immI_bitmask()
 %{
-  predicate(Assembler::operand_valid_for_add_sub_immediate(n->get_long()));
-  match(ConL);
+  predicate(((n->get_int() & 0xc0000000) == 0)
+	    && is_power_of_2(n->get_int() + 1));
+  match(ConI);
+
   op_cost(0);
   format %{ %}
   interface(CONST_INTER);
 %}

-// 64 bit integer valid for logical immediate
-operand immLLog()
+// Scale values for scaled offset addressing modes (up to long but not quad)
+operand immIScale()
 %{
-  predicate(Assembler::operand_valid_for_logical_immediate(true, (unsigned long)n->get_long()));
-  match(ConL);
-  op_cost(0);
+  predicate(0 <= n->get_int() && (n->get_int() <= 3));
+  match(ConI);
+
   format %{ %}
   interface(CONST_INTER);
 %}

-// Long Immediate: low 32-bit mask
-operand immL_32bits()
+// 26 bit signed offset -- for pc-relative branches
+operand immI26()
 %{
-  predicate(n->get_long() == 0xFFFFFFFFL);
-  match(ConL);
-  op_cost(0);
+  predicate(((-(1 << 25)) <= n->get_int()) && (n->get_int() < (1 << 25)));
+  match(ConI);
+
   format %{ %}
   interface(CONST_INTER);
 %}

-// Pointer operands
-// Pointer Immediate
-operand immP()
+// 19 bit signed offset -- for pc-relative loads
+operand immI19()
 %{
-  match(ConP);
+  predicate(((-(1 << 18)) <= n->get_int()) && (n->get_int() < (1 << 18)));
+  match(ConI);

-  op_cost(10);
   format %{ %}
   interface(CONST_INTER);
 %}

-// NULL Pointer Immediate
-operand immP0()
+// 12 bit unsigned offset -- for base plus immediate loads
+operand immIU12()
 %{
-  predicate(n->get_ptr() == 0);
-  match(ConP);
+  predicate((0 <= n->get_int()) && (n->get_int() < (1 << 12)));
+  match(ConI);

-  op_cost(5);
   format %{ %}
   interface(CONST_INTER);
 %}

-// Pointer Immediate One
-// this is used in object initialization (initial object header)
-operand immP_1()
+// Valid 9 bit unsigned offset
+operand immI9()
+%{
+  predicate(((-(1 << 8)) <= n->get_int()) && (n->get_int() < (1 << 8)));
+  match(ConI);
+
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// 32 bit integer valid for add sub immediate
+operand immIAddSub()
+%{
+  predicate(Assembler::operand_valid_for_add_sub_immediate((long)n->get_int()));
+  match(ConI);
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// 32 bit unsigned integer valid for logical immediate
+// TODO -- check this is right when e.g the mask is 0x80000000
+operand immILog()
+%{
+  predicate(Assembler::operand_valid_for_logical_immediate(true, (unsigned long)n->get_int()));
+  match(ConI);
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// Integer operands 64 bit
+// 64 bit immediate
+operand immL()
+%{
+  match(ConL);
+
+  op_cost(20);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// 64 bit zero
+operand immL0()
+%{
+  predicate(n->get_long() == 0);
+  match(ConL);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// 64 bit unit increment
+operand immL_1()
+%{
+  predicate(n->get_long() == 1);
+  match(ConL);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// 64 bit unit decrement
+operand immL_M1()
+%{
+  predicate(n->get_long() == -1);
+  match(ConL);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// 32 bit offset of pc in thread anchor
+
+operand immL_pc_off()
+%{
+  predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
+                             in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
+  match(ConL);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// 64 bit integer valid for add sub immediate
+operand immLAddSub()
+%{
+  predicate(Assembler::operand_valid_for_add_sub_immediate(n->get_long()));
+  match(ConL);
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// 64 bit integer valid for logical immediate
+operand immLLog()
+%{
+  predicate(Assembler::operand_valid_for_logical_immediate(true, (unsigned long)n->get_long()));
+  match(ConL);
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// Long Immediate: low 32-bit mask
+operand immL_32bits()
+%{
+  predicate(n->get_long() == 0xFFFFFFFFL);
+  match(ConL);
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// Pointer operands
+// Pointer Immediate
+operand immP()
+%{
+  match(ConP);
+
+  op_cost(10);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// NULL Pointer Immediate
+operand immP0()
+%{
+  predicate(n->get_ptr() == 0);
+  match(ConP);
+
+  op_cost(5);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// Pointer Immediate One
+// this is used in object initialization (initial object header)
+operand immP_1()
 %{
   predicate(n->get_ptr() == 1);
   match(ConP);
@@ -4279,15 +4110,11 @@
   %}
 %}

-// TODO this is the pattern used by x86/ppc but for aarch64 extended
-// reg we probably want to match (LShiftI ireg scale) need to see if
-// the ideal code will ever generate an LShiftI
-
 operand indIndexScaledOffsetI(iRegP reg, iRegL lreg, immIScale scale, immIAddSub off)
 %{
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP (AddP reg (LShiftL lreg scale)) off);
-  op_cost(DEFAULT_COST_LOW);
+  op_cost(DEFAULT_COST);
   format %{ "$reg, $lreg lsl($scale), $off" %}
   interface(MEMORY_INTER) %{
     base($reg);
@@ -4301,7 +4128,7 @@
 %{
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP (AddP reg (LShiftL lreg scale)) off);
-  op_cost(DEFAULT_COST_LOW);
+  op_cost(DEFAULT_COST);
   format %{ "$reg, $lreg lsl($scale), $off" %}
   interface(MEMORY_INTER) %{
     base($reg);
@@ -4311,6 +4138,34 @@
   %}
 %}

+operand indIndexScaledOffsetI2L(iRegP reg, iRegI ireg, immIScale scale, immLAddSub off)
+%{
+  constraint(ALLOC_IN_RC(ptr_reg));
+  match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off);
+  op_cost(DEFAULT_COST);
+  format %{ "$reg, $ireg sxtw($scale), $off I2L" %}
+  interface(MEMORY_INTER) %{
+    base($reg);
+    index($ireg);
+    scale($scale);
+    disp($off);
+  %}
+%}
+
+operand indIndexScaledI2L(iRegP reg, iRegI ireg, immIScale scale)
+%{
+  constraint(ALLOC_IN_RC(ptr_reg));
+  match(AddP reg (LShiftL (ConvI2L ireg) scale));
+  op_cost(0);
+  format %{ "$reg, $ireg sxtw($scale), 0, I2L" %}
+  interface(MEMORY_INTER) %{
+    base($reg);
+    index($ireg);
+    scale($scale);
+    disp(0x0);
+  %}
+%}
+
 operand indIndexScaled(iRegP reg, iRegL lreg, immIScale scale)
 %{
   constraint(ALLOC_IN_RC(ptr_reg));
@@ -4329,7 +4184,7 @@
 %{
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP reg lreg);
-  op_cost(40);
+  op_cost(0);
   format %{ "$reg, $lreg" %}
   interface(MEMORY_INTER) %{
     base($reg);
@@ -4530,7 +4385,7 @@
 // memory is used to define read/write location for load/store
 // instruction defs. we can turn a memory op into an Address

-opclass memory(indirect, indIndexScaledOffsetI,  indIndexScaledOffsetL, indIndexScaled, indIndex, indOffI, indOffL);
+opclass memory(indirect, indIndexScaledOffsetI,  indIndexScaledOffsetL, indIndexScaledOffsetI2L, indIndexScaled, indIndexScaledI2L, indIndex, indOffI, indOffL);

 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
 // operations. it allows the src to be either an iRegI or a (ConvL2I
@@ -4702,7 +4557,7 @@
   ins_cost(MEMORY_REF_COST);
   format %{ "ldrbw  $dst, $mem\t# byte" %}

-  ins_encode(aarch64_enc_ldrbw(dst, mem));
+  ins_encode(aarch64_enc_ldrb(dst, mem));

   ins_pipe(pipe_class_memory);
 %}
@@ -4756,9 +4611,9 @@
   predicate(!((MemNode*)n)->is_volatile());

   ins_cost(MEMORY_REF_COST);
-  format %{ "ldrhw  $dst, $mem\t# short" %}
+  format %{ "ldrh  $dst, $mem\t# short" %}

-  ins_encode(aarch64_enc_ldrhw(dst, mem));
+  ins_encode(aarch64_enc_ldrh(dst, mem));

   ins_pipe(pipe_class_memory);
 %}
@@ -5916,6 +5771,7 @@
 instruct castX2P(iRegPNoSp dst, iRegL src) %{
   match(Set dst (CastX2P src));

+  ins_cost(DEFAULT_COST);
   format %{ "mov $dst, $src\t# long -> ptr" %}

   ins_encode %{
@@ -5930,6 +5786,7 @@
 instruct castP2X(iRegLNoSp dst, iRegP src) %{
   match(Set dst (CastP2X src));

+  ins_cost(DEFAULT_COST);
   format %{ "mov $dst, $src\t# ptr -> long" %}

   ins_encode %{
@@ -5945,6 +5802,7 @@
 instruct convP2I(iRegINoSp dst, iRegP src) %{
   match(Set dst (ConvL2I (CastP2X src)));

+  ins_cost(DEFAULT_COST);
   format %{ "movw $dst, $src\t# ptr -> int" %}
   ins_encode %{
     __ movw($dst$$Register, $src$$Register);
@@ -5960,6 +5818,7 @@
   predicate(Universe::narrow_oop_shift() == 0);
   match(Set dst (ConvL2I (CastP2X (DecodeN src))));

+  ins_cost(DEFAULT_COST);
   format %{ "mov dst, $src\t# compressed ptr -> int" %}
   ins_encode %{
     __ movw($dst$$Register, $src$$Register);
@@ -5973,6 +5832,7 @@
 instruct encodeHeapOop(iRegNNoSp dst, iRegP src, rFlagsReg cr) %{
   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
   match(Set dst (EncodeP src));
+  ins_cost(DEFAULT_COST * 3);
   effect(KILL cr);
   format %{ "encode_heap_oop $dst, $src" %}
   ins_encode %{
@@ -5990,6 +5850,7 @@
   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
   match(Set dst (EncodeP src));
   effect(KILL cr);
+  ins_cost(DEFAULT_COST * 3);
   format %{ "encode_heap_oop_not_null $dst, $src" %}
   ins_encode %{
     __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
@@ -6002,6 +5863,7 @@
             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
   match(Set dst (DecodeN src));
   effect(KILL cr);
+  ins_cost(DEFAULT_COST * 3);
   format %{ "decode_heap_oop $dst, $src" %}
   ins_encode %{
     Register s = $src$$Register;
@@ -6021,6 +5883,7 @@
             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
   match(Set dst (DecodeN src));
   effect(KILL cr);
+  ins_cost(DEFAULT_COST * 3);
   format %{ "decode_heap_oop_not_null $dst, $src" %}
   ins_encode %{
     Register s = $src$$Register;
@@ -6041,6 +5904,7 @@
 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
   match(Set dst (EncodePKlass src));

+  ins_cost(DEFAULT_COST * 3);
   format %{ "encode_klass_not_null $dst,$src" %}

   ins_encode %{
@@ -6055,6 +5919,7 @@
 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src) %{
   match(Set dst (DecodeNKlass src));

+  ins_cost(DEFAULT_COST * 3);
   format %{ "decode_klass_not_null $dst,$src" %}

   ins_encode %{
@@ -6298,1110 +6163,2650 @@
 // which throws a ShouldNotHappen. So, we have to provide two flavours
 // of each rule, one for a cmpOp and a second for a cmpOpU (sigh).

-instruct cmovI_reg_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegI src1, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
+instruct cmovI_reg_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegI src1, iRegI src2) %{
+  match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, int"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             as_Register($src2$$reg),
+             as_Register($src1$$reg),
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUI_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegI src1, iRegI src2) %{
+  match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, $src2, $src1 $cmp\t# unsigned, int"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             as_Register($src2$$reg),
+             as_Register($src1$$reg),
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// special cases where one arg is zero
+
+// n.b. this is selected in preference to the rule above because it
+// avoids loading constant 0 into a source register
+
+// TODO
+// we ought only to be able to cull one of these variants as the ideal
+// transforms ought always to order the zero consistently (to left/right?)
+
+instruct cmovI_zero_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, iRegI src2) %{
+  match(Set dst (CMoveI (Binary cmp cr) (Binary zero src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, $src2, zr $cmp\t# signed, int"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             as_Register($src2$$reg),
+             zr,
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUI_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, iRegI src2) %{
+  match(Set dst (CMoveI (Binary cmp cr) (Binary zero src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, $src2, zr $cmp\t# unsigned, int"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             as_Register($src2$$reg),
+             zr,
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovI_reg_zero(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegI src1, immI0 zero) %{
+  match(Set dst (CMoveI (Binary cmp cr) (Binary src1 zero)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, zr, $src1 $cmp\t# signed, int"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             zr,
+             as_Register($src1$$reg),
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUI_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegI src1, immI0 zero) %{
+  match(Set dst (CMoveI (Binary cmp cr) (Binary src1 zero)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, zr, $src1 $cmp\t# unsigned, int"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             zr,
+             as_Register($src1$$reg),
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// special case for creating a boolean 0 or 1
+
+// n.b. this is selected in preference to the rule above because it
+// avoids loading constants 0 and 1 into a source register
+
+instruct cmovI_reg_zero_one(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
+  match(Set dst (CMoveI (Binary cmp cr) (Binary one zero)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csincw $dst, zr, zr $cmp\t# signed, int"  %}
+
+  ins_encode %{
+    // equivalently
+    // cset(as_Register($dst$$reg),
+    //      negate_condition((Assembler::Condition)$cmp$$cmpcode));
+    __ csincw(as_Register($dst$$reg),
+	     zr,
+	     zr,
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUI_reg_zero_one(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
+  match(Set dst (CMoveI (Binary cmp cr) (Binary one zero)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csincw $dst, zr, zr $cmp\t# unsigned, int"  %}
+
+  ins_encode %{
+    // equivalently
+    // cset(as_Register($dst$$reg),
+    //      negate_condition((Assembler::Condition)$cmp$$cmpcode));
+    __ csincw(as_Register($dst$$reg),
+	     zr,
+	     zr,
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovL_reg_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
+  match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, $src2, $src1 $cmp\t# signed, long"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            as_Register($src2$$reg),
+            as_Register($src1$$reg),
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUL_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
+  match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, long"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            as_Register($src2$$reg),
+            as_Register($src1$$reg),
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// special cases where one arg is zero
+
+instruct cmovL_reg_zero(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src1, immL0 zero) %{
+  match(Set dst (CMoveL (Binary cmp cr) (Binary src1 zero)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, zr, $src1 $cmp\t# signed, long"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            zr,
+            as_Register($src1$$reg),
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUL_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, immL0 zero) %{
+  match(Set dst (CMoveL (Binary cmp cr) (Binary src1 zero)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, zr, $src1 $cmp\t# unsigned, long"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            zr,
+            as_Register($src1$$reg),
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovL_zero_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, immL0 zero, iRegL src2) %{
+  match(Set dst (CMoveL (Binary cmp cr) (Binary zero src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, $src2, zr $cmp\t# signed, long"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            as_Register($src2$$reg),
+            zr,
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUL_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, immL0 zero, iRegL src2) %{
+  match(Set dst (CMoveL (Binary cmp cr) (Binary zero src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, $src2, zr $cmp\t# unsigned, long"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            as_Register($src2$$reg),
+            zr,
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovP_reg_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
+  match(Set dst (CMoveP (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, $src2, $src1 $cmp\t# signed, ptr"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            as_Register($src2$$reg),
+            as_Register($src1$$reg),
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUP_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
+  match(Set dst (CMoveP (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, ptr"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            as_Register($src2$$reg),
+            as_Register($src1$$reg),
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// special cases where one arg is zero
+
+instruct cmovP_reg_zero(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, iRegP src1, immP0 zero) %{
+  match(Set dst (CMoveP (Binary cmp cr) (Binary src1 zero)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, zr, $src1 $cmp\t# signed, ptr"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            zr,
+            as_Register($src1$$reg),
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUP_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src1, immP0 zero) %{
+  match(Set dst (CMoveP (Binary cmp cr) (Binary src1 zero)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, zr, $src1 $cmp\t# unsigned, ptr"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            zr,
+            as_Register($src1$$reg),
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovP_zero_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, immP0 zero, iRegP src2) %{
+  match(Set dst (CMoveP (Binary cmp cr) (Binary zero src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, $src2, zr $cmp\t# signed, ptr"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            as_Register($src2$$reg),
+            zr,
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUP_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, immP0 zero, iRegP src2) %{
+  match(Set dst (CMoveP (Binary cmp cr) (Binary zero src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "csel $dst, $src2, zr $cmp\t# unsigned, ptr"  %}
+
+  ins_encode %{
+    __ csel(as_Register($dst$$reg),
+            as_Register($src2$$reg),
+            zr,
+            (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovN_reg_reg(cmpOp cmp, rFlagsReg cr, iRegN dst, iRegN src1, iRegN src2) %{
+  match(Set dst (CMoveN (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, compressed ptr"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             as_Register($src2$$reg),
+             as_Register($src1$$reg),
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUN_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegN dst, iRegN src1, iRegN src2) %{
+  match(Set dst (CMoveN (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, compressed ptr"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             as_Register($src2$$reg),
+             as_Register($src1$$reg),
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// special cases where one arg is zero
+
+instruct cmovN_reg_zero(cmpOp cmp, rFlagsReg cr, iRegN dst, iRegN src1, immN0 zero) %{
+  match(Set dst (CMoveN (Binary cmp cr) (Binary src1 zero)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, zr, $src1 $cmp\t# signed, compressed ptr"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             zr,
+             as_Register($src1$$reg),
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUN_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegN dst, iRegN src1, immN0 zero) %{
+  match(Set dst (CMoveN (Binary cmp cr) (Binary src1 zero)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, zr, $src1 $cmp\t# unsigned, compressed ptr"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             zr,
+             as_Register($src1$$reg),
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovN_zero_reg(cmpOp cmp, rFlagsReg cr, iRegN dst, immN0 zero, iRegN src2) %{
+  match(Set dst (CMoveN (Binary cmp cr) (Binary zero src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, $src2, zr $cmp\t# signed, compressed ptr"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             as_Register($src2$$reg),
+             zr,
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovUN_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegN dst, immN0 zero, iRegN src2) %{
+  match(Set dst (CMoveN (Binary cmp cr) (Binary zero src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "cselw $dst, $src2, zr $cmp\t# unsigned, compressed ptr"  %}
+
+  ins_encode %{
+    __ cselw(as_Register($dst$$reg),
+             as_Register($src2$$reg),
+             zr,
+             (Assembler::Condition)$cmp$$cmpcode);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovF_reg(cmpOp cmp, rFlagsReg cr, vRegF dst, vRegF src1,  vRegF src2)
+%{
+  match(Set dst (CMoveF (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+
+  format %{ "fcsels $dst, $src1, $src2, $cmp\t# signed cmove float\n\t" %}
+  ins_encode %{
+    Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+    __ fcsels(as_FloatRegister($dst$$reg),
+              as_FloatRegister($src2$$reg),
+              as_FloatRegister($src1$$reg),
+              cond);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovF_regU(cmpOpU cmp, rFlagsRegU cr, vRegF dst, vRegF src1,  vRegF src2)
+%{
+  match(Set dst (CMoveF (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+
+  format %{ "fcsels $dst, $src1, $src2, $cmp\t# unsigned cmove float\n\t" %}
+  ins_encode %{
+    Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+    __ fcsels(as_FloatRegister($dst$$reg),
+              as_FloatRegister($src2$$reg),
+              as_FloatRegister($src1$$reg),
+              cond);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovD_reg(cmpOp cmp, rFlagsReg cr, vRegD dst, vRegD src1,  vRegD src2)
+%{
+  match(Set dst (CMoveD (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+
+  format %{ "fcseld $dst, $src1, $src2, $cmp\t# signed cmove float\n\t" %}
+  ins_encode %{
+    Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+    __ fcseld(as_FloatRegister($dst$$reg),
+              as_FloatRegister($src2$$reg),
+              as_FloatRegister($src1$$reg),
+              cond);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmovD_regU(cmpOpU cmp, rFlagsRegU cr, vRegD dst, vRegD src1,  vRegD src2)
+%{
+  match(Set dst (CMoveD (Binary cmp cr) (Binary src1 src2)));
+
+  ins_cost(DEFAULT_COST);
+
+  format %{ "fcseld $dst, $src1, $src2, $cmp\t# unsigned cmove float\n\t" %}
+  ins_encode %{
+    Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+    __ fcseld(as_FloatRegister($dst$$reg),
+              as_FloatRegister($src2$$reg),
+              as_FloatRegister($src1$$reg),
+              cond);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// ============================================================================
+// Arithmetic Instructions
+//
+// TODO
+// these currently employ operations which do not set CR and hence are
+// not flagged as killing CR but we would like to isolate the cases
+// where we want to set flags from those where we don't. need to work
+// out how to do that.
+
+// Integer Addition
+
+instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
+  match(Set dst (AddI src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "addw  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ addw(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct addI_reg_imm(iRegINoSp dst, iRegI src1, immIAddSub src2) %{
+  match(Set dst (AddI src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "addw $dst, $src1, $src2" %}
+
+  // use opcode to indicate that this is an add not a sub
+  opcode(0x0);
+
+  ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct addI_reg_imm_i2l(iRegINoSp dst, iRegL src1, immIAddSub src2) %{
+  match(Set dst (AddI (ConvL2I src1) src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "addw $dst, $src1, $src2" %}
+
+  // use opcode to indicate that this is an add not a sub
+  opcode(0x0);
+
+  ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Pointer Addition
+instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
+  match(Set dst (AddP src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "add $dst, $src1, $src2\t# ptr" %}
+
+  ins_encode %{
+    __ add(as_Register($dst$$reg),
+           as_Register($src1$$reg),
+           as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct addP_reg_reg_ext(iRegPNoSp dst, iRegP src1, iRegI src2) %{
+  match(Set dst (AddP src1 (ConvI2L src2)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "add $dst, $src1, $src2\t# ptr" %}
+
+  ins_encode %{
+    __ add(as_Register($dst$$reg),
+           as_Register($src1$$reg),
+           as_Register($src2$$reg), ext::sxtw);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct addP_reg_reg_lsl(iRegPNoSp dst, iRegP src1, iRegL src2, immIScale scale) %{
+  match(Set dst (AddP src1 (LShiftL src2 scale)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "add $dst, $src1, $src2, LShiftL $scale\t# ptr" %}
+
+  ins_encode %{
+    __ lea(as_Register($dst$$reg),
+	   Address(as_Register($src1$$reg), as_Register($src2$$reg),
+		   Address::lsl($scale$$constant)));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct addP_reg_reg_ext_shift(iRegPNoSp dst, iRegP src1, iRegI src2, immIScale scale) %{
+  match(Set dst (AddP src1 (LShiftL (ConvI2L src2) scale)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "add $dst, $src1, $src2, I2L $scale\t# ptr" %}
+
+  ins_encode %{
+    __ lea(as_Register($dst$$reg),
+	   Address(as_Register($src1$$reg), as_Register($src2$$reg),
+		   Address::sxtw($scale$$constant)));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Pointer Immediate Addition
+// n.b. this needs to be more expensive than using an indirect memory
+// operand
+instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAddSub src2) %{
+  match(Set dst (AddP src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "add $dst, $src1, $src2\t# ptr" %}
+
+  // use opcode to indicate that this is an add not a sub
+  opcode(0x0);
+
+  ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Long Addition
+instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
+
+  match(Set dst (AddL src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ add(as_Register($dst$$reg),
+           as_Register($src1$$reg),
+           as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// No constant pool entries requiredLong Immediate Addition.
+instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
+  match(Set dst (AddL src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "add $dst, $src1, $src2" %}
+
+  // use opcode to indicate that this is an add not a sub
+  opcode(0x0);
+
+  ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Integer Subtraction
+instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
+  match(Set dst (SubI src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "subw  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ subw(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Immediate Subtraction
+instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
+  match(Set dst (SubI src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "subw $dst, $src1, $src2" %}
+
+  // use opcode to indicate that this is a sub not an add
+  opcode(0x1);
+
+  ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Long Subtraction
+instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
+
+  match(Set dst (SubL src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "sub  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ sub(as_Register($dst$$reg),
+           as_Register($src1$$reg),
+           as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// No constant pool entries requiredLong Immediate Subtraction.
+instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
+  match(Set dst (SubL src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "sub$dst, $src1, $src2" %}
+
+  // use opcode to indicate that this is a sub not an add
+  opcode(0x1);
+
+  ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Integer Negation (special case for sub)
+
+instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr) %{
+  match(Set dst (SubI zero src));
+
+  effect(KILL cr);
+
+  ins_cost(DEFAULT_COST);
+  format %{ "negsw $dst, $src\t# int" %}
+
+  ins_encode %{
+    __ negsw(as_Register($dst$$reg),
+             as_Register($src$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Long Negation
+
+instruct negL_reg(iRegLNoSp dst, iRegIorL2I src, immL0 zero, rFlagsReg cr) %{
+  match(Set dst (SubL zero src));
+
+  effect(KILL cr);
+
+  ins_cost(DEFAULT_COST);
+  format %{ "negs $dst, $src\t# long" %}
+
+  ins_encode %{
+    __ negs(as_Register($dst$$reg),
+            as_Register($src$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Integer Multiply
+
+instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
+  match(Set dst (MulI src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "mulw  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ mulw(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Long Multiply
+
+instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
+  match(Set dst (MulL src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "mul  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ mul(as_Register($dst$$reg),
+           as_Register($src1$$reg),
+           as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Combined Integer Multiply & Add/Sub
+
+instruct maddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
+  match(Set dst (AddI (MulI src1 src2) src3));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "madd  $dst, $src1, $src2, $src3" %}
+
+  ins_encode %{
+    __ maddw(as_Register($dst$$reg),
+             as_Register($src1$$reg),
+             as_Register($src2$$reg),
+             as_Register($src3$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct msubI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
+  match(Set dst (SubI (MulI src1 src2) src3));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "msub  $dst, $src1, $src2, $src3" %}
+
+  ins_encode %{
+    __ msubw(as_Register($dst$$reg),
+             as_Register($src1$$reg),
+             as_Register($src2$$reg),
+             as_Register($src3$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Combined Long Multiply & Add/Sub
+
+instruct maddL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
+  match(Set dst (AddL (MulL src1 src2) src3));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "madd  $dst, $src1, $src2, $src3" %}
+
+  ins_encode %{
+    __ madd(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            as_Register($src2$$reg),
+            as_Register($src3$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct msubL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
+  match(Set dst (SubL (MulL src1 src2) src3));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "msub  $dst, $src1, $src2, $src3" %}
+
+  ins_encode %{
+    __ msub(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            as_Register($src2$$reg),
+            as_Register($src3$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Integer Divide
+
+instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
+  match(Set dst (DivI src1 src2));
+
+  ins_cost(10*DEFAULT_COST);
+  format %{ "cmpw   $src1, #0x80000000\t# idiv\n\t"
+            "bne    normal\n\t"
+            "cmnw   $src2, #1\n\t"
+            "beq    normal\n\t"
+            "movw   $dst, $src1\n\t"
+            "b      done\n"
+    "normal: sdivw  $dst, $src1, $src2\n"
+    "done:" %}
+
+  ins_encode(aarch64_enc_divw(dst, src1, src2));
+  ins_pipe(pipe_class_default);
+%}
+
+// Long Divide
+
+instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
+  match(Set dst (DivL src1 src2));
+
+  ins_cost(10*DEFAULT_COST);
+  format %{ "cmp    $src1, #0x8000000000000000\t# ldiv\n\t"
+            "bne    normal\n\t"
+            "cmn    $src2, #1\n\t"
+            "beq    normal\n\t"
+            "mov    $dst, $src1\n\t"
+            "b      done\n"
+    "normal: sdiv   $dst, $src1, $src2\n"
+    "done:" %}
+
+  ins_encode(aarch64_enc_div(dst, src1, src2));
+  ins_pipe(pipe_class_default);
+%}
+
+// Integer Remainder
+
+instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
+  match(Set dst (ModI src1 src2));
+
+  format %{ "cmpw   $src1, #0x80000000\t# imod\n\t"
+            "bne    normal\n\t"
+            "cmnw   $src2, #1\n\t"
+            "beq    normal\n\t"
+            "movw   $dst, zr\n\t"
+            "b      done\n"
+    "normal: sdivw  rscratch1, $src1, $src2\n\t"
+            "msubw($dst, rscratch1, $src2, $src1"
+    "done:" %}
+
+  ins_encode(aarch64_enc_modw(dst, src1, src2));
+  ins_pipe(pipe_class_default);
+%}
+
+// Long Remainder
+
+instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
+  match(Set dst (ModL src1 src2));
+
+  ins_cost(10*DEFAULT_COST);
+  format %{ "cmp    $src1, #0x8000000000000000\t# lmod\n\t"
+            "bne    normal\n\t"
+            "cmn    $src2, #1\n\t"
+            "beq    normal\n\t"
+            "mov    $dst, zr\n\t"
+            "b      done\n"
+    "normal: sdiv   rscratch1, $src1, $src2\n"
+            "msub($dst, rscratch1, $src2, $src1"
+    "done:" %}
+
+  ins_encode(aarch64_enc_mod(dst, src1, src2));
+  ins_pipe(pipe_class_default);
+%}
+
+// Integer Shifts
+
+// Shift Left Register
+instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
+  match(Set dst (LShiftI src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "lslvw  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ lslvw(as_Register($dst$$reg),
+             as_Register($src1$$reg),
+             as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Left Immediate
+instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
+  match(Set dst (LShiftI src1 src2));
+
+  format %{ "lslw $dst, $src1, ($src2 & 0x1f)" %}
+
+  ins_encode %{
+    __ lslw(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            $src2$$constant & 0x1f);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Right Logical Register
+instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
+  match(Set dst (URShiftI src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "lsrvw  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ lsrvw(as_Register($dst$$reg),
+             as_Register($src1$$reg),
+             as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Right Logical Immediate
+instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
+  match(Set dst (URShiftI src1 src2));
+
+  format %{ "lsrw $dst, $src1, ($src2 & 0x1f)" %}
+
+  ins_encode %{
+    __ lsrw(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            $src2$$constant & 0x1f);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Right Arithmetic Register
+instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
+  match(Set dst (RShiftI src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "asrvw  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ asrvw(as_Register($dst$$reg),
+             as_Register($src1$$reg),
+             as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Right Arithmetic Immediate
+instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
+  match(Set dst (RShiftI src1 src2));
+
+  format %{ "asrw $dst, $src1, ($src2 & 0x1f)" %}
+
+  ins_encode %{
+    __ asrw(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            $src2$$constant & 0x1f);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Combined Int Mask and Right Shift (using UBFM)
+// TODO
+
+// Long Shifts
+
+// Shift Left Register
+instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
+  match(Set dst (LShiftL src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "lslv  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ lslv(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Left Immediate
+instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
+  match(Set dst (LShiftL src1 src2));
+
+  format %{ "lsl $dst, $src1, ($src2 & 0x3f)" %}
+
+  ins_encode %{
+    __ lsl(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            $src2$$constant & 0x3f);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Right Logical Register
+instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
+  match(Set dst (URShiftL src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "lsrv  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ lsrv(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Right Logical Immediate
+instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
+  match(Set dst (URShiftL src1 src2));
+
+  format %{ "lsr $dst, $src1, ($src2 & 0x3f)" %}
+
+  ins_encode %{
+    __ lsr(as_Register($dst$$reg),
+           as_Register($src1$$reg),
+           $src2$$constant & 0x3f);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Right Arithmetic Register
+instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
+  match(Set dst (RShiftL src1 src2));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "asrv  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ asrv(as_Register($dst$$reg),
+            as_Register($src1$$reg),
+            as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Right Arithmetic Immediate
+instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
+  match(Set dst (RShiftL src1 src2));
+
+  format %{ "asr $dst, $src1, ($src2 & 0x3f)" %}
+
+  ins_encode %{
+    __ asr(as_Register($dst$$reg),
+           as_Register($src1$$reg),
+           $src2$$constant & 0x3f);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+// BEGIN This section of the file is automatically generated. Do not edit --------------
+
+
+
+
+
+
+

+
+instruct regL_not_reg(iRegLNoSp dst,
+                         iRegL src1, immL_M1 m1,
+                         rFlagsReg cr) %{
+  match(Set dst (XorL src1 m1));
   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, int"  %}
+  format %{ "eon  $dst, $src1, zr" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             as_Register($src2$$reg),
-             as_Register($src1$$reg),
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ eon(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              zr,
+              Assembler::LSL, 0);
   %}

   ins_pipe(pipe_class_default);
 %}
-
-instruct cmovUI_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegI src1, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
-
+instruct regI_not_reg(iRegINoSp dst,
+                         iRegI src1, immI_M1 m1,
+                         rFlagsReg cr) %{
+  match(Set dst (XorI src1 m1));
   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, $src2, $src1 $cmp\t# unsigned, int"  %}
+  format %{ "eonw  $dst, $src1, zr" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             as_Register($src2$$reg),
-             as_Register($src1$$reg),
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ eonw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              zr,
+              Assembler::LSL, 0);
   %}

   ins_pipe(pipe_class_default);
 %}

-// special cases where one arg is zero
-
-// n.b. this is selected in preference to the rule above because it
-// avoids loading constant 0 into a source register
+instruct AndI_reg_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2, immI_M1 m1,
+                         rFlagsReg cr) %{
+  match(Set dst (AndI src1 (XorI src2 m1)));
+  ins_cost(DEFAULT_COST);
+  format %{ "bic  $dst, $src1, $src2" %}

-// TODO
-// we ought only to be able to cull one of these variants as the ideal
-// transforms ought always to order the zero consistently (to left/right?)
+  ins_encode %{
+    __ bic(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL, 0);
+  %}

-instruct cmovI_zero_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp cr) (Binary zero src2)));
+  ins_pipe(pipe_class_default);
+%}

+instruct AndL_reg_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2, immL_M1 m1,
+                         rFlagsReg cr) %{
+  match(Set dst (AndL src1 (XorL src2 m1)));
   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, $src2, zr $cmp\t# signed, int"  %}
+  format %{ "bic  $dst, $src1, $src2" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             as_Register($src2$$reg),
-             zr,
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ bic(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL, 0);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUI_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp cr) (Binary zero src2)));
-
+instruct OrI_reg_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2, immI_M1 m1,
+                         rFlagsReg cr) %{
+  match(Set dst (OrI src1 (XorI src2 m1)));
   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, $src2, zr $cmp\t# unsigned, int"  %}
+  format %{ "orn  $dst, $src1, $src2" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             as_Register($src2$$reg),
-             zr,
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ orn(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL, 0);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovI_reg_zero(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegI src1, immI0 zero) %{
-  match(Set dst (CMoveI (Binary cmp cr) (Binary src1 zero)));
-
+instruct OrL_reg_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2, immL_M1 m1,
+                         rFlagsReg cr) %{
+  match(Set dst (OrL src1 (XorL src2 m1)));
   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, zr, $src1 $cmp\t# signed, int"  %}
+  format %{ "orn  $dst, $src1, $src2" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             zr,
-             as_Register($src1$$reg),
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ orn(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL, 0);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUI_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegI src1, immI0 zero) %{
-  match(Set dst (CMoveI (Binary cmp cr) (Binary src1 zero)));
-
+instruct XorI_reg_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2, immI_M1 m1,
+                         rFlagsReg cr) %{
+  match(Set dst (XorI m1 (XorI src2 src1)));
   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, zr, $src1 $cmp\t# unsigned, int"  %}
+  format %{ "eon  $dst, $src1, $src2" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             zr,
-             as_Register($src1$$reg),
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ eon(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL, 0);
   %}

   ins_pipe(pipe_class_default);
 %}

-// special case for creating a boolean 0 or 1
+instruct XorL_reg_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2, immL_M1 m1,
+                         rFlagsReg cr) %{
+  match(Set dst (XorL m1 (XorL src2 src1)));
+  ins_cost(DEFAULT_COST);
+  format %{ "eon  $dst, $src1, $src2" %}

-// n.b. this is selected in preference to the rule above because it
-// avoids loading constants 0 and 1 into a source register
+  ins_encode %{
+    __ eon(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL, 0);
+  %}

-instruct cmovI_reg_zero_one(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
-  match(Set dst (CMoveI (Binary cmp cr) (Binary one zero)));
+  ins_pipe(pipe_class_default);
+%}

+instruct AndI_reg_URShift_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, immI_M1 src4, rFlagsReg cr) %{
+  match(Set dst (AndI src1 (XorI(URShiftI src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "csincw $dst, zr, zr $cmp\t# signed, int"  %}
+  format %{ "bicw  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    // equivalently
-    // cset(as_Register($dst$$reg),
-    //      negate_condition((Assembler::Condition)$cmp$$cmpcode));
-    __ csincw(as_Register($dst$$reg),
-	     zr,
-	     zr,
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ bicw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUI_reg_zero_one(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
-  match(Set dst (CMoveI (Binary cmp cr) (Binary one zero)));
-
+instruct AndL_reg_URShift_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, immL_M1 src4, rFlagsReg cr) %{
+  match(Set dst (AndL src1 (XorL(URShiftL src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "csincw $dst, zr, zr $cmp\t# unsigned, int"  %}
+  format %{ "bic  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    // equivalently
-    // cset(as_Register($dst$$reg),
-    //      negate_condition((Assembler::Condition)$cmp$$cmpcode));
-    __ csincw(as_Register($dst$$reg),
-	     zr,
-	     zr,
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ bic(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovL_reg_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
-
+instruct AndI_reg_RShift_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, immI_M1 src4, rFlagsReg cr) %{
+  match(Set dst (AndI src1 (XorI(RShiftI src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, $src2, $src1 $cmp\t# signed, long"  %}
+  format %{ "bicw  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            as_Register($src2$$reg),
-            as_Register($src1$$reg),
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ bicw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUL_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
-
+instruct AndL_reg_RShift_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, immL_M1 src4, rFlagsReg cr) %{
+  match(Set dst (AndL src1 (XorL(RShiftL src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, long"  %}
+  format %{ "bic  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            as_Register($src2$$reg),
-            as_Register($src1$$reg),
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ bic(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// special cases where one arg is zero
-
-instruct cmovL_reg_zero(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src1, immL0 zero) %{
-  match(Set dst (CMoveL (Binary cmp cr) (Binary src1 zero)));
-
+instruct AndI_reg_LShift_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, immI_M1 src4, rFlagsReg cr) %{
+  match(Set dst (AndI src1 (XorI(LShiftI src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, zr, $src1 $cmp\t# signed, long"  %}
+  format %{ "bicw  $dst, $src1, $src2, LSL $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            zr,
-            as_Register($src1$$reg),
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ bicw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUL_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, immL0 zero) %{
-  match(Set dst (CMoveL (Binary cmp cr) (Binary src1 zero)));
-
+instruct AndL_reg_LShift_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, immL_M1 src4, rFlagsReg cr) %{
+  match(Set dst (AndL src1 (XorL(LShiftL src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, zr, $src1 $cmp\t# unsigned, long"  %}
+  format %{ "bic  $dst, $src1, $src2, LSL $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            zr,
-            as_Register($src1$$reg),
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ bic(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovL_zero_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, immL0 zero, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp cr) (Binary zero src2)));
-
+instruct XorI_reg_URShift_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, immI_M1 src4, rFlagsReg cr) %{
+  match(Set dst (XorI src4 (XorI(URShiftI src2 src3) src1)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, $src2, zr $cmp\t# signed, long"  %}
+  format %{ "eonw  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            as_Register($src2$$reg),
-            zr,
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ eonw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUL_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, immL0 zero, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp cr) (Binary zero src2)));
-
+instruct XorL_reg_URShift_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, immL_M1 src4, rFlagsReg cr) %{
+  match(Set dst (XorL src4 (XorL(URShiftL src2 src3) src1)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, $src2, zr $cmp\t# unsigned, long"  %}
+  format %{ "eon  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            as_Register($src2$$reg),
-            zr,
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ eon(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovP_reg_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp cr) (Binary src1 src2)));
-
+instruct XorI_reg_RShift_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, immI_M1 src4, rFlagsReg cr) %{
+  match(Set dst (XorI src4 (XorI(RShiftI src2 src3) src1)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, $src2, $src1 $cmp\t# signed, ptr"  %}
+  format %{ "eonw  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            as_Register($src2$$reg),
-            as_Register($src1$$reg),
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ eonw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUP_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp cr) (Binary src1 src2)));
-
+instruct XorL_reg_RShift_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, immL_M1 src4, rFlagsReg cr) %{
+  match(Set dst (XorL src4 (XorL(RShiftL src2 src3) src1)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, ptr"  %}
+  format %{ "eon  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            as_Register($src2$$reg),
-            as_Register($src1$$reg),
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ eon(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// special cases where one arg is zero
-
-instruct cmovP_reg_zero(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, iRegP src1, immP0 zero) %{
-  match(Set dst (CMoveP (Binary cmp cr) (Binary src1 zero)));
-
+instruct XorI_reg_LShift_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, immI_M1 src4, rFlagsReg cr) %{
+  match(Set dst (XorI src4 (XorI(LShiftI src2 src3) src1)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, zr, $src1 $cmp\t# signed, ptr"  %}
+  format %{ "eonw  $dst, $src1, $src2, LSL $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            zr,
-            as_Register($src1$$reg),
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ eonw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUP_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src1, immP0 zero) %{
-  match(Set dst (CMoveP (Binary cmp cr) (Binary src1 zero)));
-
+instruct XorL_reg_LShift_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, immL_M1 src4, rFlagsReg cr) %{
+  match(Set dst (XorL src4 (XorL(LShiftL src2 src3) src1)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, zr, $src1 $cmp\t# unsigned, ptr"  %}
+  format %{ "eon  $dst, $src1, $src2, LSL $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            zr,
-            as_Register($src1$$reg),
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ eon(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovP_zero_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, immP0 zero, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp cr) (Binary zero src2)));
-
+instruct OrI_reg_URShift_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, immI_M1 src4, rFlagsReg cr) %{
+  match(Set dst (OrI src1 (XorI(URShiftI src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, $src2, zr $cmp\t# signed, ptr"  %}
+  format %{ "ornw  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            as_Register($src2$$reg),
-            zr,
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ ornw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUP_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, immP0 zero, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp cr) (Binary zero src2)));
-
+instruct OrL_reg_URShift_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, immL_M1 src4, rFlagsReg cr) %{
+  match(Set dst (OrL src1 (XorL(URShiftL src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "csel $dst, $src2, zr $cmp\t# unsigned, ptr"  %}
+  format %{ "orn  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    __ csel(as_Register($dst$$reg),
-            as_Register($src2$$reg),
-            zr,
-            (Assembler::Condition)$cmp$$cmpcode);
+    __ orn(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovN_reg_reg(cmpOp cmp, rFlagsReg cr, iRegN dst, iRegN src1, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp cr) (Binary src1 src2)));
-
+instruct OrI_reg_RShift_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, immI_M1 src4, rFlagsReg cr) %{
+  match(Set dst (OrI src1 (XorI(RShiftI src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, compressed ptr"  %}
+  format %{ "ornw  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             as_Register($src2$$reg),
-             as_Register($src1$$reg),
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ ornw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUN_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegN dst, iRegN src1, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp cr) (Binary src1 src2)));
-
+instruct OrL_reg_RShift_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, immL_M1 src4, rFlagsReg cr) %{
+  match(Set dst (OrL src1 (XorL(RShiftL src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, compressed ptr"  %}
+  format %{ "orn  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             as_Register($src2$$reg),
-             as_Register($src1$$reg),
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ orn(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// special cases where one arg is zero
+instruct OrI_reg_LShift_not_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, immI_M1 src4, rFlagsReg cr) %{
+  match(Set dst (OrI src1 (XorI(LShiftI src2 src3) src4)));
+  ins_cost(DEFAULT_COST);
+  format %{ "ornw  $dst, $src1, $src2, LSL $src3" %}

-instruct cmovN_reg_zero(cmpOp cmp, rFlagsReg cr, iRegN dst, iRegN src1, immN0 zero) %{
-  match(Set dst (CMoveN (Binary cmp cr) (Binary src1 zero)));
+  ins_encode %{
+    __ ornw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}

+instruct OrL_reg_LShift_not_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, immL_M1 src4, rFlagsReg cr) %{
+  match(Set dst (OrL src1 (XorL(LShiftL src2 src3) src4)));
   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, zr, $src1 $cmp\t# signed, compressed ptr"  %}
+  format %{ "orn  $dst, $src1, $src2, LSL $src3" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             zr,
-             as_Register($src1$$reg),
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ orn(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUN_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegN dst, iRegN src1, immN0 zero) %{
-  match(Set dst (CMoveN (Binary cmp cr) (Binary src1 zero)));
+instruct AndI_reg_URShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AndI src1 (URShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, zr, $src1 $cmp\t# unsigned, compressed ptr"  %}
+  format %{ "andw  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             zr,
-             as_Register($src1$$reg),
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ andw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovN_zero_reg(cmpOp cmp, rFlagsReg cr, iRegN dst, immN0 zero, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp cr) (Binary zero src2)));
+instruct AndL_reg_URShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AndL src1 (URShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, $src2, zr $cmp\t# signed, compressed ptr"  %}
+  format %{ "andr  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             as_Register($src2$$reg),
-             zr,
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ andr(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovUN_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegN dst, immN0 zero, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp cr) (Binary zero src2)));
+instruct AndI_reg_RShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AndI src1 (RShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "cselw $dst, $src2, zr $cmp\t# unsigned, compressed ptr"  %}
+  format %{ "andw  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ cselw(as_Register($dst$$reg),
-             as_Register($src2$$reg),
-             zr,
-             (Assembler::Condition)$cmp$$cmpcode);
+    __ andw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovF_reg(cmpOp cmp, rFlagsReg cr, vRegF dst, vRegF src1,  vRegF src2)
-%{
-  match(Set dst (CMoveF (Binary cmp cr) (Binary src1 src2)));
+instruct AndL_reg_RShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AndL src1 (RShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
+  format %{ "andr  $dst, $src1, $src2, ASR $src3" %}

-  format %{ "fcsels $dst, $src1, $src2, $cmp\t# signed cmove float\n\t" %}
   ins_encode %{
-    Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
-    __ fcsels(as_FloatRegister($dst$$reg),
-              as_FloatRegister($src2$$reg),
-              as_FloatRegister($src1$$reg),
-              cond);
+    __ andr(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct AndI_reg_LShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AndI src1 (LShiftI src2 src3)));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "andw  $dst, $src1, $src2, LSL $src3" %}
+
+  ins_encode %{
+    __ andw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovF_regU(cmpOpU cmp, rFlagsRegU cr, vRegF dst, vRegF src1,  vRegF src2)
-%{
-  match(Set dst (CMoveF (Binary cmp cr) (Binary src1 src2)));
+instruct AndL_reg_LShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AndL src1 (LShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
+  format %{ "andr  $dst, $src1, $src2, LSL $src3" %}

-  format %{ "fcsels $dst, $src1, $src2, $cmp\t# unsigned cmove float\n\t" %}
   ins_encode %{
-    Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
-    __ fcsels(as_FloatRegister($dst$$reg),
-              as_FloatRegister($src2$$reg),
-              as_FloatRegister($src1$$reg),
-              cond);
+    __ andr(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovD_reg(cmpOp cmp, rFlagsReg cr, vRegD dst, vRegD src1,  vRegD src2)
-%{
-  match(Set dst (CMoveD (Binary cmp cr) (Binary src1 src2)));
+instruct XorI_reg_URShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (XorI src1 (URShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
+  format %{ "eorw  $dst, $src1, $src2, LSR $src3" %}

-  format %{ "fcseld $dst, $src1, $src2, $cmp\t# signed cmove float\n\t" %}
   ins_encode %{
-    Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
-    __ fcseld(as_FloatRegister($dst$$reg),
-              as_FloatRegister($src2$$reg),
-              as_FloatRegister($src1$$reg),
-              cond);
+    __ eorw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct cmovD_regU(cmpOpU cmp, rFlagsRegU cr, vRegD dst, vRegD src1,  vRegD src2)
-%{
-  match(Set dst (CMoveD (Binary cmp cr) (Binary src1 src2)));
+instruct XorL_reg_URShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (XorL src1 (URShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
+  format %{ "eor  $dst, $src1, $src2, LSR $src3" %}

-  format %{ "fcseld $dst, $src1, $src2, $cmp\t# unsigned cmove float\n\t" %}
   ins_encode %{
-    Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
-    __ fcseld(as_FloatRegister($dst$$reg),
-              as_FloatRegister($src2$$reg),
-              as_FloatRegister($src1$$reg),
-              cond);
+    __ eor(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// ============================================================================
-// Arithmetic Instructions
-//
-// TODO
-// these currently employ operations which do not set CR and hence are
-// not flagged as killing CR but we would like to isolate the cases
-// where we want to set flags from those where we don't. need to work
-// out how to do that.
-
-// Integer Addition
-
-instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
-  match(Set dst (AddI src1 src2));
+instruct XorI_reg_RShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (XorI src1 (RShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "addw  $dst, $src1, $src2" %}
+  format %{ "eorw  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ addw(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            as_Register($src2$$reg));
+    __ eorw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct addI_reg_imm(iRegINoSp dst, iRegI src1, immIAddSub src2) %{
-  match(Set dst (AddI src1 src2));
+instruct XorL_reg_RShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (XorL src1 (RShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "addw $dst, $src1, $src2" %}
-
-  // use opcode to indicate that this is an add not a sub
-  opcode(0x0);
+  format %{ "eor  $dst, $src1, $src2, ASR $src3" %}

-  ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
+  ins_encode %{
+    __ eor(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
+  %}

   ins_pipe(pipe_class_default);
 %}

-instruct addI_reg_imm_i2l(iRegINoSp dst, iRegL src1, immIAddSub src2) %{
-  match(Set dst (AddI (ConvL2I src1) src2));
+instruct XorI_reg_LShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (XorI src1 (LShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "addw $dst, $src1, $src2" %}
+  format %{ "eorw  $dst, $src1, $src2, LSL $src3" %}

-  // use opcode to indicate that this is an add not a sub
-  opcode(0x0);
-
-  ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
+  ins_encode %{
+    __ eorw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
+  %}

   ins_pipe(pipe_class_default);
 %}

-// Pointer Addition
-instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
-  match(Set dst (AddP src1 src2));
+instruct XorL_reg_LShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (XorL src1 (LShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "add $dst, $src1, $src2\t# ptr" %}
+  format %{ "eor  $dst, $src1, $src2, LSL $src3" %}

   ins_encode %{
-    __ add(as_Register($dst$$reg),
-           as_Register($src1$$reg),
-           as_Register($src2$$reg));
+    __ eor(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// Pointer Immediate Addition
-// n.b. this needs to be more expensive than using an indirect memory
-// operand
-instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAddSub src2) %{
-  match(Set dst (AddP src1 src2));
+instruct OrI_reg_URShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (OrI src1 (URShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "add $dst, $src1, $src2\t# ptr" %}
-
-  // use opcode to indicate that this is an add not a sub
-  opcode(0x0);
+  format %{ "orrw  $dst, $src1, $src2, LSR $src3" %}

-  ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
+  ins_encode %{
+    __ orrw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
+  %}

   ins_pipe(pipe_class_default);
 %}

-// Long Addition
-instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
-
-  match(Set dst (AddL src1 src2));
+instruct OrL_reg_URShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (OrL src1 (URShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "add  $dst, $src1, $src2" %}
+  format %{ "orr  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    __ add(as_Register($dst$$reg),
-           as_Register($src1$$reg),
-           as_Register($src2$$reg));
+    __ orr(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// No constant pool entries requiredLong Immediate Addition.
-instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
-  match(Set dst (AddL src1 src2));
+instruct OrI_reg_RShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (OrI src1 (RShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "add $dst, $src1, $src2" %}
-
-  // use opcode to indicate that this is an add not a sub
-  opcode(0x0);
+  format %{ "orrw  $dst, $src1, $src2, ASR $src3" %}

-  ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
+  ins_encode %{
+    __ orrw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
+  %}

   ins_pipe(pipe_class_default);
 %}

-// Integer Subtraction
-instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
-  match(Set dst (SubI src1 src2));
+instruct OrL_reg_RShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (OrL src1 (RShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "subw  $dst, $src1, $src2" %}
+  format %{ "orr  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ subw(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            as_Register($src2$$reg));
+    __ orr(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// Immediate Subtraction
-instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
-  match(Set dst (SubI src1 src2));
+instruct OrI_reg_LShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (OrI src1 (LShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "subw $dst, $src1, $src2" %}
+  format %{ "orrw  $dst, $src1, $src2, LSL $src3" %}

-  // use opcode to indicate that this is a sub not an add
-  opcode(0x1);
-
-  ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
+  ins_encode %{
+    __ orrw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
+  %}

   ins_pipe(pipe_class_default);
 %}

-// Long Subtraction
-instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
-
-  match(Set dst (SubL src1 src2));
+instruct OrL_reg_LShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (OrL src1 (LShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "sub  $dst, $src1, $src2" %}
+  format %{ "orr  $dst, $src1, $src2, LSL $src3" %}

   ins_encode %{
-    __ sub(as_Register($dst$$reg),
-           as_Register($src1$$reg),
-           as_Register($src2$$reg));
+    __ orr(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// No constant pool entries requiredLong Immediate Subtraction.
-instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
-  match(Set dst (SubL src1 src2));
+instruct AddI_reg_URShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AddI src1 (URShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "sub$dst, $src1, $src2" %}
+  format %{ "addw  $dst, $src1, $src2, LSR $src3" %}

-  // use opcode to indicate that this is a sub not an add
-  opcode(0x1);
-
-  ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
+  ins_encode %{
+    __ addw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
+  %}

   ins_pipe(pipe_class_default);
 %}

-// Integer Negation (special case for sub)
-
-instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr) %{
-  match(Set dst (SubI zero src));
-
-  effect(KILL cr);
+instruct AddL_reg_URShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AddL src1 (URShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "negsw $dst, $src\t# int" %}
+  format %{ "add  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    __ negsw(as_Register($dst$$reg),
-             as_Register($src$$reg));
+    __ add(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// Long Negation
-
-instruct negL_reg(iRegLNoSp dst, iRegIorL2I src, immL0 zero, rFlagsReg cr) %{
-  match(Set dst (SubL zero src));
-
-  effect(KILL cr);
+instruct AddI_reg_RShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AddI src1 (RShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "negs $dst, $src\t# long" %}
+  format %{ "addw  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ negs(as_Register($dst$$reg),
-            as_Register($src$$reg));
+    __ addw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// Integer Multiply
-
-instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
-  match(Set dst (MulI src1 src2));
+instruct AddL_reg_RShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AddL src1 (RShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "mulw  $dst, $src1, $src2" %}
+  format %{ "add  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ mulw(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            as_Register($src2$$reg));
+    __ add(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// Long Multiply
-
-instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
-  match(Set dst (MulL src1 src2));
+instruct AddI_reg_LShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AddI src1 (LShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "mul  $dst, $src1, $src2" %}
+  format %{ "addw  $dst, $src1, $src2, LSL $src3" %}

   ins_encode %{
-    __ mul(as_Register($dst$$reg),
-           as_Register($src1$$reg),
-           as_Register($src2$$reg));
+    __ addw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// Combined Integer Multiply & Add/Sub
-
-instruct maddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
-  match(Set dst (AddI (MulI src1 src2) src3));
+instruct AddL_reg_LShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (AddL src1 (LShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "madd  $dst, $src1, $src2, $src3" %}
+  format %{ "add  $dst, $src1, $src2, LSL $src3" %}

   ins_encode %{
-    __ maddw(as_Register($dst$$reg),
-             as_Register($src1$$reg),
-             as_Register($src2$$reg),
-             as_Register($src3$$reg));
+    __ add(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct msubI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
-  match(Set dst (SubI (MulI src1 src2) src3));
+instruct SubI_reg_URShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (SubI src1 (URShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "msub  $dst, $src1, $src2, $src3" %}
+  format %{ "subw  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    __ msubw(as_Register($dst$$reg),
-             as_Register($src1$$reg),
-             as_Register($src2$$reg),
-             as_Register($src3$$reg));
+    __ subw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// Combined Long Multiply & Add/Sub
-
-instruct maddL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
-  match(Set dst (AddL (MulL src1 src2) src3));
+instruct SubL_reg_URShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (SubL src1 (URShiftL src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "madd  $dst, $src1, $src2, $src3" %}
+  format %{ "sub  $dst, $src1, $src2, LSR $src3" %}

   ins_encode %{
-    __ madd(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            as_Register($src2$$reg),
-            as_Register($src3$$reg));
+    __ sub(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-instruct msubL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
-  match(Set dst (SubL (MulL src1 src2) src3));
+instruct SubI_reg_RShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (SubI src1 (RShiftI src2 src3)));

   ins_cost(DEFAULT_COST);
-  format %{ "msub  $dst, $src1, $src2, $src3" %}
+  format %{ "subw  $dst, $src1, $src2, ASR $src3" %}

   ins_encode %{
-    __ msub(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            as_Register($src2$$reg),
-            as_Register($src3$$reg));
+    __ subw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
   %}

   ins_pipe(pipe_class_default);
 %}

-// Integer Divide
+instruct SubL_reg_RShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (SubL src1 (RShiftL src2 src3)));

-instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
-  match(Set dst (DivI src1 src2));
+  ins_cost(DEFAULT_COST);
+  format %{ "sub  $dst, $src1, $src2, ASR $src3" %}

-  ins_cost(10*DEFAULT_COST);
-  format %{ "cmpw   $src1, #0x80000000\t# idiv\n\t"
-            "bne    normal\n\t"
-            "cmnw   $src2, #1\n\t"
-            "beq    normal\n\t"
-            "movw   $dst, $src1\n\t"
-            "b      done\n"
-    "normal: sdivw  $dst, $src1, $src2\n"
-    "done:" %}
+  ins_encode %{
+    __ sub(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::ASR,
+              $src3$$constant & 0x3f);
+  %}

-  ins_encode(aarch64_enc_divw(dst, src1, src2));
   ins_pipe(pipe_class_default);
 %}

-// Long Divide
+instruct SubI_reg_LShift_reg(iRegINoSp dst,
+                         iRegI src1, iRegI src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (SubI src1 (LShiftI src2 src3)));

-instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
-  match(Set dst (DivL src1 src2));
+  ins_cost(DEFAULT_COST);
+  format %{ "subw  $dst, $src1, $src2, LSL $src3" %}

-  ins_cost(10*DEFAULT_COST);
-  format %{ "cmp    $src1, #0x8000000000000000\t# ldiv\n\t"
-            "bne    normal\n\t"
-            "cmn    $src2, #1\n\t"
-            "beq    normal\n\t"
-            "mov    $dst, $src1\n\t"
-            "b      done\n"
-    "normal: sdiv   $dst, $src1, $src2\n"
-    "done:" %}
+  ins_encode %{
+    __ subw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
+  %}

-  ins_encode(aarch64_enc_div(dst, src1, src2));
   ins_pipe(pipe_class_default);
 %}

-// Integer Remainder
+instruct SubL_reg_LShift_reg(iRegLNoSp dst,
+                         iRegL src1, iRegL src2,
+                         immI src3, rFlagsReg cr) %{
+  match(Set dst (SubL src1 (LShiftL src2 src3)));

-instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
-  match(Set dst (ModI src1 src2));
+  ins_cost(DEFAULT_COST);
+  format %{ "sub  $dst, $src1, $src2, LSL $src3" %}

-  format %{ "cmpw   $src1, #0x80000000\t# imod\n\t"
-            "bne    normal\n\t"
-            "cmnw   $src2, #1\n\t"
-            "beq    normal\n\t"
-            "movw   $dst, zr\n\t"
-            "b      done\n"
-    "normal: sdivw  rscratch1, $src1, $src2\n\t"
-            "msubw($dst, rscratch1, $src2, $src1"
-    "done:" %}
+  ins_encode %{
+    __ sub(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              as_Register($src2$$reg),
+              Assembler::LSL,
+              $src3$$constant & 0x3f);
+  %}

-  ins_encode(aarch64_enc_modw(dst, src1, src2));
   ins_pipe(pipe_class_default);
 %}

-// Long Remainder

-instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
-  match(Set dst (ModL src1 src2));

-  ins_cost(10*DEFAULT_COST);
-  format %{ "cmp    $src1, #0x8000000000000000\t# lmod\n\t"
-            "bne    normal\n\t"
-            "cmn    $src2, #1\n\t"
-            "beq    normal\n\t"
-            "mov    $dst, zr\n\t"
-            "b      done\n"
-    "normal: sdiv   rscratch1, $src1, $src2\n"
-            "msub($dst, rscratch1, $src2, $src1"
-    "done:" %}
+// Shift Left followed by Shift Right.
+// This idiom is used by the compiler for the i2b bytecode etc.
+instruct sbfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
+%{
+  match(Set dst (RShiftL (LShiftL src lshift_count) rshift_count));
+  // Make sure we are not going to exceed what sbfm can do.
+  predicate((unsigned int)n->in(2)->get_int() <= 63
+            && (unsigned int)n->in(1)->in(2)->get_int() <= 63);
+
+  ins_cost(DEFAULT_COST);
+  format %{ "sbfm  $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
+  ins_encode %{
+    int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
+    int s = 63 - lshift;
+    int r = (rshift - lshift) & 63;
+    __ sbfm(as_Register($dst$$reg),
+	    as_Register($src$$reg),
+	    r, s);
+  %}

-  ins_encode(aarch64_enc_mod(dst, src1, src2));
   ins_pipe(pipe_class_default);
 %}

-// Integer Shifts
-
-// Shift Left Register
-instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
-  match(Set dst (LShiftI src1 src2));
+// Shift Left followed by Shift Right.
+// This idiom is used by the compiler for the i2b bytecode etc.
+instruct sbfmwI(iRegINoSp dst, iRegI src, immI lshift_count, immI rshift_count)
+%{
+  match(Set dst (RShiftI (LShiftI src lshift_count) rshift_count));
+  // Make sure we are not going to exceed what sbfmw can do.
+  predicate((unsigned int)n->in(2)->get_int() <= 31
+            && (unsigned int)n->in(1)->in(2)->get_int() <= 31);

   ins_cost(DEFAULT_COST);
-  format %{ "lslvw  $dst, $src1, $src2" %}
-
+  format %{ "sbfmw  $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
   ins_encode %{
-    __ lslvw(as_Register($dst$$reg),
-             as_Register($src1$$reg),
-             as_Register($src2$$reg));
+    int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
+    int s = 31 - lshift;
+    int r = (rshift - lshift) & 31;
+    __ sbfmw(as_Register($dst$$reg),
+	    as_Register($src$$reg),
+	    r, s);
   %}

   ins_pipe(pipe_class_default);
 %}

-// Shift Left Immediate
-instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
-  match(Set dst (LShiftI src1 src2));
+// Shift Left followed by Shift Right.
+// This idiom is used by the compiler for the i2b bytecode etc.
+instruct ubfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
+%{
+  match(Set dst (URShiftL (LShiftL src lshift_count) rshift_count));
+  // Make sure we are not going to exceed what ubfm can do.
+  predicate((unsigned int)n->in(2)->get_int() <= 63
+            && (unsigned int)n->in(1)->in(2)->get_int() <= 63);

-  format %{ "lslw $dst, $src1, ($src2 & 0x1f)" %}
+  ins_cost(DEFAULT_COST);
+  format %{ "ubfm  $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
+  ins_encode %{
+    int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
+    int s = 63 - lshift;
+    int r = (rshift - lshift) & 63;
+    __ ubfm(as_Register($dst$$reg),
+	    as_Register($src$$reg),
+	    r, s);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+// Shift Left followed by Shift Right.
+// This idiom is used by the compiler for the i2b bytecode etc.
+instruct ubfmwI(iRegINoSp dst, iRegI src, immI lshift_count, immI rshift_count)
+%{
+  match(Set dst (URShiftI (LShiftI src lshift_count) rshift_count));
+  // Make sure we are not going to exceed what ubfmw can do.
+  predicate((unsigned int)n->in(2)->get_int() <= 31
+            && (unsigned int)n->in(1)->in(2)->get_int() <= 31);

+  ins_cost(DEFAULT_COST);
+  format %{ "ubfmw  $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
   ins_encode %{
-    __ lslw(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            $src2$$constant & 0x1f);
+    int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
+    int s = 31 - lshift;
+    int r = (rshift - lshift) & 31;
+    __ ubfmw(as_Register($dst$$reg),
+	    as_Register($src$$reg),
+	    r, s);
   %}

   ins_pipe(pipe_class_default);
 %}
+// Bitfield extract with shift & mask

-// Shift Right Logical Register
-instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
-  match(Set dst (URShiftI src1 src2));
+instruct ubfxwI(iRegINoSp dst, iRegI src, immI rshift, immI_bitmask mask)
+%{
+  match(Set dst (AndI (URShiftI src rshift) mask));

   ins_cost(DEFAULT_COST);
-  format %{ "lsrvw  $dst, $src1, $src2" %}
+  format %{ "ubfxw $dst, $src, $mask" %}
+  ins_encode %{
+    int rshift = $rshift$$constant;
+    long mask = $mask$$constant;
+    int width = exact_log2(mask+1);
+    __ ubfxw(as_Register($dst$$reg),
+	    as_Register($src$$reg), rshift, width);
+  %}
+  ins_pipe(pipe_class_default);
+%}
+instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
+%{
+  match(Set dst (AndL (URShiftL src rshift) mask));

+  ins_cost(DEFAULT_COST);
+  format %{ "ubfx $dst, $src, $mask" %}
   ins_encode %{
-    __ lsrvw(as_Register($dst$$reg),
-             as_Register($src1$$reg),
-             as_Register($src2$$reg));
+    int rshift = $rshift$$constant;
+    long mask = $mask$$constant;
+    int width = exact_log2(mask+1);
+    __ ubfx(as_Register($dst$$reg),
+	    as_Register($src$$reg), rshift, width);
   %}
+  ins_pipe(pipe_class_default);
+%}
+
+// We can use ubfx when extending an And with a mask when we know mask
+// is positive.  We know that because immI_bitmask guarantees it.
+instruct ubfxIConvI2L(iRegLNoSp dst, iRegI src, immI rshift, immI_bitmask mask)
+%{
+  match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));

+  ins_cost(DEFAULT_COST);
+  format %{ "ubfx $dst, $src, $mask" %}
+  ins_encode %{
+    int rshift = $rshift$$constant;
+    long mask = $mask$$constant;
+    int width = exact_log2(mask+1);
+    __ ubfx(as_Register($dst$$reg),
+	    as_Register($src$$reg), rshift, width);
+  %}
   ins_pipe(pipe_class_default);
 %}
+// Rotations

-// Shift Right Logical Immediate
-instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
-  match(Set dst (URShiftI src1 src2));
+instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
+%{
+  match(Set dst (OrL (LShiftL src1 lshift) (URShiftL src2 rshift)));
+  predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 63));

-  format %{ "lsrw $dst, $src1, ($src2 & 0x1f)" %}
+  ins_cost(DEFAULT_COST);
+  format %{ "extr $dst, $src1, $src2, #$rshift" %}

   ins_encode %{
-    __ lsrw(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            $src2$$constant & 0x1f);
+    __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
+            $rshift$$constant & 63);
   %}
-
   ins_pipe(pipe_class_default);
 %}

-// Shift Right Arithmetic Register
-instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
-  match(Set dst (RShiftI src1 src2));
+instruct extrOrI(iRegINoSp dst, iRegI src1, iRegI src2, immI lshift, immI rshift, rFlagsReg cr)
+%{
+  match(Set dst (OrI (LShiftI src1 lshift) (URShiftI src2 rshift)));
+  predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 31));

   ins_cost(DEFAULT_COST);
-  format %{ "asrvw  $dst, $src1, $src2" %}
+  format %{ "extr $dst, $src1, $src2, #$rshift" %}

   ins_encode %{
-    __ asrvw(as_Register($dst$$reg),
-             as_Register($src1$$reg),
-             as_Register($src2$$reg));
+    __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
+            $rshift$$constant & 31);
   %}
+  ins_pipe(pipe_class_default);
+%}
+
+instruct extrAddL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL (LShiftL src1 lshift) (URShiftL src2 rshift)));
+  predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 63));
+
+  ins_cost(DEFAULT_COST);
+  format %{ "extr $dst, $src1, $src2, #$rshift" %}

+  ins_encode %{
+    __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
+            $rshift$$constant & 63);
+  %}
   ins_pipe(pipe_class_default);
 %}

-// Shift Right Arithmetic Immediate
-instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
-  match(Set dst (RShiftI src1 src2));
+instruct extrAddI(iRegINoSp dst, iRegI src1, iRegI src2, immI lshift, immI rshift, rFlagsReg cr)
+%{
+  match(Set dst (AddI (LShiftI src1 lshift) (URShiftI src2 rshift)));
+  predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 31));

-  format %{ "asrw $dst, $src1, ($src2 & 0x1f)" %}
+  ins_cost(DEFAULT_COST);
+  format %{ "extr $dst, $src1, $src2, #$rshift" %}

   ins_encode %{
-    __ asrw(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            $src2$$constant & 0x1f);
+    __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
+            $rshift$$constant & 31);
   %}
+  ins_pipe(pipe_class_default);
+%}
+
+// Add/subtract (extended)
+
+
+instruct AddExtI(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (ConvI2L src2)));
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1,  $src2" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw);
+   %}
+  ins_pipe(pipe_class_default);
+%};
+
+instruct SubExtI(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (ConvI2L src2)));
+  ins_cost(DEFAULT_COST);
+  format %{ "sub  $dst, $src1,  $src2" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw);
+   %}
+  ins_pipe(pipe_class_default);
+%};
+
+
+instruct AddExtI_sxth(iRegINoSp dst, iRegI src1, iRegI src2, immI_16 lshift, immI_16 rshift, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1, sxth $src2" %}

+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxth);
+   %}
   ins_pipe(pipe_class_default);
 %}

-// Combined Int Mask and Right Shift (using UBFM)
-// TODO
+instruct AddExtI_sxtb(iRegINoSp dst, iRegI src1, iRegI src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1, sxtb $src2" %}

-// Long Shifts
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtb);
+   %}
+  ins_pipe(pipe_class_default);
+%}

-// Shift Left Register
-instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
-  match(Set dst (LShiftL src1 src2));
+instruct AddExtI_uxtb(iRegINoSp dst, iRegI src1, iRegI src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (URShiftI (LShiftI src2 lshift) rshift)));
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1, uxtb $src2" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb);
+   %}
+  ins_pipe(pipe_class_default);
+%}

+instruct AddExtL_sxth(iRegLNoSp dst, iRegL src1, iRegL src2, immI_48 lshift, immI_48 rshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
   ins_cost(DEFAULT_COST);
-  format %{ "lslv  $dst, $src1, $src2" %}
+  format %{ "add  $dst, $src1, sxth $src2" %}

-  ins_encode %{
-    __ lslv(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            as_Register($src2$$reg));
-  %}
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxth);
+   %}
+  ins_pipe(pipe_class_default);
+%}
+
+instruct AddExtL_sxtw(iRegLNoSp dst, iRegL src1, iRegL src2, immI_32 lshift, immI_32 rshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1, sxtw $src2" %}

+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw);
+   %}
   ins_pipe(pipe_class_default);
 %}

-// Shift Left Immediate
-instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
-  match(Set dst (LShiftL src1 src2));
+instruct AddExtL_sxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1, sxtb $src2" %}

-  format %{ "lsl $dst, $src1, ($src2 & 0x3f)" %}
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtb);
+   %}
+  ins_pipe(pipe_class_default);
+%}

-  ins_encode %{
-    __ lsl(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            $src2$$constant & 0x3f);
-  %}
+instruct AddExtL_uxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (URShiftL (LShiftL src2 lshift) rshift)));
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1, uxtb $src2" %}

+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb);
+   %}
   ins_pipe(pipe_class_default);
 %}

-// Shift Right Logical Register
-instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
-  match(Set dst (URShiftL src1 src2));

+instruct AddExtI_uxtb_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_255 mask, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (AndI src2 mask)));
   ins_cost(DEFAULT_COST);
-  format %{ "lsrv  $dst, $src1, $src2" %}
+  format %{ "addw  $dst, $src1, $src2, uxtb" %}

-  ins_encode %{
-    __ lsrv(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            as_Register($src2$$reg));
-  %}
+   ins_encode %{
+     __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb);
+   %}
+  ins_pipe(pipe_class_default);
+%}
+
+instruct AddExtI_uxth_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_65535 mask, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (AndI src2 mask)));
+  ins_cost(DEFAULT_COST);
+  format %{ "addw  $dst, $src1, $src2, uxth" %}

+   ins_encode %{
+     __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth);
+   %}
   ins_pipe(pipe_class_default);
 %}

-// Shift Right Logical Immediate
-instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
-  match(Set dst (URShiftL src1 src2));
+instruct AddExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (AndL src2 mask)));
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1, $src2, uxtb" %}

-  format %{ "lsr $dst, $src1, ($src2 & 0x3f)" %}
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb);
+   %}
+  ins_pipe(pipe_class_default);
+%}

-  ins_encode %{
-    __ lsr(as_Register($dst$$reg),
-           as_Register($src1$$reg),
-           $src2$$constant & 0x3f);
-  %}
+instruct AddExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (AndL src2 mask)));
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1, $src2, uxth" %}

+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth);
+   %}
   ins_pipe(pipe_class_default);
 %}

-// Shift Right Arithmetic Register
-instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
-  match(Set dst (RShiftL src1 src2));
+instruct AddExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (AndL src2 mask)));
+  ins_cost(DEFAULT_COST);
+  format %{ "add  $dst, $src1, $src2, uxtw" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtw);
+   %}
+  ins_pipe(pipe_class_default);
+%}

+instruct SubExtI_uxtb_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_255 mask, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (AndI src2 mask)));
   ins_cost(DEFAULT_COST);
-  format %{ "asrv  $dst, $src1, $src2" %}
+  format %{ "subw  $dst, $src1, $src2, uxtb" %}

-  ins_encode %{
-    __ asrv(as_Register($dst$$reg),
-            as_Register($src1$$reg),
-            as_Register($src2$$reg));
-  %}
+   ins_encode %{
+     __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb);
+   %}
+  ins_pipe(pipe_class_default);
+%}
+
+instruct SubExtI_uxth_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_65535 mask, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (AndI src2 mask)));
+  ins_cost(DEFAULT_COST);
+  format %{ "subw  $dst, $src1, $src2, uxth" %}

+   ins_encode %{
+     __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth);
+   %}
   ins_pipe(pipe_class_default);
 %}

-// Shift Right Arithmetic Immediate
-instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
-  match(Set dst (RShiftL src1 src2));
+instruct SubExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (AndL src2 mask)));
+  ins_cost(DEFAULT_COST);
+  format %{ "sub  $dst, $src1, $src2, uxtb" %}

-  format %{ "asr $dst, $src1, ($src2 & 0x3f)" %}
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb);
+   %}
+  ins_pipe(pipe_class_default);
+%}

-  ins_encode %{
-    __ asr(as_Register($dst$$reg),
-           as_Register($src1$$reg),
-           $src2$$constant & 0x3f);
-  %}
+instruct SubExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (AndL src2 mask)));
+  ins_cost(DEFAULT_COST);
+  format %{ "sub  $dst, $src1, $src2, uxth" %}

+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth);
+   %}
   ins_pipe(pipe_class_default);
 %}

+instruct SubExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (AndL src2 mask)));
+  ins_cost(DEFAULT_COST);
+  format %{ "sub  $dst, $src1, $src2, uxtw" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtw);
+   %}
+  ins_pipe(pipe_class_default);
+%}
+// END This section of the file is automatically generated. Do not edit --------------
 // Combined Long Mask and Right Shift (using UBFM)
 // TODO

@@ -7870,6 +9275,7 @@
 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2) %{
   match(Set dst (XorL src1 src2));

+  ins_cost(DEFAULT_COST);
   format %{ "eor  $dst, $src1, $src2\t# int" %}

   ins_encode %{
@@ -7881,12 +9287,11 @@
   ins_pipe(pipe_class_default);
 %}

-// Arithmetic Conversion Instructions
-
 instruct convI2L_reg_reg(iRegLNoSp dst, iRegI src)
 %{
   match(Set dst (ConvI2L src));

+  ins_cost(DEFAULT_COST);
   format %{ "sxtw  $dst, $src\t# i2l" %}
   ins_encode %{
     __ sbfm($dst$$Register, $src$$Register, 0, 31);
diff -ur hs-tmp/src/cpu/aarch64/vm/assembler_aarch64.hpp /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/assembler_aarch64.hpp
--- hs-tmp/src/cpu/aarch64/vm/assembler_aarch64.hpp	2013-10-25 16:34:20.469631919 +0100
+++ /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/assembler_aarch64.hpp	2013-10-16 17:07:08.484228081 +0100
@@ -1286,7 +1286,7 @@
     f(kind, 23, 22);
   }

-  // Logical (shifted regsiter)
+  // Logical (shifted register)
 #define INSN(NAME, size, op, N)					\
   void NAME(Register Rd, Register Rn, Register Rm,		\
 	    enum shift_kind kind = LSL, unsigned shift = 0) {	\
@@ -1316,7 +1316,7 @@

 #undef INSN

-  // Add/subtract (shifted regsiter)
+  // Add/subtract (shifted register)
 #define INSN(NAME, size, op)				\
   void NAME(Register Rd, Register Rn, Register Rm,	\
 	    enum shift_kind kind, unsigned shift = 0) {	\
diff -ur hs-tmp/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- hs-tmp/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	2013-10-25 16:34:20.473631794 +0100
+++ /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	2013-10-17 18:55:50.887377607 +0100
@@ -1295,7 +1295,8 @@
   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
     Label next_test;
     // See if the receiver is receiver[n].
-    __ ldr(rscratch1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
+    __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
+    __ ldr(rscratch1, Address(rscratch2));
     __ cmp(recv, rscratch1);
     __ br(Assembler::NE, next_test);
     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
@@ -1307,12 +1308,15 @@
   // Didn't find receiver; find next empty slot and fill it in
   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
     Label next_test;
-    Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
+    __ lea(rscratch2,
+	   Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
+    Address recv_addr(rscratch2);
     __ ldr(rscratch1, recv_addr);
     __ cbnz(rscratch1, next_test);
     __ str(recv, recv_addr);
     __ mov(rscratch1, DataLayout::counter_increment);
-    __ str(rscratch1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
+    __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
+    __ str(rscratch1, Address(rscratch2));
     __ b(*update_done);
     __ bind(next_test);
   }
@@ -2586,7 +2590,8 @@
         if (receiver == NULL) {
           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
 	  __ mov_metadata(rscratch1, known_klass->constant_encoding());
-          __ str(rscratch1, recv_addr);
+	  __ lea(rscratch2, recv_addr);
+          __ str(rscratch1, Address(rscratch2));
           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
 	  __ addptr(counter_addr, DataLayout::counter_increment);
           return;
diff -ur hs-tmp/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- hs-tmp/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	2013-10-25 16:34:20.486631387 +0100
+++ /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	2013-10-25 16:29:15.924131639 +0100
@@ -2078,7 +2078,7 @@
   }
 }

-void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
+void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
   if (use_XOR_for_compressed_class_base) {
     if (Universe::narrow_klass_shift() != 0) {
       eor(dst, src, (uint64_t)Universe::narrow_klass_base());
@@ -2089,29 +2089,29 @@
     return;
   }

-#ifdef ASSERT
-  verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
-#endif
+#ifdef ASSERT
+  verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
+#endif

   Register rbase = dst;
-  if (dst == src) rbase = rheapbase;
-  mov(rbase, (uint64_t)Universe::narrow_klass_base());
-  sub(dst, src, rbase);
-  if (Universe::narrow_klass_shift() != 0) {
-    assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
-    lsr(dst, dst, LogKlassAlignmentInBytes);
-  }
-  if (dst == src) reinit_heapbase();
-}
-
-void MacroAssembler::encode_klass_not_null(Register r) {
-  encode_klass_not_null(r, r);
-}
-
-void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
-  Register rbase = dst;
-  assert(Universe::narrow_klass_base() != NULL, "Base should be initialized");
-  assert (UseCompressedClassPointers, "should only be used for compressed headers");
+  if (dst == src) rbase = rheapbase;
+  mov(rbase, (uint64_t)Universe::narrow_klass_base());
+  sub(dst, src, rbase);
+  if (Universe::narrow_klass_shift() != 0) {
+    assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
+    lsr(dst, dst, LogKlassAlignmentInBytes);
+  }
+  if (dst == src) reinit_heapbase();
+}
+
+void MacroAssembler::encode_klass_not_null(Register r) {
+  encode_klass_not_null(r, r);
+}
+
+void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
+  Register rbase = dst;
+  assert(Universe::narrow_klass_base() != NULL, "Base should be initialized");
+  assert (UseCompressedClassPointers, "should only be used for compressed headers");

   if (use_XOR_for_compressed_class_base) {
     if (Universe::narrow_klass_shift() != 0) {
@@ -2123,23 +2123,23 @@
     return;
   }

-  // Cannot assert, unverified entry point counts instructions (see .ad file)
-  // vtableStubs also counts instructions in pd_code_size_limit.
-  // Also do not verify_oop as this is called by verify_oop.
-  if (dst == src) rbase = rheapbase;
-  mov(rbase, (uint64_t)Universe::narrow_klass_base());
-  if (Universe::narrow_klass_shift() != 0) {
-    assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
-    add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes);
-  } else {
-    add(dst, rbase, src);
-  }
-  if (dst == src) reinit_heapbase();
-}
-
-void  MacroAssembler::decode_klass_not_null(Register r) {
-  decode_klass_not_null(r, r);
-}
+  // Cannot assert, unverified entry point counts instructions (see .ad file)
+  // vtableStubs also counts instructions in pd_code_size_limit.
+  // Also do not verify_oop as this is called by verify_oop.
+  if (dst == src) rbase = rheapbase;
+  mov(rbase, (uint64_t)Universe::narrow_klass_base());
+  if (Universe::narrow_klass_shift() != 0) {
+    assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
+    add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes);
+  } else {
+    add(dst, rbase, src);
+  }
+  if (dst == src) reinit_heapbase();
+}
+
+void  MacroAssembler::decode_klass_not_null(Register r) {
+  decode_klass_not_null(r, r);
+}

 // TODO
 //
diff -ur hs-tmp/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
--- hs-tmp/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	2013-10-25 16:34:20.486631387 +0100
+++ /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	2013-10-25 16:30:09.186473470 +0100
@@ -89,15 +89,16 @@

   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);

+  // Maximum size of class area in Metaspace when compressed
   uint64_t use_XOR_for_compressed_class_base;

  public:
   MacroAssembler(CodeBuffer* code) : Assembler(code) {
     use_XOR_for_compressed_class_base
       = (operand_valid_for_logical_immediate(false /*is32*/,
-                                            (uint64_t)Universe::narrow_klass_base())
-        && ((uint64_t)Universe::narrow_klass_base()
-            > (1u << log2_intptr(CompressedClassSpaceSize))));
+					     (uint64_t)Universe::narrow_klass_base())
+	 && ((uint64_t)Universe::narrow_klass_base()
+	     > (1u << log2_intptr(CompressedClassSpaceSize))));
   }

   // Biased locking support
@@ -1022,10 +1023,12 @@
   // Arithmetics

   void addptr(Address dst, int32_t src) {
-    ldr(rscratch1, dst);
+    lea(rscratch2, dst);
+    ldr(rscratch1, Address(rscratch2));
     add(rscratch1, rscratch1, src);
-    str(rscratch1, dst);
-}
+    str(rscratch1, Address(rscratch2));
+  }
+
   // unimplemented
 #if 0
   void addptr(Address dst, Register src);
diff -ur hs-tmp/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
--- hs-tmp/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	2013-10-25 16:34:20.492631199 +0100
+++ /local/aarch64/jdk8/hotspot/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	2013-10-25 11:18:53.470583457 +0100
@@ -281,7 +281,7 @@
     Label parameters_done;
     // parameter count is still in c_rarg6
     // and parameter pointer identifying param 1 is in c_rarg5
-    __ cbz(c_rarg6, parameters_done);
+    __ cbzw(c_rarg6, parameters_done);

     address loop = __ pc();
     __ ldr(rscratch1, Address(__ post(c_rarg5, wordSize)));


From aph at redhat.com  Fri Oct 25 10:38:42 2013
From: aph at redhat.com (Andrew Haley)
Date: Fri, 25 Oct 2013 18:38:42 +0100
Subject: [aarch64-port-dev ] Add a bunch of missing JVMTI methods
Message-ID: <526AACA2.2050907@redhat.com>

This fixes Eclipse debugging with the latest VM builds.

Andrew.


# HG changeset patch
# User aph
# Date 1382722618 -3600
# Node ID 55c4c3af794e1d7e999e530823e02c5907eaa376
# Parent  d4c02a1427a6e16972718078c317f24160f5f904
Add a bunch of missing JVMTI methods.

diff -r d4c02a1427a6 -r 55c4c3af794e src/cpu/aarch64/vm/interp_masm_aarch64.cpp
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Fri Oct 25 16:31:03 2013 +0100
+++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Fri Oct 25 18:36:58 2013 +0100
@@ -200,7 +200,18 @@
 void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache,
                                                                Register tmp,
                                                                int bcp_offset,
-                                                               size_t index_size) { Unimplemented(); }
+                                                               size_t index_size) {
+  assert(cache != tmp, "must use different register");
+  get_cache_index_at_bcp(tmp, bcp_offset, index_size);
+  assert(sizeof(ConstantPoolCacheEntry) == 4 * wordSize, "adjust code below");
+  // convert from field index to ConstantPoolCacheEntry index
+  // and from word offset to byte offset
+  assert(exact_log2(in_bytes(ConstantPoolCacheEntry::size_in_bytes())) == 2 + LogBytesPerWord, "else change next line");
+  ldr(cache, Address(rfp, frame::interpreter_frame_cache_offset * wordSize));
+  // skip past the header
+  add(cache, cache, in_bytes(ConstantPoolCache::base_offset()));
+  add(cache, cache, tmp, Assembler::LSL, 2 + LogBytesPerWord);  // construct pointer to cache entry
+}

 void InterpreterMacroAssembler::get_method_counters(Register method,
                                                     Register mcs, Label& skip) {
diff -r d4c02a1427a6 -r 55c4c3af794e src/cpu/aarch64/vm/templateTable_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp	Fri Oct 25 16:31:03 2013 +0100
+++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp	Fri Oct 25 18:36:58 2013 +0100
@@ -262,7 +262,15 @@
   }

   if (JvmtiExport::can_post_breakpoint()) {
-    __ call_Unimplemented();
+    Label L_fast_patch;
+    // if a breakpoint is present we can't rewrite the stream directly
+    __ load_unsigned_byte(temp_reg, at_bcp(0));
+    __ cmpw(temp_reg, Bytecodes::_breakpoint);
+    __ br(Assembler::NE, L_fast_patch);
+    // Let breakpoint table handling rewrite to quicker bytecode
+    __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::set_original_bytecode_at), rmethod, rbcp, bc_reg);
+    __ b(L_patch_done);
+    __ bind(L_fast_patch);
   }

 #ifdef ASSERT
@@ -2651,7 +2659,54 @@
 void TemplateTable::jvmti_post_fast_field_mod()
 {
   if (JvmtiExport::can_post_field_modification()) {
-    __ call_Unimplemented();
+    // Check to see if a field modification watch has been set before
+    // we take the time to call into the VM.
+    Label L2;
+    __ lea(rscratch1, ExternalAddress((address)JvmtiExport::get_field_modification_count_addr()));
+    __ ldrw(c_rarg3, Address(rscratch1));
+    __ cbzw(c_rarg3, L2);
+    __ pop_ptr(r19);                  // copy the object pointer from tos
+    __ verify_oop(r19);
+    __ push_ptr(r19);                 // put the object pointer back on tos
+    // Save tos values before call_VM() clobbers them. Since we have
+    // to do it for every data type, we use the saved values as the
+    // jvalue object.
+    switch (bytecode()) {          // load values into the jvalue object
+    case Bytecodes::_fast_aputfield: __ push_ptr(r0); break;
+    case Bytecodes::_fast_bputfield: // fall through
+    case Bytecodes::_fast_sputfield: // fall through
+    case Bytecodes::_fast_cputfield: // fall through
+    case Bytecodes::_fast_iputfield: __ push_i(r0); break;
+    case Bytecodes::_fast_dputfield: __ push_d(); break;
+    case Bytecodes::_fast_fputfield: __ push_f(); break;
+    case Bytecodes::_fast_lputfield: __ push_l(r0); break;
+
+    default:
+      ShouldNotReachHere();
+    }
+    __ mov(c_rarg3, esp);             // points to jvalue on the stack
+    // access constant pool cache entry
+    __ get_cache_entry_pointer_at_bcp(c_rarg2, r0, 1);
+    __ verify_oop(r19);
+    // r19: object pointer copied above
+    // c_rarg2: cache entry pointer
+    // c_rarg3: jvalue object on the stack
+    __ call_VM(noreg,
+               CAST_FROM_FN_PTR(address,
+                                InterpreterRuntime::post_field_modification),
+               r19, c_rarg2, c_rarg3);
+
+    switch (bytecode()) {             // restore tos values
+    case Bytecodes::_fast_aputfield: __ pop_ptr(r0); break;
+    case Bytecodes::_fast_bputfield: // fall through
+    case Bytecodes::_fast_sputfield: // fall through
+    case Bytecodes::_fast_cputfield: // fall through
+    case Bytecodes::_fast_iputfield: __ pop_i(r0); break;
+    case Bytecodes::_fast_dputfield: __ pop_d(); break;
+    case Bytecodes::_fast_fputfield: __ pop_f(); break;
+    case Bytecodes::_fast_lputfield: __ pop_l(r0); break;
+    }
+    __ bind(L2);
   }
 }

@@ -2731,8 +2786,27 @@
   transition(atos, state);
   // Do the JVMTI work here to avoid disturbing the register state below
   if (JvmtiExport::can_post_field_access()) {
-    __ call_Unimplemented();
+    // Check to see if a field access watch has been set before we
+    // take the time to call into the VM.
+    Label L1;
+    __ lea(rscratch1, ExternalAddress((address) JvmtiExport::get_field_access_count_addr()));
+    __ ldrw(r2, Address(rscratch1));
+    __ cbzw(r2, L1);
+    // access constant pool cache entry
+    __ get_cache_entry_pointer_at_bcp(c_rarg2, rscratch2, 1);
+    __ verify_oop(r0);
+    __ push_ptr(r0);  // save object pointer before call_VM() clobbers it
+    __ mov(c_rarg1, r0);
+    // c_rarg1: object pointer copied above
+    // c_rarg2: cache entry pointer
+    __ call_VM(noreg,
+               CAST_FROM_FN_PTR(address,
+                                InterpreterRuntime::post_field_access),
+               c_rarg1, c_rarg2);
+    __ pop_ptr(r0); // restore object pointer
+    __ bind(L1);
   }
+
   // access constant pool cache
   __ get_cache_and_index_at_bcp(r2, r1, 1);
   __ ldr(r1, Address(r2, in_bytes(ConstantPoolCache::base_offset() +


From edward.nevill at linaro.org  Mon Oct 28 12:59:17 2013
From: edward.nevill at linaro.org (Edward Nevill)
Date: Mon, 28 Oct 2013 12:59:17 -0700
Subject: [aarch64-port-dev ] A rather large patch to aarch64.ad
In-Reply-To: <526A9E41.3080002@redhat.com>
References: <526A9E41.3080002@redhat.com>
Message-ID: <1382990357.1513.7.camel@fleetfoot.lan>

On Fri, 2013-10-25 at 17:37 +0100, Andrew Haley wrote:
> This is a substantial rewrite of the AArch64 patterns for arithmetic
> and memory access.  The idea is to make use of the more complex
> AArch64 instructions wherever possible, so that e.g. we use UBFX
> rather than a series of shifts and masks, and LDR Xd, [Xn, Wn, sxtw #3]
> for array loads.

4000 more lines deleted...

Hi Andrew,

I have merged this in and tested it on the RTSM model which shows an appreciable performance gain on a range of benchmarks.

I have also briefly scanned the > 4000 lines of diffs.

One question I had was the following

+  ins_pipe(pipe_class_default);
+%}
+// BEGIN This section of the file is automatically generated. Do not edit --------------
+
+

Is the section in question in fact automatically generated? And if so where is the tool to generate it?

Otherwise it all looks good to me, please push.

Thanks for this,
Ed.




From aph at redhat.com  Mon Oct 28 13:34:19 2013
From: aph at redhat.com (Andrew Haley)
Date: Mon, 28 Oct 2013 20:34:19 +0000
Subject: [aarch64-port-dev ] A rather large patch to aarch64.ad
In-Reply-To: <1382990357.1513.7.camel@fleetfoot.lan>
References: <526A9E41.3080002@redhat.com>
	<1382990357.1513.7.camel@fleetfoot.lan>
Message-ID: <526ECA4B.7080401@redhat.com>

On 10/28/2013 07:59 PM, Edward Nevill wrote:
> Is the section in question in fact automatically generated? And if so where is the tool to generate it?

It'll be there in the commit.

Andrew.



From adinn at redhat.com  Tue Oct 29 03:08:34 2013
From: adinn at redhat.com (Andrew Dinn)
Date: Tue, 29 Oct 2013 10:08:34 +0000
Subject: [aarch64-port-dev ] A rather large patch to aarch64.ad
In-Reply-To: <526A9E41.3080002@redhat.com>
References: <526A9E41.3080002@redhat.com>
Message-ID: <526F8922.40108@redhat.com>

On 25/10/13 17:37, Andrew Haley wrote:
> This is a substantial rewrite of the AArch64 patterns for arithmetic
> and memory access.  The idea is to make use of the more complex
> AArch64 instructions wherever possible, so that e.g. we use UBFX
> rather than a series of shifts and masks, and LDR Xd, [Xn, Wn, sxtw #3]
> for array loads.
> 
> The patch itself is hard to follow because of the reorganization I had
> to do.  I apologize for that.  However, the resulting aarch64.ad isn't
> so bad.
> 
> I have checked many of these patterns and HotSpot really does generate
> the fast AArch64 instructions.
> 
> Comments?

Apologies for the lack of comment. The new rules look good but I have
not yet tried them. I have been holding off pulling these changes down
while I try to pin down the register pressure problem thrown up by
eclipse -- just in case the pulled changes make the bug go underground.
I think I have pinned down exactly where things go wrong but am still
not clear exactly why.

However, since it takes almost 1/2 hour to reach the point of error I
think I will try out a build which includes the new rules. If the bug
still remains then at least I will be able to restart a debug session
somewhat faster.

regards,


Andrew Dinn
-----------



From aph at redhat.com  Tue Oct 29 07:15:30 2013
From: aph at redhat.com (Andrew Haley)
Date: Tue, 29 Oct 2013 14:15:30 +0000
Subject: [aarch64-port-dev ] aarch64.ad: Rotate instructions and a few minor
	twiddles
Message-ID: <526FC302.4030404@redhat.com>

Rotate variable, mainly, and a few corrections and additions.

Andrew.


# HG changeset patch
# User aph
# Date 1383055925 0
# Node ID 2d0b9fa2cd76ca4a9d397e7d2573e72bdf85de2b
# Parent  55c4c3af794e1d7e999e530823e02c5907eaa376
Variable rotate instructions

diff -r 55c4c3af794e -r 2d0b9fa2cd76 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Fri Oct 25 18:36:58 2013 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad	Tue Oct 29 14:12:05 2013 +0000
@@ -3478,6 +3478,16 @@
   interface(CONST_INTER);
 %}

+operand immI_64()
+%{
+  predicate(n->get_int() == 64);
+  match(ConI);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
 operand immI_255()
 %{
   predicate(n->get_int() == 255);
@@ -6974,10 +6984,26 @@
   ins_pipe(pipe_class_default);
 %}

+instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr)
+%{
+  match(Set dst (MulHiL src1 src2));
+
+  ins_cost(2 * DEFAULT_COST);
+  format %{ "smulh   $dst, $src1, $src2, \t# mulhi" %}
+
+  ins_encode %{
+    __ smulh(as_Register($dst$$reg),
+             as_Register($src1$$reg),
+	     as_Register($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
 // Combined Integer Multiply & Add/Sub

 instruct maddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
-  match(Set dst (AddI (MulI src1 src2) src3));
+  match(Set dst (AddI src3 (MulI src1 src2)));

   ins_cost(DEFAULT_COST);
   format %{ "madd  $dst, $src1, $src2, $src3" %}
@@ -6993,7 +7019,7 @@
 %}

 instruct msubI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
-  match(Set dst (SubI (MulI src1 src2) src3));
+  match(Set dst (SubI src3 (MulI src1 src2)));

   ins_cost(DEFAULT_COST);
   format %{ "msub  $dst, $src1, $src2, $src3" %}
@@ -7011,7 +7037,7 @@
 // Combined Long Multiply & Add/Sub

 instruct maddL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
-  match(Set dst (AddL (MulL src1 src2) src3));
+  match(Set dst (AddL src3 (MulL src1 src2)));

   ins_cost(DEFAULT_COST);
   format %{ "madd  $dst, $src1, $src2, $src3" %}
@@ -7027,7 +7053,7 @@
 %}

 instruct msubL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
-  match(Set dst (SubL (MulL src1 src2) src3));
+  match(Set dst (SubL src3 (MulL src1 src2)));

   ins_cost(DEFAULT_COST);
   format %{ "msub  $dst, $src1, $src2, $src3" %}
@@ -7313,14 +7339,6 @@
 %}
 // BEGIN This section of the file is automatically generated. Do not edit --------------

-
-
-
-
-
-
-
-
 instruct regL_not_reg(iRegLNoSp dst,
                          iRegL src1, immL_M1 m1,
                          rFlagsReg cr) %{
@@ -8493,6 +8511,7 @@
   %}
   ins_pipe(pipe_class_default);
 %}
+
 // Rotations

 instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
@@ -8555,9 +8574,143 @@
   ins_pipe(pipe_class_default);
 %}

+
+// rol expander
+
+instruct rolL_rReg(iRegL dst, iRegL src, iRegI shift, rFlagsReg cr)
+%{
+  effect(DEF dst, USE src, USE shift);
+
+  format %{ "rol    $dst, $src, $shift" %}
+  ins_cost(2*DEFAULT_COST);
+  ins_encode %{
+    __ subw(rscratch1, zr, as_Register($shift$$reg));
+    __ rorv(as_Register($dst$$reg), as_Register($src$$reg),
+	    rscratch1);
+    %}
+  ins_pipe(pipe_class_default);
+%}
+
+// rol expander
+
+instruct rolI_rReg(iRegI dst, iRegI src, iRegI shift, rFlagsReg cr)
+%{
+  effect(DEF dst, USE src, USE shift);
+
+  format %{ "rol    $dst, $src, $shift" %}
+  ins_cost(2*DEFAULT_COST);
+  ins_encode %{
+    __ subw(rscratch1, zr, as_Register($shift$$reg));
+    __ rorvw(as_Register($dst$$reg), as_Register($src$$reg),
+	    rscratch1);
+    %}
+  ins_pipe(pipe_class_default);
+%}
+
+instruct rolL_rReg_Var_C_64(iRegL dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr)
+%{
+  match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c_64 shift))));
+
+  expand %{
+    rolL_rReg(dst, src, shift, cr);
+  %}
+%}
+
+instruct rolL_rReg_Var_C0(iRegL dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+%{
+  match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c0 shift))));
+
+  expand %{
+    rolL_rReg(dst, src, shift, cr);
+  %}
+%}
+
+instruct rolI_rReg_Var_C_32(iRegL dst, iRegL src, iRegI shift, immI_32 c_32, rFlagsReg cr)
+%{
+  match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c_32 shift))));
+
+  expand %{
+    rolL_rReg(dst, src, shift, cr);
+  %}
+%}
+
+instruct rolI_rReg_Var_C0(iRegL dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+%{
+  match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c0 shift))));
+
+  expand %{
+    rolL_rReg(dst, src, shift, cr);
+  %}
+%}
+
+// ror expander
+
+instruct rorL_rReg(iRegL dst, iRegL src, iRegI shift, rFlagsReg cr)
+%{
+  effect(DEF dst, USE src, USE shift);
+
+  format %{ "ror    $dst, $src, $shift" %}
+  ins_cost(DEFAULT_COST);
+  ins_encode %{
+    __ rorv(as_Register($dst$$reg), as_Register($src$$reg),
+	    rscratch1);
+    %}
+  ins_pipe(pipe_class_default);
+%}
+
+// ror expander
+
+instruct rorI_rReg(iRegI dst, iRegI src, iRegI shift, rFlagsReg cr)
+%{
+  effect(DEF dst, USE src, USE shift);
+
+  format %{ "ror    $dst, $src, $shift" %}
+  ins_cost(DEFAULT_COST);
+  ins_encode %{
+    __ rorvw(as_Register($dst$$reg), as_Register($src$$reg),
+	    rscratch1);
+    %}
+  ins_pipe(pipe_class_default);
+%}
+
+instruct rorL_rReg_Var_C_64(iRegL dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr)
+%{
+  match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c_64 shift))));
+
+  expand %{
+    rorL_rReg(dst, src, shift, cr);
+  %}
+%}
+
+instruct rorL_rReg_Var_C0(iRegL dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+%{
+  match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c0 shift))));
+
+  expand %{
+    rorL_rReg(dst, src, shift, cr);
+  %}
+%}
+
+instruct rorI_rReg_Var_C_32(iRegL dst, iRegL src, iRegI shift, immI_32 c_32, rFlagsReg cr)
+%{
+  match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c_32 shift))));
+
+  expand %{
+    rorL_rReg(dst, src, shift, cr);
+  %}
+%}
+
+instruct rorI_rReg_Var_C0(iRegL dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+%{
+  match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c0 shift))));
+
+  expand %{
+    rorL_rReg(dst, src, shift, cr);
+  %}
+%}
+
 // Add/subtract (extended)

-
 instruct AddExtI(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
 %{
   match(Set dst (AddI src1 (ConvI2L src2)));
@@ -8806,15 +8959,11 @@
    %}
   ins_pipe(pipe_class_default);
 %}
+
 // END This section of the file is automatically generated. Do not edit --------------
 // Combined Long Mask and Right Shift (using UBFM)
 // TODO

-// Integer Rotate Instructions
-// TODO
-
-// Long Rotate Instructions
-// TODO

 // ============================================================================
 // Floating Point Arithmetic Instructions
diff -r 55c4c3af794e -r 2d0b9fa2cd76 src/cpu/aarch64/vm/aarch64_ad.m4
--- a/src/cpu/aarch64/vm/aarch64_ad.m4	Fri Oct 25 18:36:58 2013 +0100
+++ b/src/cpu/aarch64/vm/aarch64_ad.m4	Tue Oct 29 14:12:05 2013 +0000
@@ -1,4 +1,5 @@
 // BEGIN This section of the file is automatically generated. Do not edit --------------
+
 define(`BASE_SHIFT_INSN',
 `
 instruct $2$1_reg_$4_reg(iReg$1NoSp dst,
@@ -18,7 +19,7 @@
   %}

   ins_pipe(pipe_class_default);
-%}')
+%}')dnl
 define(`BASE_INVERTED_INSN',
 `
 instruct $2$1_reg_not_reg(iReg$1NoSp dst,
@@ -40,7 +41,7 @@
   %}

   ins_pipe(pipe_class_default);
-%}')
+%}')dnl
 define(`INVERTED_SHIFT_INSN',
 `
 instruct $2$1_reg_$4_not_reg(iReg$1NoSp dst,
@@ -63,7 +64,7 @@
   %}

   ins_pipe(pipe_class_default);
-%}')
+%}')dnl
 define(`NOT_INSN',
 `instruct reg$1_not_reg(iReg$1NoSp dst,
                          iReg$1 src1, imm$1_M1 m1,
@@ -80,29 +81,29 @@
   %}

   ins_pipe(pipe_class_default);
-%}')
+%}')dnl
 dnl
 define(`BOTH_SHIFT_INSNS',
 `BASE_SHIFT_INSN(I, $1, ifelse($2,andr,andw,$2w), $3, $4)
-BASE_SHIFT_INSN(L, $1, $2, $3, $4)')
+BASE_SHIFT_INSN(L, $1, $2, $3, $4)')dnl
 dnl
 define(`BOTH_INVERTED_INSNS',
 `BASE_INVERTED_INSN(I, $1, $2, $3, $4)
-BASE_INVERTED_INSN(L, $1, $2, $3, $4)')
+BASE_INVERTED_INSN(L, $1, $2, $3, $4)')dnl
 dnl
 define(`BOTH_INVERTED_SHIFT_INSNS',
 `INVERTED_SHIFT_INSN(I, $1, $2w, $3, $4, ~0, int)
-INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, long)')
+INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, long)')dnl
 dnl
 define(`ALL_SHIFT_KINDS',
 `BOTH_SHIFT_INSNS($1, $2, URShift, LSR)
 BOTH_SHIFT_INSNS($1, $2, RShift, ASR)
-BOTH_SHIFT_INSNS($1, $2, LShift, LSL)')
+BOTH_SHIFT_INSNS($1, $2, LShift, LSL)')dnl
 dnl
 define(`ALL_INVERTED_SHIFT_KINDS',
 `BOTH_INVERTED_SHIFT_INSNS($1, $2, URShift, LSR)
 BOTH_INVERTED_SHIFT_INSNS($1, $2, RShift, ASR)
-BOTH_INVERTED_SHIFT_INSNS($1, $2, LShift, LSL)')
+BOTH_INVERTED_SHIFT_INSNS($1, $2, LShift, LSL)')dnl
 dnl
 NOT_INSN(L, eon)
 NOT_INSN(I, eonw)
@@ -185,8 +186,9 @@
   %}
   ins_pipe(pipe_class_default);
 %}
-dnl
+
 // Rotations
+
 define(`EXTRACT_INSN',
 `instruct extr$3$1(iReg$1NoSp dst, iReg$1 src1, iReg$1 src2, immI lshift, immI rshift, rFlagsReg cr)
 %{
@@ -202,12 +204,73 @@
   %}
   ins_pipe(pipe_class_default);
 %}
-')
+')dnl
 EXTRACT_INSN(L, 63, Or, extr)
 EXTRACT_INSN(I, 31, Or, extrw)
 EXTRACT_INSN(L, 63, Add, extr)
 EXTRACT_INSN(I, 31, Add, extrw)
-dnl
+define(`ROL_EXPAND', `
+// $2 expander
+
+instruct $2$1_rReg(iReg$1 dst, iReg$1 src, iRegI shift, rFlagsReg cr)
+%{
+  effect(DEF dst, USE src, USE shift);
+
+  format %{ "$2    $dst, $src, $shift" %}
+  ins_cost(2*DEFAULT_COST);
+  ins_encode %{
+    __ subw(rscratch1, zr, as_Register($shift$$reg));
+    __ $3(as_Register($dst$$reg), as_Register($src$$reg),
+	    rscratch1);
+    %}
+  ins_pipe(pipe_class_default);
+%}')dnl
+define(`ROR_EXPAND', `
+// $2 expander
+
+instruct $2$1_rReg(iReg$1 dst, iReg$1 src, iRegI shift, rFlagsReg cr)
+%{
+  effect(DEF dst, USE src, USE shift);
+
+  format %{ "$2    $dst, $src, $shift" %}
+  ins_cost(DEFAULT_COST);
+  ins_encode %{
+    __ $3(as_Register($dst$$reg), as_Register($src$$reg),
+	    rscratch1);
+    %}
+  ins_pipe(pipe_class_default);
+%}')dnl
+define(ROL_INSN, `
+instruct $3$1_rReg_Var_C$2(iRegL dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
+%{
+  match(Set dst (Or$1 (LShift$1 src shift) (URShift$1 src (SubI c$2 shift))));
+
+  expand %{
+    $3L_rReg(dst, src, shift, cr);
+  %}
+%}')dnl
+define(ROR_INSN, `
+instruct $3$1_rReg_Var_C$2(iRegL dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
+%{
+  match(Set dst (Or$1 (URShift$1 src shift) (LShift$1 src (SubI c$2 shift))));
+
+  expand %{
+    $3L_rReg(dst, src, shift, cr);
+  %}
+%}')dnl
+ROL_EXPAND(L, rol, rorv)
+ROL_EXPAND(I, rol, rorvw)
+ROL_INSN(L, _64, rol)
+ROL_INSN(L, 0, rol)
+ROL_INSN(I, _32, rol)
+ROL_INSN(I, 0, rol)
+ROR_EXPAND(L, ror, rorv)
+ROR_EXPAND(I, ror, rorvw)
+ROR_INSN(L, _64, ror)
+ROR_INSN(L, 0, ror)
+ROR_INSN(I, _32, ror)
+ROR_INSN(I, 0, ror)
+
 // Add/subtract (extended)
 dnl ADD_SUB_EXTENDED(mode, size, add node, shift node, insn, shift type, wordsize
 define(`ADD_SUB_CONV', `
@@ -222,7 +285,7 @@
             as_Register($src2$$reg), ext::$5);
    %}
   ins_pipe(pipe_class_default);
-%}')
+%}')dnl
 ADD_SUB_CONV(I,L,Add,add,sxtw);
 ADD_SUB_CONV(I,L,Sub,sub,sxtw);
 dnl
@@ -273,4 +336,5 @@
 ADD_SUB_ZERO_EXTEND(L,255,Sub,sub,uxtb)
 ADD_SUB_ZERO_EXTEND(L,65535,Sub,sub,uxth)
 ADD_SUB_ZERO_EXTEND(L,4294967295,Sub,sub,uxtw)
+
 // END This section of the file is automatically generated. Do not edit --------------


From adinn at redhat.com  Tue Oct 29 08:49:45 2013
From: adinn at redhat.com (adinn at redhat.com)
Date: Tue, 29 Oct 2013 15:49:45 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: corrected
	register match rules, ensured rule outputs are all iRegXNoSp
Message-ID: <20131029155006.36659627F1@hg.openjdk.java.net>

Changeset: 74bfec34e208
Author:    adinn
Date:      2013-10-29 15:49 +0000
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/74bfec34e208

corrected register match rules, ensured rule outputs are all iRegXNoSp

the iRegPXXX operand declarations were matching registers the wrong
way round and as a consequence were allowing matches which were
unnecessary. they are now correct and this avoids unnecessary work in
the generated DFA code.

more seriously, some of the rules were declaring their outputs with
type iRegX instead of iRegXNoSp i.e. allowing the allocator to
allocate the destination output from the special register set R27 to
R31. this results in an asser in the register pressure computation in
build_ifg_physical. specifically, this happens when a which rule
generates an output declared with type iRegX produces a live range
which crosses a VM callout. the fat projection following the callout
kills the SOC registers but does not remove the special registers from
the range, leaving the range still live even when it ought to have
been yanked. this is caught by the assert because the register
pressure for the block gets decremented by the amount associated with
the yanked projection and it does not tally with the count associated
with the live ranges.

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/c2_globals_aarch64.hpp



From adinn at redhat.com  Tue Oct 29 09:03:02 2013
From: adinn at redhat.com (Andrew Dinn)
Date: Tue, 29 Oct 2013 16:03:02 +0000
Subject: [aarch64-port-dev ] Fixed register pressure problem at last!
Message-ID: <526FDC36.1000507@redhat.com>

I finally worked out what was causing the register pressure problem
which was causing eclipse to break. The root problem was to do with a
few of the instructions definitions which were still declaring their
output register dst to be of type iRegX instead of iRegXNoSp (where X is
one of P, L or I). The specific instruction which was causing the
problem was ConvI2B but there were about half a dozen others which also
needed to be corrected.

This manifests as a register pressure error during construction of the
physical interference graph in the situation where the instruction
produces a live range which crosses a callout to the VM. The callout is
followed by a fat projection (special type of MachProj node) which is
meant to kill all the save-on-call (SOC) registers (i.e. cause them to
be spilled). Since the live range built by the instruction includes
R0-R31, which are no-save (NS), the kill merely reduces it to a live
range containing R27-R31 rather than an empty range. The register
pressure count for the block is reduced by 1 after the fat projection is
processed but the register pressure count associated with the live
ranges remains as it was. Luckily an assert detects this disparity.

I am continuing to run Eclipse on beyond this point. Perhaps we could
consider including Andrew's optimizations now? That would at least mean
that I hit Eclipse problems quicker (since it substantially reduces the
instruction count for the compiled code).
regards,


Andrew Dinn
-----------



From aph at redhat.com  Tue Oct 29 09:09:27 2013
From: aph at redhat.com (aph at redhat.com)
Date: Tue, 29 Oct 2013 16:09:27 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: 20 new changesets
Message-ID: <20131029161021.14CBA627F2@hg.openjdk.java.net>

Changeset: 7bf52c3b41bf
Author:    aph
Date:      2013-10-16 17:06 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/7bf52c3b41bf

Add/subtract (shifted regsiter) and Logical (shifted regsiter)

! make/linux/makefiles/adlc.make
! src/cpu/aarch64/vm/aarch64.ad
+ src/cpu/aarch64/vm/aarch64_ad.m4

Changeset: effb95dde9f8
Author:    aph
Date:      2013-10-17 13:58 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/effb95dde9f8

Bitfield moves and rotations

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/aarch64_ad.m4
! src/cpu/aarch64/vm/assembler_aarch64.hpp

Changeset: 03f55b66e8cf
Author:    aph
Date:      2013-10-17 16:33 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/03f55b66e8cf

Merge

- agent/src/share/classes/sun/jvm/hotspot/debugger/cdbg/basic/amd64/AMD64CFrame.java
- agent/src/share/classes/sun/jvm/hotspot/debugger/cdbg/basic/x86/X86CFrame.java
- make/bsd/makefiles/launcher.make
! make/linux/makefiles/adlc.make
- make/linux/makefiles/launcher.make
- make/solaris/makefiles/launcher.make
- make/windows/makefiles/launcher.make
! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
! src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
- src/os/posix/launcher/java_md.c
- src/os/posix/launcher/java_md.h
- src/os/posix/launcher/launcher.script
- src/os/windows/launcher/java_md.c
- src/os/windows/launcher/java_md.h
- src/os_cpu/bsd_x86/vm/bsd_x86_32.ad
- src/os_cpu/bsd_x86/vm/bsd_x86_64.ad
- src/os_cpu/linux_sparc/vm/assembler_linux_sparc.cpp
- src/os_cpu/linux_x86/vm/linux_x86_32.ad
- src/os_cpu/linux_x86/vm/linux_x86_64.ad
- src/os_cpu/solaris_sparc/vm/assembler_solaris_sparc.cpp
- src/os_cpu/solaris_sparc/vm/solaris_sparc.ad
- src/os_cpu/solaris_x86/vm/solaris_x86_32.ad
- src/os_cpu/solaris_x86/vm/solaris_x86_64.ad
- src/os_cpu/windows_x86/vm/windows_x86_32.ad
- src/os_cpu/windows_x86/vm/windows_x86_64.ad
- src/share/tools/launcher/java.c
- src/share/tools/launcher/java.h
- src/share/tools/launcher/jli_util.c
- src/share/tools/launcher/jli_util.h
- src/share/tools/launcher/wildcard.c
- src/share/tools/launcher/wildcard.h
- src/share/vm/classfile/genericSignatures.cpp
- src/share/vm/classfile/genericSignatures.hpp
- src/share/vm/gc_implementation/parallelScavenge/parMarkBitMap.inline.hpp
- src/share/vm/runtime/aprofiler.cpp
- src/share/vm/runtime/aprofiler.hpp
- src/share/vm/trace/traceEventTypes.hpp
- test/gc/metaspace/ClassMetaspaceSizeInJmapHeap.java
- test/runtime/6878713/Test6878713.sh
- test/runtime/6878713/testcase.jar
- test/runtime/7020373/Test7020373.sh
- test/runtime/7020373/testcase.jar
- test/runtime/7051189/Xchecksig.sh
- test/runtime/7158804/Test7158804.sh
- test/runtime/7196045/Test7196045.java
- test/runtime/8000968/Test8000968.sh
- test/runtime/8003985/Test8003985.java

Changeset: 7ad16844c57e
Author:    aph
Date:      2013-10-17 16:46 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/7ad16844c57e

Use XOR encoding for compressed class pointers.

! src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
! src/cpu/aarch64/vm/macroAssembler_aarch64.hpp

Changeset: 0fdfde044549
Author:    aph
Date:      2013-10-17 18:49 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/0fdfde044549

Restore LR for use by C2 runtime

! src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp

Changeset: 78123d7fe1c5
Author:    aph
Date:      2013-10-22 10:21 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/78123d7fe1c5

Fix offset overflows in profile counters.

! src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp

Changeset: c9d218a8476d
Author:    aph
Date:      2013-10-22 10:22 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/c9d218a8476d

Fix offset overflow in addptr.

! src/cpu/aarch64/vm/macroAssembler_aarch64.hpp

Changeset: 919191537d1c
Author:    aph
Date:      2013-10-22 10:22 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/919191537d1c

More shift/add/mask patterns.

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/aarch64_ad.m4

Changeset: c5a148cea134
Author:    aph
Date:      2013-10-22 18:02 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/c5a148cea134

Move aarch64_enc_save_pc

! src/cpu/aarch64/vm/aarch64.ad

Changeset: a669c60b445e
Author:    aph
Date:      2013-10-22 18:37 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/a669c60b445e

Whitespace and minor name changes only.

! src/cpu/aarch64/vm/aarch64.ad

Changeset: 3a03874840c6
Author:    aph
Date:      2013-10-22 18:52 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/3a03874840c6

Add indIndexScaledOffsetI2L addessing mode

! src/cpu/aarch64/vm/aarch64.ad

Changeset: b962569eb666
Author:    aph
Date:      2013-10-24 14:05 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/b962569eb666

Temporary commit before reorganaization.

! make/linux/makefiles/adlc.make
! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/aarch64_ad.m4

Changeset: 92b2e1520bcb
Author:    aph
Date:      2013-10-25 11:22 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/92b2e1520bcb

Record work in progress

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/stubGenerator_aarch64.cpp

Changeset: d29d243a63e1
Author:    aph
Date:      2013-10-25 12:09 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/d29d243a63e1

Record work in progress

! src/cpu/aarch64/vm/aarch64.ad

Changeset: 543d6fc7ce4a
Author:    aph
Date:      2013-10-25 14:21 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/543d6fc7ce4a

Record work in progress

! src/cpu/aarch64/vm/aarch64.ad
+ src/cpu/aarch64/vm/ad_encode.m4

Changeset: 0e127d01f89a
Author:    aph
Date:      2013-10-25 16:27 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/0e127d01f89a

Merge

! .hgtags
! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/c2_globals_aarch64.hpp

Changeset: d4c02a1427a6
Author:    aph
Date:      2013-10-25 16:31 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/d4c02a1427a6

Merge

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
! src/cpu/aarch64/vm/macroAssembler_aarch64.hpp

Changeset: 55c4c3af794e
Author:    aph
Date:      2013-10-25 18:36 +0100
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/55c4c3af794e

Add a bunch of missing JVMTI methods.

! src/cpu/aarch64/vm/interp_masm_aarch64.cpp
! src/cpu/aarch64/vm/templateTable_aarch64.cpp

Changeset: 2d0b9fa2cd76
Author:    aph
Date:      2013-10-29 14:12 +0000
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/2d0b9fa2cd76

Variable rotate instructions

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/aarch64_ad.m4

Changeset: 2c9491db660f
Author:    aph
Date:      2013-10-29 16:06 +0000
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/2c9491db660f

merge

! src/cpu/aarch64/vm/aarch64.ad



From andy.johnson at linaro.org  Tue Oct 29 17:04:46 2013
From: andy.johnson at linaro.org (Andy Johnson)
Date: Tue, 29 Oct 2013 17:04:46 -0700
Subject: [aarch64-port-dev ] printf format conflict
Message-ID: <CABOt5x=+EfsTDTvTMXZQFTWG1QaTSBQbVXZBpVJ5+ev4ef=2DQ@mail.gmail.com>

I got an error while doing a sim_compile.  It complained about a type
conflict between the argument and the corresponding format.  The following
patch solves the problem:

# HG changeset patch
# User andy johnson andy.johnson at linaro.org
# Date 1383091105 0
# Node ID 88d8843ae27ffb6f66baf16dfc9b3b34775b91c9
# Parent  2c9491db660f51559026478f7053a0e1054cb277
Fixed conflicting types in printf format argument.

diff -r 2c9491db660f -r 88d8843ae27f src/cpu/aarch64/vm/frame_aarch64.cpp
--- a/src/cpu/aarch64/vm/frame_aarch64.cpp    Tue Oct 29 16:06:56 2013 +0000
+++ b/src/cpu/aarch64/vm/frame_aarch64.cpp    Tue Oct 29 23:58:25 2013 +0000
@@ -713,7 +713,7 @@
 #define DESCRIBE_FP_OFFSET(name)                \
   {                                \
     unsigned long *p = (unsigned long *)fp;            \
-    printf("0x%016lx 0x%016lx %s\n", p + frame::name##_offset,    \
+    printf("0x%016lx 0x%016lx %s\n", (unsigned long)(p +
frame::name##_offset),\
        p[frame::name##_offset], #name);            \
   }


From thuhc at yahoo.com  Tue Oct 29 20:20:35 2013
From: thuhc at yahoo.com (Cao Hoang Thu)
Date: Tue, 29 Oct 2013 20:20:35 -0700 (PDT)
Subject: [aarch64-port-dev ] Problematic frame: j
	sun.reflect.MethodAccessorGenerator.generate(Ljava/lang/Class;
	Ljava/lang/String; [Ljava/lang/Class; Ljava/lang/Class;
	[Ljava/lang/Class; IZZLjava/lang/Class;
	)Lsun/reflect/MagicAccessorImpl; +755
In-Reply-To: <CABOt5x=+EfsTDTvTMXZQFTWG1QaTSBQbVXZBpVJ5+ev4ef=2DQ@mail.gmail.com>
References: <CABOt5x=+EfsTDTvTMXZQFTWG1QaTSBQbVXZBpVJ5+ev4ef=2DQ@mail.gmail.com>
Message-ID: <1383103235.31351.YahooMailNeo@web164604.mail.gq1.yahoo.com>

I got this error with current source

# java -Xmx1024m -jar dacapo-9.12-bach.jar lusearch


#
# A fatal error has been detected by the Java Runtime Environment:
#
# ?SIGSEGV (0xb) at pc=0x0000007fa5094be8, pid=1663, tid=547052581392
#
# JRE version: OpenJDK Runtime Environment (8.0) (build 1.8.0-internal-thcao_2013_10_30_09_31-b00)
# Java VM: OpenJDK 64-Bit Client VM (25.0-b52 mixed mode linux-aarch64 )
# Problematic frame:
# j ?sun.reflect.MethodAccessorGenerator.generate(Ljava/lang/Class;Ljava/lang/String;[Ljava/lang/Class;Ljava/lang/Class;[Ljava/lang/Class;IZZLjava/lang/Class;)Lsun/reflect/MagicAccessorImpl;+755
#
# Failed to write core dump. Core dumps have been disabled. To enable core dumping, try "ulimit -c unlimited" before starting Java again
#
# An error report file with more information is saved as:
# /root/hs_err_pid1663.log
[thread 547054678544 also had an error]
[thread 547056775696 also had an error]
#
# If you would like to submit a bug report, please visit:
# ? http://bugreport.sun.com/bugreport/crash.jsp
#
Aborted

Regards,
Thu Cao


From thuhc at yahoo.com  Wed Oct 30 00:31:14 2013
From: thuhc at yahoo.com (Cao Hoang Thu)
Date: Wed, 30 Oct 2013 00:31:14 -0700 (PDT)
Subject: [aarch64-port-dev ] Problematic frame:
	j	sun.reflect.MethodAccessorGenerator.generate(Ljava/lang/Class;
	Ljava/lang/String; [Ljava/lang/Class; Ljava/lang/Class;
	[Ljava/lang/Class; IZZLjava/lang/Class;
	)Lsun/reflect/MagicAccessorImpl; +755
In-Reply-To: <1383103235.31351.YahooMailNeo@web164604.mail.gq1.yahoo.com>
References: <CABOt5x=+EfsTDTvTMXZQFTWG1QaTSBQbVXZBpVJ5+ev4ef=2DQ@mail.gmail.com>
	<1383103235.31351.YahooMailNeo@web164604.mail.gq1.yahoo.com>
Message-ID: <1383118274.59647.YahooMailNeo@web164602.mail.gq1.yahoo.com>

But I run this command with build server-release, it passed
openjdk version "1.8.0-internal"
OpenJDK Runtime Environment (build 1.8.0-internal-thcao_2013_10_30_10_30-b00)
OpenJDK 64-Bit Server VM (build 25.0-b52, mixed mode)


#java -Xmx1024m -jar dacapo-9.12-bach.jar lusearch
===== DaCapo 9.12 lusearch starting =====
4 query batches completed
8 query batches completed
12 query batches completed
16 query batches completed
20 query batches completed
24 query batches completed
28 query batches completed
32 query batches completed
36 query batches completed
40 query batches completed
44 query batches completed
48 query batches completed
52 query batches completed
56 query batches completed
60 query batches completed
64 query batches completed
===== DaCapo 9.12 lusearch PASSED in 5760 msec =====



________________________________
 From: Cao Hoang Thu <thuhc at yahoo.com>
To: "aarch64-port-dev at openjdk.java.net" <aarch64-port-dev at openjdk.java.net> 
Sent: Wednesday, October 30, 2013 10:20 AM
Subject: [aarch64-port-dev ] Problematic frame: j	sun.reflect.MethodAccessorGenerator.generate(Ljava/lang/Class;	Ljava/lang/String; [Ljava/lang/Class; Ljava/lang/Class;	[Ljava/lang/Class; IZZLjava/lang/Class;	)Lsun/reflect/MagicAccessorImpl; +755
 

I got this error with current source

# java -Xmx1024m -jar dacapo-9.12-bach.jar lusearch


#
# A fatal error has been detected by the Java Runtime Environment:
#
# ?SIGSEGV (0xb) at pc=0x0000007fa5094be8, pid=1663, tid=547052581392
#
# JRE version: OpenJDK Runtime Environment (8.0) (build 1.8.0-internal-thcao_2013_10_30_09_31-b00)
# Java VM: OpenJDK 64-Bit Client VM (25.0-b52 mixed mode linux-aarch64 )
# Problematic frame:
# j ?sun.reflect.MethodAccessorGenerator.generate(Ljava/lang/Class;Ljava/lang/String;[Ljava/lang/Class;Ljava/lang/Class;[Ljava/lang/Class;IZZLjava/lang/Class;)Lsun/reflect/MagicAccessorImpl;+755
#
# Failed to write core dump. Core dumps have been disabled. To enable core dumping, try "ulimit -c unlimited" before starting Java again
#
# An error report file with more information is saved as:
# /root/hs_err_pid1663.log
[thread 547054678544 also had an error]
[thread 547056775696 also had an error]
#
# If you would like to submit a bug report, please visit:
# ? http://bugreport.sun.com/bugreport/crash.jsp
#
Aborted

Regards,
Thu Cao

From aph at redhat.com  Wed Oct 30 01:25:35 2013
From: aph at redhat.com (Andrew Haley)
Date: Wed, 30 Oct 2013 08:25:35 +0000
Subject: [aarch64-port-dev ] printf format conflict
In-Reply-To: <CABOt5x=+EfsTDTvTMXZQFTWG1QaTSBQbVXZBpVJ5+ev4ef=2DQ@mail.gmail.com>
References: <CABOt5x=+EfsTDTvTMXZQFTWG1QaTSBQbVXZBpVJ5+ev4ef=2DQ@mail.gmail.com>
Message-ID: <5270C27F.4050906@redhat.com>

On 10/30/2013 12:04 AM, Andy Johnson wrote:
> I got an error while doing a sim_compile.  It complained about a type
> conflict between the argument and the corresponding format.  The following
> patch solves the problem:
> 
> # HG changeset patch
> # User andy johnson andy.johnson at linaro.org
> # Date 1383091105 0
> # Node ID 88d8843ae27ffb6f66baf16dfc9b3b34775b91c9
> # Parent  2c9491db660f51559026478f7053a0e1054cb277
> Fixed conflicting types in printf format argument.

OK, thanks.

Andrew.




From aph at redhat.com  Wed Oct 30 01:48:38 2013
From: aph at redhat.com (aph at redhat.com)
Date: Wed, 30 Oct 2013 08:48:38 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: Fix Add/subtract
	(extended) pattern	which did not match anything
Message-ID: <20131030084906.E492F62820@hg.openjdk.java.net>

Changeset: ed0fe5cfe272
Author:    aph
Date:      2013-10-30 08:47 +0000
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/ed0fe5cfe272

Fix Add/subtract (extended) pattern which did not match anything

! src/cpu/aarch64/vm/aarch64.ad
! src/cpu/aarch64/vm/aarch64_ad.m4



From aph at redhat.com  Wed Oct 30 10:53:01 2013
From: aph at redhat.com (Andrew Haley)
Date: Wed, 30 Oct 2013 17:53:01 +0000
Subject: [aarch64-port-dev ] Clone shifts on addressing modes
Message-ID: <5271477D.3010004@redhat.com>

This patch improves code for loads and stores, turning this:

     sxtw       x10, w2
     lsl        x10, x10, #1
     add        xmethod, x4, x10
     ldrsh      w13, [xmethod,#24]  ;*saload
     cmp        w2, w11
     b.cs       0x00007fffed199480  ;*caload
     add        x10, x5, x10
     ldrh       w10, [x10,#24]

into this:

     add    xscratch1, x4, #0x18
     ldrsh      w13, [xscratch1,w2,sxtw #1]   ;*saload
     cmp        w2, w11
     b.cs       0x00007fffed199478  ;*caload
     add        xscratch1, x5, #0x18
     ldrh       w10, [xscratch1,w2,sxtw #1]

Andrew.



# HG changeset patch
# User aph
# Date 1383155220 0
# Node ID b92e284531b2d7aa6bc8b94405a5488a28b33f4f
# Parent  ed0fe5cfe272133e22484d7c99375e1099e4cabb
Clone shifts on addressing modes

diff -r ed0fe5cfe272 -r b92e284531b2 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 30 08:47:21 2013 +0000
+++ b/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 30 17:47:00 2013 +0000
@@ -1591,7 +1591,7 @@
 // Should the Matcher clone shifts on addressing modes, expecting them
 // to be subsumed into complex addressing expressions or compute them
 // into registers?  True for Intel but false for most RISCs
-const bool Matcher::clone_shift_expressions = false;
+const bool Matcher::clone_shift_expressions = true;

 // Do we need to mask the count passed to shift instructions or does
 // the cpu only look at the lower 5/6 bits anyway?


From aph at redhat.com  Wed Oct 30 10:56:27 2013
From: aph at redhat.com (aph at redhat.com)
Date: Wed, 30 Oct 2013 17:56:27 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: Clone shifts on
	addressing modes
Message-ID: <20131030175655.BE37B6283F@hg.openjdk.java.net>

Changeset: b92e284531b2
Author:    aph
Date:      2013-10-30 17:47 +0000
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/b92e284531b2

Clone shifts on addressing modes

! src/cpu/aarch64/vm/aarch64.ad



From aph at redhat.com  Wed Oct 30 11:07:13 2013
From: aph at redhat.com (aph at redhat.com)
Date: Wed, 30 Oct 2013 18:07:13 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: Fixed
	conflicting types in printf	format argument.
Message-ID: <20131030180720.B986862840@hg.openjdk.java.net>

Changeset: 3857ada3f2e9
Author:    andy johnson andy.johnson at linaro.org
Date:      2013-10-30 18:06 +0000
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/3857ada3f2e9

Fixed conflicting types in printf format argument.

! src/cpu/aarch64/vm/frame_aarch64.cpp



From aph at redhat.com  Wed Oct 30 11:13:29 2013
From: aph at redhat.com (Andrew Haley)
Date: Wed, 30 Oct 2013 18:13:29 +0000
Subject: [aarch64-port-dev ] Problematic frame: j
 sun.reflect.MethodAccessorGenerator.generate(Ljava/lang/Class;
 Ljava/lang/String; [Ljava/lang/Class; Ljava/lang/Class; [Ljava/lang/Class;
 IZZLjava/lang/Class; )Lsun/reflect/MagicAccessorImpl; +755
In-Reply-To: <1383103235.31351.YahooMailNeo@web164604.mail.gq1.yahoo.com>
References: <CABOt5x=+EfsTDTvTMXZQFTWG1QaTSBQbVXZBpVJ5+ev4ef=2DQ@mail.gmail.com>
	<1383103235.31351.YahooMailNeo@web164604.mail.gq1.yahoo.com>
Message-ID: <52714C49.7000605@redhat.com>

On 10/30/2013 03:20 AM, Cao Hoang Thu wrote:
> I got this error with current source
> 
> # java -Xmx1024m -jar dacapo-9.12-bach.jar lusearch

OK, I'm trying it now.

What build options did you use?

Where is dacapo-9.12-bach.jar from?

Andrew.



From thuhc at yahoo.com  Wed Oct 30 19:55:16 2013
From: thuhc at yahoo.com (Cao Hoang Thu)
Date: Wed, 30 Oct 2013 19:55:16 -0700 (PDT)
Subject: [aarch64-port-dev ] Problematic frame: j
	sun.reflect.MethodAccessorGenerator.generate(Ljava/lang/Class;
	Ljava/lang/String; [Ljava/lang/Class; Ljava/lang/Class;
	[Ljava/lang/Class; IZZLjava/lang/Class;
	)Lsun/reflect/MagicAccessorImpl; +755
In-Reply-To: <52714C49.7000605@redhat.com>
References: <CABOt5x=+EfsTDTvTMXZQFTWG1QaTSBQbVXZBpVJ5+ev4ef=2DQ@mail.gmail.com>
	<1383103235.31351.YahooMailNeo@web164604.mail.gq1.yahoo.com>
	<52714C49.7000605@redhat.com>
Message-ID: <1383188116.66938.YahooMailNeo@web164601.mail.gq1.yahoo.com>

Hi Andrew,

You can get dacapo-9.12-bach.jar from?http://sourceforge.net/projects/dacapobench/files/9.12-bach/
I build cross compile:

OPENJDK8_DEBUG_LEVEL=release

OPENJDK8_JVM_VARIANTS=client

HOST_JDK_HOME=jdk-7u25-linux-x64


#./configure \
? ? ? ? ? ? ? ? --with-debug-level=$(OPENJDK8_DEBUG_LEVEL) \
? ? ? ? ? ? ? ? --with-jvm-variants=$(OPENJDK8_JVM_VARIANTS) \
? ? ? ? ? ? ? ? --enable-unlimited-crypto \
? ? ? ? ? ? ? ? --openjdk-target=$(AARCH64_TOOLCHAIN_PREFIX) \
? ? ? ? ? ? ? ? --with-cacerts-file=$(HOST_JDK_HOME)/jre/lib/security/cacerts \
? ? ? ? ? ? ? ? --with-stdc++lib=dynamic \
? ? ? ? ? ? ? ? --with-boot-jdk=$(HOST_JDK_HOME) \
? ? ? ? ? ? ? ? --with-sys-root=$(STAGING_DIR) \
? ? ? ? ? ? ? ? --with-extra-cflags=$(EXTRA_CFLAGS) \
? ? ? ? ? ? ? ? --with-extra-cxxflags=$(EXTRA_CXXFLAGS) \
? ? ? ? ? ? ? ? --with-extra-ldflags=$(EXTRA_LDFLAGS) \
? ? ? ? ? ? ? ? --disable-ccache \

#make images

Regards,
Thu Cao

________________________________
 From: Andrew Haley <aph at redhat.com>
To: Cao Hoang Thu <thuhc at yahoo.com> 
Cc: "aarch64-port-dev at openjdk.java.net" <aarch64-port-dev at openjdk.java.net> 
Sent: Thursday, October 31, 2013 1:13 AM
Subject: Re: [aarch64-port-dev ] Problematic frame: j sun.reflect.MethodAccessorGenerator.generate(Ljava/lang/Class; Ljava/lang/String; [Ljava/lang/Class; Ljava/lang/Class; [Ljava/lang/Class; IZZLjava/lang/Class; )Lsun/reflect/MagicAccessorImpl; +755
 

On 10/30/2013 03:20 AM, Cao Hoang Thu wrote:

> I got this error with current source
> 
> # java -Xmx1024m -jar dacapo-9.12-bach.jar lusearch

OK, I'm trying it now.

What build options did you use?

Where is dacapo-9.12-bach.jar from?

Andrew.

From aph at redhat.com  Thu Oct 31 00:56:14 2013
From: aph at redhat.com (Andrew Haley)
Date: Thu, 31 Oct 2013 07:56:14 +0000
Subject: [aarch64-port-dev ] Clone shifts on addressing modes
In-Reply-To: <5271477D.3010004@redhat.com>
References: <5271477D.3010004@redhat.com>
Message-ID: <52720D1E.5090507@redhat.com>

On 10/30/2013 05:53 PM, Andrew Haley wrote:
> This patch improves code for loads and stores

But it makes array accesses in loops worse.  :-(

Bah, I'm going to have to back this out and think of something
else.

Andrew.




From adinn at redhat.com  Thu Oct 31 03:55:45 2013
From: adinn at redhat.com (adinn at redhat.com)
Date: Thu, 31 Oct 2013 10:55:45 +0000
Subject: [aarch64-port-dev ] hg: aarch64-port/jdk8/hotspot: Added missing
	AbsD and AbsF	instructions
Message-ID: <20131031105630.20AB362872@hg.openjdk.java.net>

Changeset: 4de6d9b68bc3
Author:    adinn
Date:      2013-10-31 10:52 +0000
URL:       http://hg.openjdk.java.net/aarch64-port/jdk8/hotspot/rev/4de6d9b68bc3

Added missing AbsD and AbsF instructions

! src/cpu/aarch64/vm/aarch64.ad



From andrew.mcdermott at linaro.org  Thu Oct 31 12:26:46 2013
From: andrew.mcdermott at linaro.org (Andrew McDermott)
Date: Thu, 31 Oct 2013 12:26:46 -0700
Subject: [aarch64-port-dev ] Building with BUILTIN_SIM generates SIGSEGV
	when running java -version
Message-ID: <CABn4x4P+e=dStyKHNroAtoHC9wcVUJ=vwBV+WH_BNXW8JYOzMA@mail.gmail.com>

Hi,

I'm building the tip of aarch64-port via the sim_configure/sim_compile
scripts but running `java -version' leads to a crash[1].

The error stems from an assert() in:

  jdk8/hotspot/src/share/vm/memory/allocation.cpp:692

  #ifndef ALLOW_OPERATOR_NEW_USAGE
  void* operator new(size_t size) throw() {
    assert(false, "Should not call global operator new");
    return 0;
  }

Digging a little deeper I see that in:

  jdk8/hotspot/make/linux/makefiles/aarch64.make

we have:

  ifeq ($(BUILTIN_SIM), true)
  CFLAGS  += -DBUILTIN_SIM
  #CFLAGS  += -DBUILTIN_SIM -DALLOW_OPERATOR_NEW_USAGE
  endif

Is there any reason why the "-DALLOW_OPERATOR_NEW_USAGE" is not enabled by
default. If I add this then the SEGV goes away (obviously!).  Or, if this
is deliberately disabled, is there any value if I create a patch which
replaces uses of 'new char[]' with, say, class stringStream in parts of the
builtin simulator code?

[1] java -version

# To suppress the following error report, specify this argument
# after -XX: or in .hotspotrc:  SuppressErrorAt=/allocation.cpp:697
#
# A fatal error has been detected by the Java Runtime Environment:
#
#  Internal Error
(/home/aim/jdk8/hotspot/src/share/vm/memory/allocation.cpp:697), pid=12534,
tid=140431156107008
#  assert(false) failed: Should not call global operator new[]
#
# JRE version:  (8.0) (build )
# Java VM: OpenJDK 64-Bit Client VM (25.0-b52-debug mixed mode
linux-aarch64 )
# Failed to write core dump. Core dumps have been disabled. To enable core
dumping, try "ulimit -c unlimited" before starting Java again
#
# An error report file with more information is saved as:
# /home/aim/jdk8/hs_err_pid12534.log
#
# If you would like to submit a bug report, please visit:
#   http://bugreport.sun.com/bugreport/crash.jsp
#
Current thread is 140431156107008
Dumping core ...
LOOPING...

-- 
andy


From andrew.mcdermott at linaro.org  Thu Oct 31 14:02:54 2013
From: andrew.mcdermott at linaro.org (Andrew McDermott)
Date: Thu, 31 Oct 2013 14:02:54 -0700
Subject: [aarch64-port-dev ] Building with BUILTIN_SIM generates SIGSEGV
	when running java -version
In-Reply-To: <CABn4x4P+e=dStyKHNroAtoHC9wcVUJ=vwBV+WH_BNXW8JYOzMA@mail.gmail.com>
References: <CABn4x4P+e=dStyKHNroAtoHC9wcVUJ=vwBV+WH_BNXW8JYOzMA@mail.gmail.com>
Message-ID: <B92A0793-2D6B-40A9-BD62-AAD566E38BE1@linaro.org>


Please disregard this - I had local changes which I had not reverted.

> Hi,
> 
> I'm building the tip of aarch64-port via the sim_configure/sim_compile scripts but running `java -version' leads to a crash[1]. 
> 
> The error stems from an assert() in:
> 
>   jdk8/hotspot/src/share/vm/memory/allocation.cpp:692
> 
>   #ifndef ALLOW_OPERATOR_NEW_USAGE
>   void* operator new(size_t size) throw() {
>     assert(false, "Should not call global operator new");
>     return 0;
>   }
> 
> Digging a little deeper I see that in:
> 
>   jdk8/hotspot/make/linux/makefiles/aarch64.make
> 
> we have:
> 
>   ifeq ($(BUILTIN_SIM), true)
>   CFLAGS  += -DBUILTIN_SIM
>   #CFLAGS  += -DBUILTIN_SIM -DALLOW_OPERATOR_NEW_USAGE
>   endif
> 
> Is there any reason why the "-DALLOW_OPERATOR_NEW_USAGE" is not enabled by default. If I add this then the SEGV goes away (obviously!).  Or, if this is deliberately disabled, is there any value if I create a patch which replaces uses of 'new char[]' with, say, class stringStream in parts of the builtin simulator code?
> 
> [1] java -version
> 
> # To suppress the following error report, specify this argument
> # after -XX: or in .hotspotrc:  SuppressErrorAt=/allocation.cpp:697
> #
> # A fatal error has been detected by the Java Runtime Environment:
> #
> #  Internal Error (/home/aim/jdk8/hotspot/src/share/vm/memory/allocation.cpp:697), pid=12534, tid=140431156107008
> #  assert(false) failed: Should not call global operator new[]
> #
> # JRE version:  (8.0) (build )
> # Java VM: OpenJDK 64-Bit Client VM (25.0-b52-debug mixed mode linux-aarch64 )
> # Failed to write core dump. Core dumps have been disabled. To enable core dumping, try "ulimit -c unlimited" before starting Java again
> #
> # An error report file with more information is saved as:
> # /home/aim/jdk8/hs_err_pid12534.log
> #
> # If you would like to submit a bug report, please visit:
> #   http://bugreport.sun.com/bugreport/crash.jsp
> #
> Current thread is 140431156107008
> Dumping core ...
> LOOPING...
> 
> -- 
> andy
> 
>