[aarch64-port-dev ] C1: Correct half word types in loads and stores

[Andrew Haley]

We were writing halfword types wit the wrong modes.

Andrew.


# HG changeset patch
# User aph
# Date 1381309495 -3600
# Node ID 5db717e716d938bccf57ddd9558c66b9b14d56c8
# Parent  1b73f7fb6f30402ed55ac131125d5d9d28a9c710
Correct half word types in loads and stores

diff -r 1b73f7fb6f30 -r 5db717e716d9 src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Thu Oct 03 14:33:45 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Wed Oct 09 10:04:55 2013 +0100
@@ -2756,7 +2756,7 @@

       case T_CHAR:    // fall through
       case T_SHORT:
-	__ stlrw(src->as_register(), rscratch1);
+	__ stlrh(src->as_register(), rscratch1);
 	break;

       default:
@@ -2802,7 +2802,7 @@

     case T_CHAR:    // fall through
     case T_SHORT:
-      __ ldarw(dest->as_register(), rscratch1);
+      __ ldarh(dest->as_register(), rscratch1);
       break;

     case T_FLOAT: