[aarch64-port-dev ] aarch64.ad: Rotate instructions and a few minor twiddles
Andrew Haley
aph at redhat.com
Tue Oct 29 07:15:30 PDT 2013
Rotate variable, mainly, and a few corrections and additions.
Andrew.
# HG changeset patch
# User aph
# Date 1383055925 0
# Node ID 2d0b9fa2cd76ca4a9d397e7d2573e72bdf85de2b
# Parent 55c4c3af794e1d7e999e530823e02c5907eaa376
Variable rotate instructions
diff -r 55c4c3af794e -r 2d0b9fa2cd76 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Fri Oct 25 18:36:58 2013 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad Tue Oct 29 14:12:05 2013 +0000
@@ -3478,6 +3478,16 @@
interface(CONST_INTER);
%}
+operand immI_64()
+%{
+ predicate(n->get_int() == 64);
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
operand immI_255()
%{
predicate(n->get_int() == 255);
@@ -6974,10 +6984,26 @@
ins_pipe(pipe_class_default);
%}
+instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr)
+%{
+ match(Set dst (MulHiL src1 src2));
+
+ ins_cost(2 * DEFAULT_COST);
+ format %{ "smulh $dst, $src1, $src2, \t# mulhi" %}
+
+ ins_encode %{
+ __ smulh(as_Register($dst$$reg),
+ as_Register($src1$$reg),
+ as_Register($src2$$reg));
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
// Combined Integer Multiply & Add/Sub
instruct maddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
- match(Set dst (AddI (MulI src1 src2) src3));
+ match(Set dst (AddI src3 (MulI src1 src2)));
ins_cost(DEFAULT_COST);
format %{ "madd $dst, $src1, $src2, $src3" %}
@@ -6993,7 +7019,7 @@
%}
instruct msubI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
- match(Set dst (SubI (MulI src1 src2) src3));
+ match(Set dst (SubI src3 (MulI src1 src2)));
ins_cost(DEFAULT_COST);
format %{ "msub $dst, $src1, $src2, $src3" %}
@@ -7011,7 +7037,7 @@
// Combined Long Multiply & Add/Sub
instruct maddL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
- match(Set dst (AddL (MulL src1 src2) src3));
+ match(Set dst (AddL src3 (MulL src1 src2)));
ins_cost(DEFAULT_COST);
format %{ "madd $dst, $src1, $src2, $src3" %}
@@ -7027,7 +7053,7 @@
%}
instruct msubL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
- match(Set dst (SubL (MulL src1 src2) src3));
+ match(Set dst (SubL src3 (MulL src1 src2)));
ins_cost(DEFAULT_COST);
format %{ "msub $dst, $src1, $src2, $src3" %}
@@ -7313,14 +7339,6 @@
%}
// BEGIN This section of the file is automatically generated. Do not edit --------------
-
-
-
-
-
-
-
-
instruct regL_not_reg(iRegLNoSp dst,
iRegL src1, immL_M1 m1,
rFlagsReg cr) %{
@@ -8493,6 +8511,7 @@
%}
ins_pipe(pipe_class_default);
%}
+
// Rotations
instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
@@ -8555,9 +8574,143 @@
ins_pipe(pipe_class_default);
%}
+
+// rol expander
+
+instruct rolL_rReg(iRegL dst, iRegL src, iRegI shift, rFlagsReg cr)
+%{
+ effect(DEF dst, USE src, USE shift);
+
+ format %{ "rol $dst, $src, $shift" %}
+ ins_cost(2*DEFAULT_COST);
+ ins_encode %{
+ __ subw(rscratch1, zr, as_Register($shift$$reg));
+ __ rorv(as_Register($dst$$reg), as_Register($src$$reg),
+ rscratch1);
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+// rol expander
+
+instruct rolI_rReg(iRegI dst, iRegI src, iRegI shift, rFlagsReg cr)
+%{
+ effect(DEF dst, USE src, USE shift);
+
+ format %{ "rol $dst, $src, $shift" %}
+ ins_cost(2*DEFAULT_COST);
+ ins_encode %{
+ __ subw(rscratch1, zr, as_Register($shift$$reg));
+ __ rorvw(as_Register($dst$$reg), as_Register($src$$reg),
+ rscratch1);
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+instruct rolL_rReg_Var_C_64(iRegL dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr)
+%{
+ match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c_64 shift))));
+
+ expand %{
+ rolL_rReg(dst, src, shift, cr);
+ %}
+%}
+
+instruct rolL_rReg_Var_C0(iRegL dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+%{
+ match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c0 shift))));
+
+ expand %{
+ rolL_rReg(dst, src, shift, cr);
+ %}
+%}
+
+instruct rolI_rReg_Var_C_32(iRegL dst, iRegL src, iRegI shift, immI_32 c_32, rFlagsReg cr)
+%{
+ match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c_32 shift))));
+
+ expand %{
+ rolL_rReg(dst, src, shift, cr);
+ %}
+%}
+
+instruct rolI_rReg_Var_C0(iRegL dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+%{
+ match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c0 shift))));
+
+ expand %{
+ rolL_rReg(dst, src, shift, cr);
+ %}
+%}
+
+// ror expander
+
+instruct rorL_rReg(iRegL dst, iRegL src, iRegI shift, rFlagsReg cr)
+%{
+ effect(DEF dst, USE src, USE shift);
+
+ format %{ "ror $dst, $src, $shift" %}
+ ins_cost(DEFAULT_COST);
+ ins_encode %{
+ __ rorv(as_Register($dst$$reg), as_Register($src$$reg),
+ rscratch1);
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+// ror expander
+
+instruct rorI_rReg(iRegI dst, iRegI src, iRegI shift, rFlagsReg cr)
+%{
+ effect(DEF dst, USE src, USE shift);
+
+ format %{ "ror $dst, $src, $shift" %}
+ ins_cost(DEFAULT_COST);
+ ins_encode %{
+ __ rorvw(as_Register($dst$$reg), as_Register($src$$reg),
+ rscratch1);
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+instruct rorL_rReg_Var_C_64(iRegL dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr)
+%{
+ match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c_64 shift))));
+
+ expand %{
+ rorL_rReg(dst, src, shift, cr);
+ %}
+%}
+
+instruct rorL_rReg_Var_C0(iRegL dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+%{
+ match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c0 shift))));
+
+ expand %{
+ rorL_rReg(dst, src, shift, cr);
+ %}
+%}
+
+instruct rorI_rReg_Var_C_32(iRegL dst, iRegL src, iRegI shift, immI_32 c_32, rFlagsReg cr)
+%{
+ match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c_32 shift))));
+
+ expand %{
+ rorL_rReg(dst, src, shift, cr);
+ %}
+%}
+
+instruct rorI_rReg_Var_C0(iRegL dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+%{
+ match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c0 shift))));
+
+ expand %{
+ rorL_rReg(dst, src, shift, cr);
+ %}
+%}
+
// Add/subtract (extended)
-
instruct AddExtI(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
%{
match(Set dst (AddI src1 (ConvI2L src2)));
@@ -8806,15 +8959,11 @@
%}
ins_pipe(pipe_class_default);
%}
+
// END This section of the file is automatically generated. Do not edit --------------
// Combined Long Mask and Right Shift (using UBFM)
// TODO
-// Integer Rotate Instructions
-// TODO
-
-// Long Rotate Instructions
-// TODO
// ============================================================================
// Floating Point Arithmetic Instructions
diff -r 55c4c3af794e -r 2d0b9fa2cd76 src/cpu/aarch64/vm/aarch64_ad.m4
--- a/src/cpu/aarch64/vm/aarch64_ad.m4 Fri Oct 25 18:36:58 2013 +0100
+++ b/src/cpu/aarch64/vm/aarch64_ad.m4 Tue Oct 29 14:12:05 2013 +0000
@@ -1,4 +1,5 @@
// BEGIN This section of the file is automatically generated. Do not edit --------------
+
define(`BASE_SHIFT_INSN',
`
instruct $2$1_reg_$4_reg(iReg$1NoSp dst,
@@ -18,7 +19,7 @@
%}
ins_pipe(pipe_class_default);
-%}')
+%}')dnl
define(`BASE_INVERTED_INSN',
`
instruct $2$1_reg_not_reg(iReg$1NoSp dst,
@@ -40,7 +41,7 @@
%}
ins_pipe(pipe_class_default);
-%}')
+%}')dnl
define(`INVERTED_SHIFT_INSN',
`
instruct $2$1_reg_$4_not_reg(iReg$1NoSp dst,
@@ -63,7 +64,7 @@
%}
ins_pipe(pipe_class_default);
-%}')
+%}')dnl
define(`NOT_INSN',
`instruct reg$1_not_reg(iReg$1NoSp dst,
iReg$1 src1, imm$1_M1 m1,
@@ -80,29 +81,29 @@
%}
ins_pipe(pipe_class_default);
-%}')
+%}')dnl
dnl
define(`BOTH_SHIFT_INSNS',
`BASE_SHIFT_INSN(I, $1, ifelse($2,andr,andw,$2w), $3, $4)
-BASE_SHIFT_INSN(L, $1, $2, $3, $4)')
+BASE_SHIFT_INSN(L, $1, $2, $3, $4)')dnl
dnl
define(`BOTH_INVERTED_INSNS',
`BASE_INVERTED_INSN(I, $1, $2, $3, $4)
-BASE_INVERTED_INSN(L, $1, $2, $3, $4)')
+BASE_INVERTED_INSN(L, $1, $2, $3, $4)')dnl
dnl
define(`BOTH_INVERTED_SHIFT_INSNS',
`INVERTED_SHIFT_INSN(I, $1, $2w, $3, $4, ~0, int)
-INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, long)')
+INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, long)')dnl
dnl
define(`ALL_SHIFT_KINDS',
`BOTH_SHIFT_INSNS($1, $2, URShift, LSR)
BOTH_SHIFT_INSNS($1, $2, RShift, ASR)
-BOTH_SHIFT_INSNS($1, $2, LShift, LSL)')
+BOTH_SHIFT_INSNS($1, $2, LShift, LSL)')dnl
dnl
define(`ALL_INVERTED_SHIFT_KINDS',
`BOTH_INVERTED_SHIFT_INSNS($1, $2, URShift, LSR)
BOTH_INVERTED_SHIFT_INSNS($1, $2, RShift, ASR)
-BOTH_INVERTED_SHIFT_INSNS($1, $2, LShift, LSL)')
+BOTH_INVERTED_SHIFT_INSNS($1, $2, LShift, LSL)')dnl
dnl
NOT_INSN(L, eon)
NOT_INSN(I, eonw)
@@ -185,8 +186,9 @@
%}
ins_pipe(pipe_class_default);
%}
-dnl
+
// Rotations
+
define(`EXTRACT_INSN',
`instruct extr$3$1(iReg$1NoSp dst, iReg$1 src1, iReg$1 src2, immI lshift, immI rshift, rFlagsReg cr)
%{
@@ -202,12 +204,73 @@
%}
ins_pipe(pipe_class_default);
%}
-')
+')dnl
EXTRACT_INSN(L, 63, Or, extr)
EXTRACT_INSN(I, 31, Or, extrw)
EXTRACT_INSN(L, 63, Add, extr)
EXTRACT_INSN(I, 31, Add, extrw)
-dnl
+define(`ROL_EXPAND', `
+// $2 expander
+
+instruct $2$1_rReg(iReg$1 dst, iReg$1 src, iRegI shift, rFlagsReg cr)
+%{
+ effect(DEF dst, USE src, USE shift);
+
+ format %{ "$2 $dst, $src, $shift" %}
+ ins_cost(2*DEFAULT_COST);
+ ins_encode %{
+ __ subw(rscratch1, zr, as_Register($shift$$reg));
+ __ $3(as_Register($dst$$reg), as_Register($src$$reg),
+ rscratch1);
+ %}
+ ins_pipe(pipe_class_default);
+%}')dnl
+define(`ROR_EXPAND', `
+// $2 expander
+
+instruct $2$1_rReg(iReg$1 dst, iReg$1 src, iRegI shift, rFlagsReg cr)
+%{
+ effect(DEF dst, USE src, USE shift);
+
+ format %{ "$2 $dst, $src, $shift" %}
+ ins_cost(DEFAULT_COST);
+ ins_encode %{
+ __ $3(as_Register($dst$$reg), as_Register($src$$reg),
+ rscratch1);
+ %}
+ ins_pipe(pipe_class_default);
+%}')dnl
+define(ROL_INSN, `
+instruct $3$1_rReg_Var_C$2(iRegL dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
+%{
+ match(Set dst (Or$1 (LShift$1 src shift) (URShift$1 src (SubI c$2 shift))));
+
+ expand %{
+ $3L_rReg(dst, src, shift, cr);
+ %}
+%}')dnl
+define(ROR_INSN, `
+instruct $3$1_rReg_Var_C$2(iRegL dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
+%{
+ match(Set dst (Or$1 (URShift$1 src shift) (LShift$1 src (SubI c$2 shift))));
+
+ expand %{
+ $3L_rReg(dst, src, shift, cr);
+ %}
+%}')dnl
+ROL_EXPAND(L, rol, rorv)
+ROL_EXPAND(I, rol, rorvw)
+ROL_INSN(L, _64, rol)
+ROL_INSN(L, 0, rol)
+ROL_INSN(I, _32, rol)
+ROL_INSN(I, 0, rol)
+ROR_EXPAND(L, ror, rorv)
+ROR_EXPAND(I, ror, rorvw)
+ROR_INSN(L, _64, ror)
+ROR_INSN(L, 0, ror)
+ROR_INSN(I, _32, ror)
+ROR_INSN(I, 0, ror)
+
// Add/subtract (extended)
dnl ADD_SUB_EXTENDED(mode, size, add node, shift node, insn, shift type, wordsize
define(`ADD_SUB_CONV', `
@@ -222,7 +285,7 @@
as_Register($src2$$reg), ext::$5);
%}
ins_pipe(pipe_class_default);
-%}')
+%}')dnl
ADD_SUB_CONV(I,L,Add,add,sxtw);
ADD_SUB_CONV(I,L,Sub,sub,sxtw);
dnl
@@ -273,4 +336,5 @@
ADD_SUB_ZERO_EXTEND(L,255,Sub,sub,uxtb)
ADD_SUB_ZERO_EXTEND(L,65535,Sub,sub,uxth)
ADD_SUB_ZERO_EXTEND(L,4294967295,Sub,sub,uxtw)
+
// END This section of the file is automatically generated. Do not edit --------------
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