[aarch64-port-dev ] Clone shifts on addressing modes

[Andrew Haley]

This patch improves code for loads and stores, turning this:

     sxtw       x10, w2
     lsl        x10, x10, #1
     add        xmethod, x4, x10
     ldrsh      w13, [xmethod,#24]  ;*saload
     cmp        w2, w11
     b.cs       0x00007fffed199480  ;*caload
     add        x10, x5, x10
     ldrh       w10, [x10,#24]

into this:

     add    xscratch1, x4, #0x18
     ldrsh      w13, [xscratch1,w2,sxtw #1]   ;*saload
     cmp        w2, w11
     b.cs       0x00007fffed199478  ;*caload
     add        xscratch1, x5, #0x18
     ldrh       w10, [xscratch1,w2,sxtw #1]

Andrew.



# HG changeset patch
# User aph
# Date 1383155220 0
# Node ID b92e284531b2d7aa6bc8b94405a5488a28b33f4f
# Parent  ed0fe5cfe272133e22484d7c99375e1099e4cabb
Clone shifts on addressing modes

diff -r ed0fe5cfe272 -r b92e284531b2 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 30 08:47:21 2013 +0000
+++ b/src/cpu/aarch64/vm/aarch64.ad	Wed Oct 30 17:47:00 2013 +0000
@@ -1591,7 +1591,7 @@
 // Should the Matcher clone shifts on addressing modes, expecting them
 // to be subsumed into complex addressing expressions or compute them
 // into registers?  True for Intel but false for most RISCs
-const bool Matcher::clone_shift_expressions = false;
+const bool Matcher::clone_shift_expressions = true;

 // Do we need to mask the count passed to shift instructions or does
 // the cpu only look at the lower 5/6 bits anyway?