[aarch64-port-dev ] Fix VerifyOops
Andrew Haley
aph at redhat.com
Thu Sep 12 06:36:55 PDT 2013
More of the VerifyOops rewrite.
Andrew.
# HG changeset patch
# User aph
# Date 1378992624 -3600
# Node ID b4b5d34fb848ba2b32e5f1c5b8a104297adcd8ce
# Parent 6af07c154ab396a431a85dd121d7b67e373a15ab
Fix VerifyOops
diff -r 6af07c154ab3 -r b4b5d34fb848 src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Thu Sep 12 14:27:56 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Thu Sep 12 14:30:24 2013 +0100
@@ -854,59 +854,50 @@
char* b = new char[strlen(s) + 50];
sprintf(b, "verify_oop: %s: %s", reg->name(), s);
BLOCK_COMMENT("verify_oop {");
+
stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
+ stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
- ExternalAddress buffer((address) b);
- // our contract is not to modify anything
- mov(rscratch1, buffer.target());
- stp(rscratch1, reg, Address(pre(sp, -2 * wordSize)));
+ mov(r0, reg);
+ mov(rscratch1, (address)b);
// call indirectly to solve generation ordering problem
- stp(reg, lr, Address(pre(sp, -2 * wordSize)));
- lea(rscratch1, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
- ldr(rscratch1, Address(rscratch1));
- blr(rscratch1);
- ldp(reg, lr, Address(post(sp, 2 * wordSize)));
- add(sp, sp, 2 * wordSize);
+ lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
+ ldr(rscratch2, Address(rscratch2));
+ blr(rscratch2);
+
+ ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
BLOCK_COMMENT("} verify_oop");
}
void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
- return;
if (!VerifyOops) return;
- // Pass register number to verify_oop_subroutine
char* b = new char[strlen(s) + 50];
sprintf(b, "verify_oop_addr: %s", s);
-
BLOCK_COMMENT("verify_oop_addr {");
stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
- // addr may contain rsp so we will have to adjust it based on the push
- // we just did (and on 64 bit we do two pushes)
- // NOTE: 64bit seemed to have had a bug in that it did movq(addr, r0); which
- // stores r0 into addr which is backwards of what was intended.
+ stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
+
+ // addr may contain sp so we will have to adjust it based on the
+ // pushes that we just did.
if (addr.uses(sp)) {
lea(r0, addr);
- ldr(r0, Address(r0, 2 * wordSize));
+ ldr(r0, Address(r0, 4 * wordSize));
} else {
ldr(r0, addr);
}
-
- ExternalAddress buffer((address) b);
- // our contract is not to modify anything
- mov(rscratch1, buffer.target());
- stp(rscratch1, r0, Address(pre(sp, -2 * wordSize)));
+ mov(rscratch1, (address)b);
// call indirectly to solve generation ordering problem
- stp(zr, lr, Address(pre(sp, -2 * wordSize)));
- lea(rscratch1, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
- ldr(rscratch1, Address(rscratch1));
- blr(rscratch1);
- ldp(zr, lr, Address(post(sp, 2 * wordSize)));
- add(sp, sp, 2 * wordSize);
+ lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
+ ldr(rscratch2, Address(rscratch2));
+ blr(rscratch2);
+
+ ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
BLOCK_COMMENT("} verify_oop_addr");
diff -r 6af07c154ab3 -r b4b5d34fb848 src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Thu Sep 12 14:27:56 2013 +0100
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Thu Sep 12 14:30:24 2013 +0100
@@ -700,18 +700,16 @@
// Non-destructive plausibility checks for oops
//
// Arguments:
- // all args on stack!
+ // r0: oop to verify
+ // rscratch1: error message
//
// Stack after saving c_rarg3:
// [tos + 0]: saved c_rarg3
// [tos + 1]: saved c_rarg2
- // [tos + 2]: scratch -- saves LR around call to debug64
+ // [tos + 2]: saved rscratch2
// [tos + 3]: saved lr
- // * [tos + 4]: error message (char*)
- // * [tos + 5]: object to verify (oop)
- // * [tos + 6]: saved r0 - saved by caller and bashed
- // * [tos + 7]: saved rscratch1 - saved by caller
- // * = popped on exit
+ // [tos + 4]: saved rscratch1
+ // [tos + 5]: saved r0
address generate_verify_oop() {
StubCodeMark mark(this, "StubRoutines", "verify_oop");
@@ -731,19 +729,7 @@
__ add(c_rarg3, c_rarg3, 1);
__ str(c_rarg3, Address(c_rarg2));
- enum {
- // After previous pushes.
- oop_to_verify = 5 * wordSize,
- saved_r0 = 6 * wordSize,
-
- // Before the call to MacroAssembler::debug(), see below.
- return_addr = (32+2) * wordSize,
- error_msg = (32+3) * wordSize
- };
-
- // get object
- __ ldr(r0, Address(sp, oop_to_verify));
-
+ // object is in r0
// make sure object is 'reasonable'
__ cbz(r0, exit); // if obj is NULL it is OK
@@ -771,34 +757,22 @@
// handle errors
__ bind(error);
__ ldp(c_rarg3, c_rarg2, Address(__ post(sp, 16)));
- __ str(lr, Address(sp, 0));
- __ ldp(zr, lr, Address(sp, 0));
- __ ldp(r0, rscratch1, Address(sp, 2 * wordSize));
+
__ push(0x7fffffff, sp);
// debug(char* msg, int64_t pc, int64_t regs[])
- // We've popped the registers we'd saved (c_rarg3, c_rarg2), and
- // pushed all the registers, so now the stack looks like:
- // [tos + 0] 32 saved registers
- // [ + 0]: garbage
- // [ + 1]: saved lr
- // * [ + 2]: error message (char*)
- // * [ + 3]: object to verify (oop)
- // * [ + 4]: saved r0 - saved by caller and bashed
- // * [ + 5]: saved rscratch1 - saved by caller
-
- __ ldr(c_rarg0, Address(sp, error_msg)); // pass address of error message
- __ ldr(c_rarg1, Address(sp, return_addr)); // pass return address
+ __ ldr(c_rarg0, Address(sp, rscratch1->encoding())); // pass address of error message
+ __ mov(c_rarg1, Address(sp, lr)); // pass return address
__ mov(c_rarg2, sp); // pass address of regs on stack
- __ mov(r19, sp); // remember rsp
#ifndef PRODUCT
assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
#endif
BLOCK_COMMENT("call MacroAssembler::debug");
__ mov(rscratch1, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
__ blrt(rscratch1, 3, 0, 1);
- __ mov(sp, r19); // restore rsp
__ pop(0x7fffffff, sp);
- __ ldr(lr, Address(sp, 0));
+
+ __ ldp(rscratch2, lr, Address(__ post(sp, 2 * wordSize)));
+ __ ldp(r0, rscratch1, Address(__ post(sp, 2 * wordSize)));
__ ret(lr);
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