[aarch64-port-dev ] FP load/stores and atomicity guarantees

[D.Sturm]

Hi,
what are the current ideas with regard to atomicity of floating point
load/stores? JLS 17.7 states that write/reads of floats are atomic, while
doubles only need to guarantee that the 2 halves are written in any order.
For volatile doubles it also expects atomicity.

The problem with these requirements is that the only guarantee the A64 ISA
gives is byte-wise atomicity (B2.6.3): "No memory accesses involving SIMD
and floating-point registers[...] have single-copy atomicity of any
quantity greater than individual bytes."

It seems to me the only way to implement the requirements given by the JLS
is to move non-local floating point values (local ones that are only
visible to one thread are expemt obviously) into an integer register for
load/store instructions (ouch).

Any thoughts on the topic? Maybe existing processor designs give stronger
guarantees? At the moment it seems that HotSpot is generating normal
ldr/str dX, address instructions indiscriminately

-- Daniel