[aarch64-port-dev ] /hg/icedtea7-forest-aarch64/hotspot: 2 new changesets

[Andrew Dinn]

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Date: Thu, 11 Dec 2014 16:42:09 +0000
Subject: /hg/icedtea7-forest-aarch64/hotspot: 2 new changesets
From: adinn at icedtea.classpath.org
X-Hg-Notification: changeset 6aed71db871e
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<hg.6aed71db871e.1418316129.-5017525213744097322 at icedtea.classpath.org>
To: aarch64-port-dev at openjdk.java.net

changeset 6aed71db871e in /hg/icedtea7-forest-aarch64/hotspot
details:
http://icedtea.classpath.org/hg/icedtea7-forest-aarch64/hotspot?cmd=changeset;node=6aed71db871e
author: adinn
date: Thu Dec 11 15:08:13 2014 +0000

	corrected pipeline class for countTrailingZerosL


changeset 5ad4c0916974 in /hg/icedtea7-forest-aarch64/hotspot
details:
http://icedtea.classpath.org/hg/icedtea7-forest-aarch64/hotspot?cmd=changeset;node=5ad4c0916974
author: adinn
date: Thu Dec 11 16:42:03 2014 +0000

	Add support for A53 multiply accumulate


diffstat:

 src/cpu/aarch64/vm/aarch64.ad              |   2 +-
 src/cpu/aarch64/vm/assembler_aarch64.cpp   |   2 +-
 src/cpu/aarch64/vm/assembler_aarch64.hpp   |  10 ++++++++++
 src/cpu/aarch64/vm/interp_masm_aarch64.cpp |   2 +-
 4 files changed, 13 insertions(+), 3 deletions(-)

diffs (56 lines):

diff -r 39befa03b58a -r 5ad4c0916974 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Wed Dec 10 06:03:04 2014 +0000
+++ b/src/cpu/aarch64/vm/aarch64.ad	Thu Dec 11 16:42:03 2014 +0000
@@ -5989,7 +5989,7 @@
     __ clz(as_Register($dst$$reg), as_Register($dst$$reg));
   %}

-  ins_pipe( pipe_serial );
+  ins_pipe( ialu_reg );
 %}

 //
============================================================================
diff -r 39befa03b58a -r 5ad4c0916974
src/cpu/aarch64/vm/assembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.cpp	Wed Dec 10 06:03:04 2014
+0000
+++ b/src/cpu/aarch64/vm/assembler_aarch64.cpp	Thu Dec 11 16:42:03 2014
+0000
@@ -3056,7 +3056,7 @@
     sdivw(result, ra, rb);
   } else {
     sdivw(scratch, ra, rb);
-    msubw(result, scratch, rb, ra);
+    Assembler::msubw(result, scratch, rb, ra);
   }

   return idivl_offset;
diff -r 39befa03b58a -r 5ad4c0916974
src/cpu/aarch64/vm/assembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp	Wed Dec 10 06:03:04 2014
+0000
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp	Thu Dec 11 16:42:03 2014
+0000
@@ -2643,6 +2643,16 @@
     umaddl(Rd, Rn, Rm, zr);
   }

+#define WRAP(INSN)                                                \
+  void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
+    if (Ra != zr) nop();                                          \
+    Assembler::INSN(Rd, Rn, Rm, Ra);                              \
+  }
+
+  WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
+  WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
+#undef WRAP
+
   // macro assembly operations needed for aarch64

   // first two private routines for loading 32 bit or 64 bit constants
diff -r 39befa03b58a -r 5ad4c0916974
src/cpu/aarch64/vm/interp_masm_aarch64.cpp
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Wed Dec 10 06:03:04
2014 +0000
+++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Thu Dec 11 16:42:03
2014 +0000
@@ -1295,7 +1295,7 @@
     // case_array_offset_in_bytes()
     movw(reg2, in_bytes(MultiBranchData::per_case_size()));
     movw(rscratch1, in_bytes(MultiBranchData::case_array_offset()));
-    maddw(index, index, reg2, rscratch1);
+    Assembler::maddw(index, index, reg2, rscratch1);

     // Update the case count
     increment_mdp_data_at(mdp,