[aarch64-port-dev ] openjdk atomics

[Andrew Dinn]

On 11/02/14 16:06, Andrew Haley wrote:
> This isn't about locking/synchronization, it's about CAS.
> 
> This is what we do at the moment:
> 
> 	<Access [A]>
> 
> 	// atomic_op (B)
> 1:	ldaxr	x0, [B]		// Exclusive load with acquire
> 	<op(B)>
> 	stlxr	w1, x0, [B]	// Exclusive store with release
> 	cbnz	w1, 1b
> 
> 	<Access [C]>
> 
> It doesn't forbid orderings such as
> 
> Load [B] -> Load [C] -> Store [A] -> Store [B]
> 
> It may be that this doesn't matter, but I would surely prefer to have a
> CAS that didn't have this property, and I'm sure we're in no position
> to audit all of C2 to make sure that it doesn't matter.

Well, it's not that difficult to determine.

There are explicit lock/unlock instrctions in aarch64.ad (FastLock,
FastUnlock) where we currently call the assembler method cmpxchgptr. In
these cases we shouldn't need to do a full dmb.

We also have other rules which may well require a full dmb
(Store{LI}Conditional, CompareAndSwap{ILNP}).

So, perhaps we need to implement two variants here.

regards,


Andrew Dinn
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