[aarch64-port-dev ] Bug fix patches for aarch64 jdk7u hotspot
Andrew Dinn
adinn at redhat.com
Fri Jul 11 15:09:06 UTC 2014
The attached patches apply all outstanding jdk8 bug fixes to the jdk7u
hotspot tree. The resulting tree builds with the latest icedtea7-forest
on a mustang box and the image can run Hello and compile Hello.java.
I have not yet tried anything more demanding for lack of any suitable
installed code on the box in question.
Note that patch 6757 (fixes for C1 and C2 frame build/remove) was
synthesized from several upstream jdk8 patches some of which were made
in different branches and had conflicts.
regards,
Andrew Dinn
-----------
-------------- next part --------------
# HG changeset patch
# User aph
# Date 1404912371 -3600
# Node ID eefd08f120e1d116aff68827d6166390fbceec43
# Parent 360d11d249a68891117ac3d89d62d96199dcaa2f
Use explicit barrier instructions in C1.
diff -r 360d11d249a6 -r eefd08f120e1 src/cpu/aarch64/vm/assembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp Fri Jan 10 15:58:40 2014 +0100
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp Wed Jul 09 14:26:11 2014 +0100
@@ -1992,6 +1992,11 @@
void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
};
+inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
+ Assembler::Membar_mask_bits b) {
+ return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
+}
+
Instruction_aarch64::~Instruction_aarch64() {
assem->emit();
}
diff -r 360d11d249a6 -r eefd08f120e1 src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Fri Jan 10 15:58:40 2014 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Wed Jul 09 14:26:11 2014 +0100
@@ -177,10 +177,6 @@
return result;
}
-static bool is_reg(LIR_Opr op) {
- return op->is_double_cpu() | op->is_single_cpu();
-}
-
Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
Register base = addr->base()->as_pointer_register();
LIR_Opr opr = addr->index();
@@ -2745,148 +2741,12 @@
}
void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
- if (dest->is_address()) {
- LIR_Address* to_addr = dest->as_address_ptr();
- Register compressed_src = noreg;
- if (is_reg(src)) {
- compressed_src = as_reg(src);
- if (type == T_ARRAY || type == T_OBJECT) {
- __ verify_oop(src->as_register());
- if (UseCompressedOops) {
- compressed_src = rscratch2;
- __ mov(compressed_src, src->as_register());
- __ encode_heap_oop(compressed_src);
- }
- }
- } else if (src->is_single_fpu()) {
- __ fmovs(rscratch2, src->as_float_reg());
- src = FrameMap::rscratch2_opr, type = T_INT;
- } else if (src->is_double_fpu()) {
- __ fmovd(rscratch2, src->as_double_reg());
- src = FrameMap::rscratch2_long_opr, type = T_LONG;
- }
-
- if (dest->is_double_cpu())
- __ lea(rscratch1, as_Address(to_addr));
- else
- __ lea(rscratch1, as_Address_lo(to_addr));
-
- int null_check_here = code_offset();
- switch (type) {
- case T_ARRAY: // fall through
- case T_OBJECT: // fall through
- if (UseCompressedOops) {
- __ stlrw(compressed_src, rscratch1);
- } else {
- __ stlr(compressed_src, rscratch1);
- }
- break;
- case T_METADATA:
- // We get here to store a method pointer to the stack to pass to
- // a dtrace runtime call. This can't work on 64 bit with
- // compressed klass ptrs: T_METADATA can be a compressed klass
- // ptr or a 64 bit method pointer.
- LP64_ONLY(ShouldNotReachHere());
- __ stlr(src->as_register(), rscratch1);
- break;
- case T_ADDRESS:
- __ stlr(src->as_register(), rscratch1);
- break;
- case T_INT:
- __ stlrw(src->as_register(), rscratch1);
- break;
-
- case T_LONG: {
- __ stlr(src->as_register_lo(), rscratch1);
- break;
- }
-
- case T_BYTE: // fall through
- case T_BOOLEAN: {
- __ stlrb(src->as_register(), rscratch1);
- break;
- }
-
- case T_CHAR: // fall through
- case T_SHORT:
- __ stlrh(src->as_register(), rscratch1);
- break;
-
- default:
- ShouldNotReachHere();
- }
- if (info != NULL) {
- add_debug_info_for_null_check(null_check_here, info);
- }
- } else if (src->is_address()) {
- LIR_Address* from_addr = src->as_address_ptr();
-
- if (src->is_double_cpu())
- __ lea(rscratch1, as_Address(from_addr));
- else
- __ lea(rscratch1, as_Address_lo(from_addr));
-
- int null_check_here = code_offset();
- switch (type) {
- case T_ARRAY: // fall through
- case T_OBJECT: // fall through
- if (UseCompressedOops) {
- __ ldarw(dest->as_register(), rscratch1);
- } else {
- __ ldar(dest->as_register(), rscratch1);
- }
- break;
- case T_ADDRESS:
- __ ldar(dest->as_register(), rscratch1);
- break;
- case T_INT:
- __ ldarw(dest->as_register(), rscratch1);
- break;
- case T_LONG: {
- __ ldar(dest->as_register_lo(), rscratch1);
- break;
- }
-
- case T_BYTE: // fall through
- case T_BOOLEAN: {
- __ ldarb(dest->as_register(), rscratch1);
- break;
- }
-
- case T_CHAR: // fall through
- case T_SHORT:
- __ ldarh(dest->as_register(), rscratch1);
- break;
-
- case T_FLOAT:
- __ ldarw(rscratch2, rscratch1);
- __ fmovs(dest->as_float_reg(), rscratch2);
- break;
-
- case T_DOUBLE:
- __ ldar(rscratch2, rscratch1);
- __ fmovd(dest->as_double_reg(), rscratch2);
- break;
-
- default:
- ShouldNotReachHere();
- }
- if (info != NULL) {
- add_debug_info_for_null_check(null_check_here, info);
- }
-
- if (type == T_ARRAY || type == T_OBJECT) {
- if (UseCompressedOops) {
- __ decode_heap_oop(dest->as_register());
- }
- __ verify_oop(dest->as_register());
- } else if (type == T_ADDRESS && from_addr->disp() == oopDesc::klass_offset_in_bytes()) {
- if (UseCompressedClassPointers) {
- __ decode_klass_not_null(dest->as_register());
- }
- }
- } else
+ if (dest->is_address() || src->is_address()) {
+ move_op(src, dest, type, lir_patch_none, info,
+ /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false);
+ } else {
ShouldNotReachHere();
+ }
}
#ifdef ASSERT
@@ -2940,17 +2800,18 @@
}
void LIR_Assembler::membar_acquire() {
- __ block_comment("membar_acquire");
+ __ membar(Assembler::LoadLoad|Assembler::LoadStore);
}
void LIR_Assembler::membar_release() {
- __ block_comment("membar_release");
+ __ membar(Assembler::LoadStore|Assembler::StoreStore);
}
-void LIR_Assembler::membar_loadload() { Unimplemented(); }
+void LIR_Assembler::membar_loadload() {
+ __ membar(Assembler::LoadLoad);
+}
void LIR_Assembler::membar_storestore() {
- COMMENT("membar_storestore");
__ membar(MacroAssembler::StoreStore);
}
-------------- next part --------------
# HG changeset patch
# User Edward Nevill edward.nevill at linaro.org
# Date 1404912935 -3600
# Node ID da8c7403f77e111a424a27f498208bde35992a59
# Parent eefd08f120e1d116aff68827d6166390fbceec43
Fix register misuse in verify_method_data_pointer
diff -r eefd08f120e1 -r da8c7403f77e src/cpu/aarch64/vm/interp_masm_aarch64.cpp
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp Wed Jul 09 14:26:11 2014 +0100
+++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp Wed Jul 09 14:35:35 2014 +0100
@@ -803,10 +803,10 @@
cmp(r2, rbcp);
br(Assembler::EQ, verify_continue);
// r1: method
- // r13: bcp
+ // rbcp: bcp // rbcp == 22
// r3: mdp
call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::verify_mdp),
- r1, r13, r3);
+ r1, rbcp, r3);
bind(verify_continue);
ldp(r2, r3, Address(post(sp, 2 * wordSize)));
ldp(r0, r1, Address(post(sp, 2 * wordSize)));
-------------- next part --------------
# HG changeset patch
# User aph
# Date 1404917518 -3600
# Node ID 22313a11db519b69b2fe3dff3252b2c6ea78470f
# Parent da8c7403f77e111a424a27f498208bde35992a59
Fix register usage in generate_verify_oop().
diff -r da8c7403f77e -r 22313a11db51 src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Wed Jul 09 14:35:35 2014 +0100
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Wed Jul 09 15:51:58 2014 +0100
@@ -754,10 +754,10 @@
// Stack after saving c_rarg3:
// [tos + 0]: saved c_rarg3
// [tos + 1]: saved c_rarg2
- // [tos + 2]: saved rscratch2
- // [tos + 3]: saved lr
- // [tos + 4]: saved rscratch1
- // [tos + 5]: saved r0
+ // [tos + 2]: saved lr
+ // [tos + 3]: saved rscratch2
+ // [tos + 4]: saved r0
+ // [tos + 5]: saved rscratch1
address generate_verify_oop() {
StubCodeMark mark(this, "StubRoutines", "verify_oop");
@@ -765,9 +765,6 @@
Label exit, error;
- // __ pushf();
- // __ push(r12);
-
// save c_rarg2 and c_rarg3
__ stp(c_rarg3, c_rarg2, Address(__ pre(sp, -16)));
@@ -807,21 +804,15 @@
__ push(RegSet::range(r0, r29), sp);
// debug(char* msg, int64_t pc, int64_t regs[])
- __ ldr(c_rarg0, Address(sp, rscratch1->encoding())); // pass address of error message
- __ mov(c_rarg1, Address(sp, lr)); // pass return address
- __ mov(c_rarg2, sp); // pass address of regs on stack
+ __ mov(c_rarg0, rscratch1); // pass address of error message
+ __ mov(c_rarg1, lr); // pass return address
+ __ mov(c_rarg2, sp); // pass address of regs on stack
#ifndef PRODUCT
assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
#endif
BLOCK_COMMENT("call MacroAssembler::debug");
__ mov(rscratch1, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
__ blrt(rscratch1, 3, 0, 1);
- __ pop(RegSet::range(r0, r29), sp);
-
- __ ldp(rscratch2, lr, Address(__ post(sp, 2 * wordSize)));
- __ ldp(r0, rscratch1, Address(__ post(sp, 2 * wordSize)));
-
- __ ret(lr);
return start;
}
-------------- next part --------------
# HG changeset patch
# User adinn
# Date 1404993900 -3600
# Node ID de03075e4aaf09c2cb4d198537730cc73837a9f1
# Parent 22313a11db519b69b2fe3dff3252b2c6ea78470f
Common frame handling for C1/C2 which correctly handle all frame sizes
This patch merges several changes from the upstream JDK8 code
diff -r 22313a11db51 -r de03075e4aaf src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Wed Jul 09 15:51:58 2014 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad Thu Jul 10 13:05:00 2014 +0100
@@ -868,7 +868,7 @@
if (framesize == 0) {
// Is this even possible?
st->print("stp lr, rfp, [sp, #%d]!", -(2 * wordSize));
- } else if (framesize < (1 << 12)) {
+ } else if (framesize < ((1 << 9) + 2 * wordSize)) {
st->print("sub sp, sp, #%d\n\t", framesize);
st->print("stp rfp, lr, [sp, #%d]", framesize - 2 * wordSize);
} else {
@@ -894,17 +894,7 @@
if (C->need_stack_bang(framesize))
__ generate_stack_overflow_check(framesize);
- if (framesize == 0) {
- // Is this even possible?
- __ stp(rfp, lr, Address(__ pre(sp, -2 * wordSize)));
- } else if (framesize < (1 << 12)) {
- __ sub(sp, sp, framesize);
- __ stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
- } else {
- __ stp(rfp, lr, Address(__ pre(sp, -2 * wordSize)));
- __ mov(rscratch1, framesize - 2 * wordSize);
- __ sub(sp, sp, rscratch1);
- }
+ __ build_frame(framesize);
if (NotifySimulator) {
__ notify(Assembler::method_entry);
@@ -946,7 +936,7 @@
if (framesize == 0) {
st->print("ldp lr, rfp, [sp],#%d\n\t", (2 * wordSize));
- } else if (framesize < (1 << 12)) {
+ } else if (framesize < ((1 << 9) + 2 * wordSize)) {
st->print("ldp lr, rfp, [sp,#%d]\n\t", framesize - 2 * wordSize);
st->print("add sp, sp, #%d\n\t", framesize);
} else {
@@ -968,16 +958,7 @@
MacroAssembler _masm(&cbuf);
int framesize = C->frame_slots() << LogBytesPerInt;
- if (framesize == 0) {
- __ ldp(rfp, lr, Address(__ post(sp, 2 * wordSize)));
- } else if (framesize < (1 << 12)) {
- __ ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
- __ add(sp, sp, framesize);
- } else {
- __ mov(rscratch1, framesize - 2 * wordSize);
- __ add(sp, sp, rscratch1);
- __ ldp(rfp, lr, Address(__ post(sp, 2 * wordSize)));
- }
+ __ remove_frame(framesize);
if (NotifySimulator) {
__ notify(Assembler::method_reentry);
diff -r 22313a11db51 -r de03075e4aaf src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp Wed Jul 09 15:51:58 2014 +0100
+++ b/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp Thu Jul 10 13:05:00 2014 +0100
@@ -420,7 +420,7 @@
}
-void C1_MacroAssembler::build_frame(int frame_size_in_bytes) {
+void C1_MacroAssembler::build_frame(int framesize) {
// If we have to make this method not-entrant we'll overwrite its
// first instruction with a jump. For this action to be legal we
// must ensure that this first instruction is a B, BL, NOP, BKPT,
@@ -428,18 +428,16 @@
nop();
// Make sure there is enough stack space for this method's activation.
// Note that we do this before doing an enter().
- generate_stack_overflow_check(frame_size_in_bytes);
- enter();
- sub(sp, sp, frame_size_in_bytes); // does not emit code for frame_size == 0
+ generate_stack_overflow_check(framesize);
+ MacroAssembler::build_frame(framesize + 2 * wordSize);
if (NotifySimulator) {
notify(Assembler::method_entry);
}
}
-void C1_MacroAssembler::remove_frame(int frame_size_in_bytes) {
- add(sp, sp, frame_size_in_bytes); // Does not emit code for frame_size == 0
- ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
+void C1_MacroAssembler::remove_frame(int framesize) {
+ MacroAssembler::remove_frame(framesize + 2 * wordSize);
if (NotifySimulator) {
notify(Assembler::method_reentry);
}
diff -r 22313a11db51 -r de03075e4aaf src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Wed Jul 09 15:51:58 2014 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Thu Jul 10 13:05:00 2014 +0100
@@ -3099,3 +3099,39 @@
return UseAcqRelForVolatileFields;
#endif
}
+
+void MacroAssembler::build_frame(int framesize) {
+ if (framesize == 0) {
+ // Is this even possible?
+ stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
+ } else if (framesize < ((1 << 9) + 2 * wordSize)) {
+ sub(sp, sp, framesize);
+ stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
+ } else {
+ stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
+ if (framesize < ((1 << 12) + 2 * wordSize))
+ sub(sp, sp, framesize - 2 * wordSize);
+ else {
+ mov(rscratch1, framesize - 2 * wordSize);
+ sub(sp, sp, rscratch1);
+ }
+ }
+}
+
+void MacroAssembler::remove_frame(int framesize) {
+ if (framesize == 0) {
+ ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
+ } else if (framesize < ((1 << 9) + 2 * wordSize)) {
+ ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
+ add(sp, sp, framesize);
+ } else {
+ if (framesize < ((1 << 12) + 2 * wordSize))
+ add(sp, sp, framesize - 2 * wordSize);
+ else {
+ mov(rscratch1, framesize - 2 * wordSize);
+ add(sp, sp, rscratch1);
+ }
+ ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
+ }
+}
+
diff -r 22313a11db51 -r de03075e4aaf src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp Wed Jul 09 15:51:58 2014 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp Thu Jul 10 13:05:00 2014 +0100
@@ -151,6 +151,10 @@
strw(scratch, a);
}
+ // Frame creation and destruction shared between JITs.
+ void build_frame(int framesize);
+ void remove_frame(int framesize);
+
virtual void _call_Unimplemented(address call_site) {
mov(rscratch2, call_site);
haltsim();
-------------- next part --------------
# HG changeset patch
# User Edward Nevill edward.nevill at linaro.org
# Date 1404846956 -3600
# Node ID a03843f2ff15e2ac97af1c0e0eec76c7819a2a1c
# Parent de03075e4aaf09c2cb4d198537730cc73837a9f1
Restrict default ReservedCodeCacheSize to 128M
diff -r de03075e4aaf -r a03843f2ff15 src/share/vm/runtime/arguments.cpp
--- a/src/share/vm/runtime/arguments.cpp Thu Jul 10 13:05:00 2014 +0100
+++ b/src/share/vm/runtime/arguments.cpp Tue Jul 08 20:15:56 2014 +0100
@@ -1129,6 +1129,8 @@
// Increase the code cache size - tiered compiles a lot more.
if (FLAG_IS_DEFAULT(ReservedCodeCacheSize)) {
FLAG_SET_DEFAULT(ReservedCodeCacheSize, ReservedCodeCacheSize * 5);
+ // The maximum B/BL offset range on AArch64 is 128MB
+ AARCH64_ONLY(FLAG_SET_DEFAULT(ReservedCodeCacheSize, MIN2(ReservedCodeCacheSize, 128*M)));
}
if (!UseInterpreter) { // -Xcomp
Tier3InvokeNotifyFreqLog = 0;
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