[aarch64-port-dev ] RFR: Refactor SIMD instructions using INSN macros
Edward Nevill
edward.nevill at linaro.org
Mon Jul 21 16:36:07 UTC 2014
Hi,
The following patch refactors the SIMD instructions using INSN macros.
In addition to removing about 100 lines of code it now supports a larger chunk of simd instructions and is more orthogonal in what it supports.
Instructions now supported using INSN macros are
ld1, ld2, ld3, ld4, st1, st2, st3, st4, ld1r, ld2r, ld3r, ld4r
eor, orr, and, bic, bif, bit, bsl, orn
aese, aesd, aesmc, aesimc
I have tested that AES and CRC intrinsics still work on appropriate HW and have done a jtreg/hotspot test.
OK?
Ed.
--- CUT HERE ---
# HG changeset patch
# User Edward Nevill edward.nevill at linaro.org
# Date 1405959820 -3600
# Mon Jul 21 17:23:40 2014 +0100
# Node ID c4af536cc45c9e0928e51408b07de2d3f9193d55
# Parent 135fb0fc41236934277396d7d0d6bb2714093ad6
Refactor SIMD instructions using INSN macros
diff -r 135fb0fc4123 -r c4af536cc45c src/cpu/aarch64/vm/assembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp Mon Jul 21 10:46:47 2014 +0100
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp Mon Jul 21 17:23:40 2014 +0100
@@ -1857,6 +1857,154 @@
S32, D64, Q128
};
+void v_ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2)
+{
+ starti;
+ f(0,31), f((int)T & 1, 30);
+ f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
+ f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
+}
+void v_ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
+ int imm, int op1, int op2)
+{
+ starti;
+ f(0,31), f((int)T & 1, 30);
+ f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
+ f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
+}
+void v_ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
+ Register Xm, int op1, int op2)
+{
+ starti;
+ f(0,31), f((int)T & 1, 30);
+ f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
+ f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
+}
+
+#define INSN1(NAME, op1, op2) \
+ void NAME(FloatRegister Vt, SIMD_Arrangement T, Register Xn) { \
+ v_ld_st(Vt, T, Xn, op1, op2); \
+ } \
+ void NAME(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int imm) { \
+ v_ld_st(Vt, T, Xn, imm, op1, op2); \
+ } \
+ void NAME(FloatRegister Vt, SIMD_Arrangement T, Register Xn, Register Xm) { \
+ v_ld_st(Vt, T, Xn, Xm, op1, op2); \
+ }
+#define INSN2(NAME, op1, op2) \
+ void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, Register Xn) { \
+ assert(Vt->successor() == Vt2, "Registers must be ordered"); \
+ v_ld_st(Vt, T, Xn, op1, op2); \
+ } \
+ void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, Register Xn, \
+ int imm) { \
+ assert(Vt->successor() == Vt2, "Registers must be ordered"); \
+ v_ld_st(Vt, T, Xn, imm, op1, op2); \
+ } \
+ void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, Register Xn, \
+ Register Xm) { \
+ assert(Vt->successor() == Vt2, "Registers must be ordered"); \
+ v_ld_st(Vt, T, Xn, Xm, op1, op2); \
+ }
+#define INSN3(NAME, op1, op2) \
+ void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
+ SIMD_Arrangement T, Register Xn) { \
+ assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
+ "Registers must be ordered"); \
+ v_ld_st(Vt, T, Xn, op1, op2); \
+ } \
+ void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
+ SIMD_Arrangement T, Register Xn, int imm) { \
+ assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
+ "Registers must be ordered"); \
+ v_ld_st(Vt, T, Xn, imm, op1, op2); \
+ } \
+ void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
+ SIMD_Arrangement T, Register Xn, Register Xm) { \
+ assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
+ "Registers must be ordered"); \
+ v_ld_st(Vt, T, Xn, Xm, op1, op2); \
+ }
+#define INSN4(NAME, op1, op2) \
+ void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
+ FloatRegister Vt4, SIMD_Arrangement T, Register Xn) { \
+ assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
+ Vt3->successor() == Vt4, "Registers must be ordered"); \
+ v_ld_st(Vt, T, Xn, op1, op2); \
+ } \
+ void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
+ FloatRegister Vt4, SIMD_Arrangement T, Register Xn, int imm) { \
+ assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
+ Vt3->successor() == Vt4, "Registers must be ordered"); \
+ v_ld_st(Vt, T, Xn, imm, op1, op2); \
+ } \
+ void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
+ FloatRegister Vt4, SIMD_Arrangement T, Register Xn, Register Xm) { \
+ assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
+ Vt3->successor() == Vt4, "Registers must be ordered"); \
+ v_ld_st(Vt, T, Xn, Xm, op1, op2); \
+ }
+
+ INSN1(v_ld1, 0b001100010, 0b0111);
+ INSN2(v_ld1, 0b001100010, 0b1010);
+ INSN3(v_ld1, 0b001100010, 0b0110);
+ INSN4(v_ld1, 0b001100010, 0b0010);
+
+ INSN2(v_ld2, 0b001100010, 0b1000);
+ INSN3(v_ld3, 0b001100010, 0b0100);
+ INSN4(v_ld4, 0b001100010, 0b0000);
+
+ INSN1(v_st1, 0b001100000, 0b0111);
+ INSN2(v_st1, 0b001100000, 0b1010);
+ INSN3(v_st1, 0b001100000, 0b0110);
+ INSN4(v_st1, 0b001100000, 0b0010);
+
+ INSN2(v_st2, 0b001100000, 0b1000);
+ INSN3(v_st3, 0b001100000, 0b0100);
+ INSN4(v_st4, 0b001100000, 0b0000);
+
+ INSN1(v_ld1r, 0b001101010, 0b1100);
+ INSN2(v_ld2r, 0b001101011, 0b1100);
+ INSN3(v_ld3r, 0b001101010, 0b1110);
+ INSN4(v_ld4r, 0b001101011, 0b1110);
+
+#undef INSN1
+#undef INSN2
+#undef INSN3
+#undef INSN4
+
+#define INSN(NAME, opc) \
+ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
+ starti; \
+ assert(T == T8B || T == T16B, "must be T8B or T16B"); \
+ f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
+ rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
+ }
+
+ INSN(v_eor, 0b101110001);
+ INSN(v_orr, 0b001110101);
+ INSN(v_and, 0b001110001);
+ INSN(v_bic, 0b001110011);
+ INSN(v_bif, 0b101110111);
+ INSN(v_bit, 0b101110101);
+ INSN(v_bsl, 0b101110011);
+ INSN(v_orn, 0b001110111);
+
+#undef INSN
+
+#define INSN(NAME, opc) \
+ void NAME(FloatRegister Vd, FloatRegister Vn) { \
+ starti; \
+ f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
+ }
+
+ INSN(v_aese, 0b0100111000101000010010);
+ INSN(v_aesd, 0b0100111000101000010110);
+ INSN(v_aesmc, 0b0100111000101000011010);
+ INSN(v_aesimc, 0b0100111000101000011110);
+
+#undef INSN
+
void v_shl(FloatRegister Vd, FloatRegister Vn, SIMD_Arrangement T, int shift){
starti;
/* The encodings for the immh:immb fields (bits 22:16) are
@@ -1924,229 +2072,6 @@
v_pmull(Vd, Ta, Vn, Vm, Tb);
}
- void v_ld1(FloatRegister Vt, SIMD_Arrangement T, Register Xn) {
- starti;
- f(0,31), f((int)T & 1, 30), f(0b00110001000000, 29, 16), f(0b0111, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, Register Xn) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- f(0,31), f((int)T & 1, 30), f(0b00110001000000, 29, 16), f(0b1010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, SIMD_Arrangement T, Register Xn) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- f(0,31), f((int)T & 1, 30), f(0b00110001000000, 29, 16), f(0b0110, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, FloatRegister Vt4, SIMD_Arrangement T, Register Xn) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- assert((Vt4->encoding_nocheck()) == ((Vt->encoding_nocheck() + 3) % 32), "Invalid Vt4");
- f(0,31), f((int)T & 1, 30), f(0b00110001000000, 29, 16), f(0b0010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
-
- void v_ld1(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int imm) {
- starti;
- assert((8 << ((int)T & 1)) == imm, "size/imm mismatch");
- f(0, 31), f((int)T & 1, 30), f(0b001100110, 29, 21), f(0b11111, 20, 16), f(0b0111, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1(FloatRegister Vt, SIMD_Arrangement T, Register Xn, Register Xm) {
- starti;
- f(0, 31), f((int)T & 1, 30), f(0b001100110, 29, 21), rf(Xm, 16), f(0b0111, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, Register Xn, int imm) {
- starti;
- assert((16 << ((int)T & 1)) == imm, "size/imm mismatch");
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- f(0, 31), f((int)T & 1, 30), f(0b001100110, 29, 21), f(0b11111, 20, 16), f(0b1010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, Register Xn, Register Xm) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- f(0, 31), f((int)T & 1, 30), f(0b001100110, 29, 21), rf(Xm, 16), f(0b1010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, SIMD_Arrangement T, Register Xn, int imm) {
- starti;
- assert((24 << ((int)T & 1)) == imm, "size/imm mismatch");
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- f(0, 31), f((int)T & 1, 30), f(0b001100110, 29, 21), f(0b11111, 20, 16), f(0b0110, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, SIMD_Arrangement T, Register Xn, Register Xm) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- f(0, 31), f((int)T & 1, 30), f(0b001100110, 29, 21), rf(Xm, 16), f(0b0110, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, FloatRegister Vt4, SIMD_Arrangement T, Register Xn, int imm) {
- starti;
- assert((32 << ((int)T & 1)) == imm, "size/imm mismatch");
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- assert((Vt4->encoding_nocheck()) == ((Vt->encoding_nocheck() + 3) % 32), "Invalid Vt4");
- f(0, 31), f((int)T & 1, 30), f(0b001100110, 29, 21), f(0b11111, 20, 16), f(0b0010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, FloatRegister Vt4, SIMD_Arrangement T, Register Xn, Register Xm) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- assert((Vt4->encoding_nocheck()) == ((Vt->encoding_nocheck() + 3) % 32), "Invalid Vt4");
- f(0, 31), f((int)T & 1, 30), f(0b001100110, 29, 21), rf(Xm, 16), f(0b0010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
-
- void v_st1(FloatRegister Vt, SIMD_Arrangement T, Register Xn) {
- starti;
- f(0, 31), f((int)T & 1, 30), f(0b00110000000000, 29, 16), f(0b0111, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_st1(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, Register Xn) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- f(0, 31), f((int)T & 1, 30), f(0b00110000000000, 29, 16), f(0b1010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_st1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, SIMD_Arrangement T, Register Xn) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- f(0, 31), f((int)T & 1, 30), f(0b00110000000000, 29, 16), f(0b0110, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_st1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, FloatRegister Vt4, SIMD_Arrangement T, Register Xn) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- assert((Vt4->encoding_nocheck()) == ((Vt->encoding_nocheck() + 3) % 32), "Invalid Vt4");
- f(0, 31), f((int)T & 1, 30), f(0b00110000000000, 29, 16), f(0b0010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
-
- void v_st1(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int imm) {
- starti;
- assert((8 << ((int)T & 1)) == imm, "size/imm mismatch");
- f(0, 31), f((int)T & 1, 30), f(0b001100100, 29, 21), f(0b11111, 20, 16), f(0b0111, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_st1(FloatRegister Vt, SIMD_Arrangement T, Register Xn, Register Xm) {
- starti;
- f(0, 31), f((int)T & 1, 30), f(0b001100100, 29, 21), rf(Xm, 16), f(0b0111, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_st1(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, Register Xn, int imm) {
- starti;
- assert((16 << ((int)T & 1)) == imm, "size/imm mismatch");
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- f(0, 31), f((int)T & 1, 30), f(0b001100100, 29, 21), f(0b11111, 20, 16), f(0b1010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_st1(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, Register Xn, Register Xm) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- f(0, 31), f((int)T & 1, 30), f(0b001100100, 29, 21), rf(Xm, 16), f(0b1010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_st1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, SIMD_Arrangement T, Register Xn, int imm) {
- starti;
- assert((24 << ((int)T & 1)) == imm, "size/imm mismatch");
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- f(0, 31), f((int)T & 1, 30), f(0b001100100, 29, 21), f(0b11111, 20, 16), f(0b0110, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_st1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, SIMD_Arrangement T, Register Xn, Register Xm) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- f(0, 31), f((int)T & 1, 30), f(0b001100100, 29, 21), rf(Xm, 16), f(0b0110, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_st1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, FloatRegister Vt4, SIMD_Arrangement T, Register Xn, int imm) {
- starti;
- assert((32 << ((int)T & 1)) == imm, "size/imm mismatch");
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- assert((Vt4->encoding_nocheck()) == ((Vt->encoding_nocheck() + 3) % 32), "Invalid Vt4");
- f(0, 31), f((int)T & 1, 30), f(0b001100100, 29, 21), f(0b11111, 20, 16), f(0b0010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_st1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, FloatRegister Vt4, SIMD_Arrangement T, Register Xn, Register Xm) {
- starti;
- assert((Vt2->encoding_nocheck()) == ((Vt->encoding_nocheck() + 1) % 32), "Invalid Vt2");
- assert((Vt3->encoding_nocheck()) == ((Vt->encoding_nocheck() + 2) % 32), "Invalid Vt3");
- assert((Vt4->encoding_nocheck()) == ((Vt->encoding_nocheck() + 3) % 32), "Invalid Vt4");
- f(0, 31), f((int)T & 1, 30), f(0b001100100, 29, 21), rf(Xm, 16), f(0b0010, 15, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
-
- void v_ld1r(FloatRegister Vt, SIMD_Arrangement T, Register Xn) {
- starti;
- f(0, 31), f((int)T & 1, 30), f(0b001101010000001100, 29, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1r(FloatRegister Vt, SIMD_Arrangement T, Register Xn, Register Xm) {
- starti;
- f(0, 31), f((int)T & 1, 30), f(0b001101110, 29, 21), rf(Xm, 16);
- f(0b1100, 15, 12), f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
- void v_ld1r(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int imm) {
- starti;
- assert((1 << ((int)T & 3)) == imm, "size/imm mismatch");
- f(0, 31), f((int)T & 1, 30), f(0b001101110111111100, 29, 12);
- f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
- }
-
- void v_eor(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) {
- starti;
- assert(T == T8B || T == T16B, "must be T8B or T16B");
- f(0, 31), f((int)T & 1, 30), f(0b101110001, 29, 21);
- rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0);
- }
-
- void v_orr(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) {
- starti;
- assert(T == T8B || T == T16B, "must be T8B or T16B");
- f(0, 31), f((int)T & 1, 30), f(0b001110101, 29, 21);
- rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0);
- }
-
- void v_aese(FloatRegister Vd, FloatRegister Vn)
- {
- starti;
- f(0b0100111000101000010010, 31, 10), rf(Vn, 5), rf(Vd, 0);
- }
-
- void v_aesd(FloatRegister Vd, FloatRegister Vn)
- {
- starti;
- f(0b0100111000101000010110, 31, 10), rf(Vn, 5), rf(Vd, 0);
- }
-
- void v_aesmc(FloatRegister Vd, FloatRegister Vn)
- {
- starti;
- f(0b0100111000101000011010, 31, 10), rf(Vn, 5), rf(Vd, 0);
- }
-
- void v_aesimc(FloatRegister Vd, FloatRegister Vn)
- {
- starti;
- f(0b0100111000101000011110, 31, 10), rf(Vn, 5), rf(Vd, 0);
- }
-
void v_rev32(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn)
{
starti;
--- CUT HERE ---
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