[aarch64-port-dev ] RFR: Fix instruction size from 8 to 4

[Edward Nevill]

Hi,

I noticed while looking at the assembly output from C2 that the loops were not being aligned correctly as in this short code section

  0x0000007f8d170a84: mov       w0, wzr
  0x0000007f8d170a88: nop                       ;*iload_1
                                                ; - dhry::execute at 9 (line 8)

<<<<< Incorrectly aligned here

  ;; B6: #      B6 B7 <- B5 B6  Loop: B6-B6 inner  Freq: 4.99998

  0x0000007f8d170a8c: add       x12, x10, w11, sxtw #2
  0x0000007f8d170a90: ldr       w12, [x12,#16]
  0x0000007f8d170a94: add       w0, w0, w12     ;*iadd
                                                ; - dhry::execute at 15 (line 8)

  0x0000007f8d170a98: add       w11, w11, #0x1  ;*iinc
                                                ; - dhry::execute at 17 (line 7)

  0x0000007f8d170a9c: cmp       w11, w1
  0x0000007f8d170aa0: b.lt      0x0000007f8d170a8c

The reason for this is that instruction_size is incorrectly defined in nativeInst_aarch64.hpp. It was defined as BytesPerWord which is of course 8. I have changed this to '4'.

The code works out the no. of nops to emit as padding/instruction_size which explains why it emitted too few nops in the above.

I have applied the patch below and the code is now generated as

  0x0000007f88d83cc4: mov       w0, wzr
  0x0000007f88d83cc8: nop
  0x0000007f88d83ccc: nop                       ;*iload_1
                                                ; - dhry::execute at 9 (line 8)

  ;; B6: #      B6 B7 <- B5 B6  Loop: B6-B6 inner  Freq: 4.99998

  0x0000007f88d83cd0: add       x12, x10, w11, sxtw #2
  0x0000007f88d83cd4: ldr       w12, [x12,#16]
  0x0000007f88d83cd8: add       w0, w0, w12     ;*iadd
                                                ; - dhry::execute at 15 (line 8)

  0x0000007f88d83cdc: add       w11, w11, #0x1  ;*iinc
                                                ; - dhry::execute at 17 (line 7)

  0x0000007f88d83ce0: cmp       w11, w1
  0x0000007f88d83ce4: b.lt      0x0000007f88d83cd0

OK to push?
Ed.

--- CUT HERE ---
# HG changeset patch
# User Edward Nevill edward.nevill at linaro.org
# Date 1398952656 -3600
#      Thu May 01 14:57:36 2014 +0100
# Node ID f67f9b1b52ae8b1778dacb49df641bb5b6e48da1
# Parent  9d641fdeea4d1772617b097fc231dcff8e4aa634
Fix instruction size from 8 to 4

diff -r 9d641fdeea4d -r f67f9b1b52ae src/cpu/aarch64/vm/nativeInst_aarch64.hpp
--- a/src/cpu/aarch64/vm/nativeInst_aarch64.hpp	Tue Apr 29 14:58:56 2014 +0100
+++ b/src/cpu/aarch64/vm/nativeInst_aarch64.hpp	Thu May 01 14:57:36 2014 +0100
@@ -54,7 +54,7 @@
 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
   friend class Relocation;
  public:
-  enum { instruction_size = BytesPerWord };
+  enum { instruction_size = 4 };
   inline bool is_nop();
   bool is_dtrace_trap();
   inline bool is_call();
--- CUT HERE ---