[aarch64-port-dev ] Correct opto assembly for sign-extened operands

[Andrew Haley]

Does what it says.

# HG changeset patch
# User aph
# Date 1399901640 -3600
#      Mon May 12 14:34:00 2014 +0100
# Node ID ac30fdebd5f5811d768d493d58d40852cff0886c
# Parent  8a569467b81b8589fb4daa87b6d4292bafc206f9
Fix opto assembly for shifts.

diff -r 8a569467b81b -r ac30fdebd5f5 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Wed May 07 16:41:56 2014 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad	Mon May 12 14:34:00 2014 +0100
@@ -6988,7 +6988,7 @@
   match(Set dst (AddP src1 (ConvI2L src2)));

   ins_cost(INSN_COST);
-  format %{ "add $dst, $src1, $src2\t# ptr" %}
+  format %{ "add $dst, $src1, $src2, sxtw\t# ptr" %}

   ins_encode %{
     __ add(as_Register($dst$$reg),
@@ -7331,7 +7331,7 @@
 instruct div2Round(iRegINoSp dst, iRegI src, immI_31 div1, immI_31 div2) %{
   match(Set dst (AddI src (URShiftI (RShiftI src div1) div2)));
   ins_cost(INSN_COST);
-  format %{ "addw $dst, $src, $div1" %}
+  format %{ "addw $dst, $src, LSR $div1" %}

   ins_encode %{
     __ addw(as_Register($dst$$reg),
@@ -8957,7 +8957,7 @@
 %{
   match(Set dst (AddL src1 (ConvI2L src2)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1,  $src2" %}
+  format %{ "add  $dst, $src1,  $src2, sxtw" %}

    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -8970,7 +8970,7 @@
 %{
   match(Set dst (SubL src1 (ConvI2L src2)));
   ins_cost(INSN_COST);
-  format %{ "sub  $dst, $src1,  $src2" %}
+  format %{ "sub  $dst, $src1,  $src2, sxtw" %}

    ins_encode %{
      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -9036,7 +9036,7 @@
 %{
   match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxtw $src2" %}
+  format %{ "add  $dst, $src1, sxtw $src2, sxtw" %}

    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),