[aarch64-port-dev ] Fix a few problems in pipeline scheduling show by overnight tests

[Edward Nevill]

Hi,

The following patch fixes a couple of problems in the pipeline scheduling show up by the overnight tests.

- bytes_reverse_long needs an IRegL, not an iRegI
- overflowMulX_reg_branch needs pipe_serial otherwise it get confused and reschedules instructions across the branch.

I have also changed the 'iRegI src' in all bytes_reverse to 'iRegIorL2I src' for consistency.

All the best,
Ed.

--- CUT HERE ---
# HG changeset patch
# User Edward Nevill <ed at camswl.com>
# Date 1415026442 0
#      Mon Nov 03 14:54:02 2014 +0000
# Node ID 71547f5343652fa9899a772cae98138d950f0864
# Parent  788f964d727f063813c7a4d8c4b7254c33b5eeb1
Fix a few pipeline scheduling problems shown by overnight tests

diff -r 788f964d727f -r 71547f534365 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Fri Oct 31 21:04:37 2014 +0000
+++ b/src/cpu/aarch64/vm/aarch64.ad	Mon Nov 03 14:54:02 2014 +0000
@@ -6229,7 +6229,7 @@
 // ============================================================================
 // BSWAP Instructions
 
-instruct bytes_reverse_int(iRegINoSp dst, iRegI src) %{
+instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src) %{
   match(Set dst (ReverseBytesI src));
 
   ins_cost(INSN_COST);
@@ -6242,7 +6242,7 @@
   ins_pipe(ialu_reg);
 %}
 
-instruct bytes_reverse_long(iRegLNoSp dst, iRegI src) %{
+instruct bytes_reverse_long(iRegLNoSp dst, iRegL src) %{
   match(Set dst (ReverseBytesL src));
 
   ins_cost(INSN_COST);
@@ -6255,7 +6255,7 @@
   ins_pipe(ialu_reg);
 %}
 
-instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegI src) %{
+instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
   match(Set dst (ReverseBytesUS src));
 
   ins_cost(INSN_COST);
@@ -6268,7 +6268,7 @@
   ins_pipe(ialu_reg);
 %}
 
-instruct bytes_reverse_short(iRegINoSp dst, iRegI src) %{
+instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
   match(Set dst (ReverseBytesS src));
 
   ins_cost(INSN_COST);
@@ -10955,7 +10955,7 @@
     __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L);
   %}
 
-  ins_pipe(pipe_slow);
+  ins_pipe(pipe_serial);
 %}
 
 instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2)
@@ -11002,7 +11002,7 @@
     __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L);
   %}
 
-  ins_pipe(pipe_slow);
+  ins_pipe(pipe_serial);
 %}
 
 // ============================================================================
--- CUT HERE ---