[aarch64-port-dev ] RFR: Tidy up allocation prefetch

[Edward Nevill]

Hi,

The following patch tidies up a few issues with allocation prefetch

1) AllocatePrefetchStepSize was set to 16 by default

This default is changed to 64 as it makes little/no sense to have an AllocatePrefetchStepSize < size of cache line

2) A number of vestigial nops have been removed and uncomment 1 __ prfm

These nops seem to have survived from a time before prefetch allocation was implemented, judging by the logs.

In addition 1 of the __ prfm calls seemed to have been left commented out.

3) The existing code just stamped on the value of AllocatePrefetchDistance

Now changed so you can override this on the command line.

OK to push to jdk8 & jdk9?

Ed.

--- CUT HERE ---
# HG changeset patch
# User enevill
# Date 1415699691 0
#      Tue Nov 11 09:54:51 2014 +0000
# Node ID f0aa6a97d4e2da49faf603052facd1d1b2a3ca33
# Parent  dba43b2d5ad23ab6ec6f5a4eebe34198a3ff7afc
Tidy up allocation prefetch

diff -r dba43b2d5ad2 -r f0aa6a97d4e2 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Thu Nov 06 09:56:19 2014 -0500
+++ b/src/cpu/aarch64/vm/aarch64.ad	Tue Nov 11 09:54:51 2014 +0000
@@ -2409,16 +2409,13 @@
     int disp = $mem$$disp;
     if (index == -1) {
       __ prfm(Address(base, disp), PLDL1KEEP);
-      __ nop();
     } else {
       Register index_reg = as_Register(index);
       if (disp == 0) {
-        // __ prfm(Address(base, index_reg, Address::lsl(scale)), PLDL1KEEP);
-        __ nop();
+        __ prfm(Address(base, index_reg, Address::lsl(scale)), PLDL1KEEP);
       } else {
         __ lea(rscratch1, Address(base, disp));
 	__ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PLDL1KEEP);
-        __ nop();
       }
     }
   %}
@@ -2436,11 +2433,9 @@
       Register index_reg = as_Register(index);
       if (disp == 0) {
         __ prfm(Address(base, index_reg, Address::lsl(scale)), PSTL1KEEP);
-        __ nop();
       } else {
         __ lea(rscratch1, Address(base, disp));
 	__ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1KEEP);
-        __ nop();
       }
     }
   %}
@@ -2453,7 +2448,6 @@
     int disp = $mem$$disp;
     if (index == -1) {
       __ prfm(Address(base, disp), PSTL1STRM);
-      __ nop();
     } else {
       Register index_reg = as_Register(index);
       if (disp == 0) {
@@ -2462,7 +2456,6 @@
       } else {
         __ lea(rscratch1, Address(base, disp));
 	__ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1STRM);
-        __ nop();
       }
     }
   %}
diff -r dba43b2d5ad2 -r f0aa6a97d4e2 src/cpu/aarch64/vm/vm_version_aarch64.cpp
--- a/src/cpu/aarch64/vm/vm_version_aarch64.cpp	Thu Nov 06 09:56:19 2014 -0500
+++ b/src/cpu/aarch64/vm/vm_version_aarch64.cpp	Tue Nov 11 09:54:51 2014 +0000
@@ -101,7 +101,10 @@
   _supports_atomic_getset8 = true;
   _supports_atomic_getadd8 = true;
 
-  FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
+  if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
+    FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
+  if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
+    FLAG_SET_DEFAULT(AllocatePrefetchStepSize, 64);
   FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 256);
   FLAG_SET_DEFAULT(PrefetchFieldsAhead, 256);
   FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 256);
--- CUT HERE ---