[aarch64-port-dev ] /hg/icedtea7-forest-aarch64/hotspot: 3 new changesets
Andrew Dinn
adinn at redhat.com
Mon Nov 24 09:07:10 UTC 2014
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Subject: /hg/icedtea7-forest-aarch64/hotspot: 3 new changesets
From: adinn at icedtea.classpath.org
X-Hg-Notification: changeset 4df02e5f0433
Message-Id:
<hg.4df02e5f0433.1416819968.-5017525213744097322 at icedtea.classpath.org>
To: aarch64-port-dev at openjdk.java.net
changeset 4df02e5f0433 in /hg/icedtea7-forest-aarch64/hotspot
details:
http://icedtea.classpath.org/hg/icedtea7-forest-aarch64/hotspot?cmd=changeset;node=4df02e5f0433
author: adinn
date: Fri Nov 21 19:18:22 2014 +0000
Add some memory barriers for object creation and runtime calls.
changeset 93b1103ebb83 in /hg/icedtea7-forest-aarch64/hotspot
details:
http://icedtea.classpath.org/hg/icedtea7-forest-aarch64/hotspot?cmd=changeset;node=93b1103ebb83
author: adinn
date: Fri Nov 21 20:26:35 2014 +0000
Call ICache::invalidate_range() from Relocation::pd_set_data_value().
also includes corrections supplied by Ed in 7818 dba43b2d5ad2
changeset 4868ef1912f1 in /hg/icedtea7-forest-aarch64/hotspot
details:
http://icedtea.classpath.org/hg/icedtea7-forest-aarch64/hotspot?cmd=changeset;node=4868ef1912f1
author: adinn
date: Fri Nov 21 20:35:24 2014 +0000
Tidy up allocation prefetch
diffstat:
src/cpu/aarch64/vm/aarch64.ad | 10 +-----
src/cpu/aarch64/vm/assembler_aarch64.cpp | 35
++++++++++++++++-----
src/cpu/aarch64/vm/assembler_aarch64.hpp | 7 +++-
src/cpu/aarch64/vm/relocInfo_aarch64.cpp | 13 ++++++-
src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp | 3 +-
src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp | 1 +
src/cpu/aarch64/vm/templateTable_aarch64.cpp | 4 ++
src/cpu/aarch64/vm/vm_version_aarch64.cpp | 5 ++-
8 files changed, 54 insertions(+), 24 deletions(-)
diffs (257 lines):
diff -r ae4b26e6783b -r 4868ef1912f1 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Fri Nov 21 13:21:30 2014 +0000
+++ b/src/cpu/aarch64/vm/aarch64.ad Fri Nov 21 20:35:24 2014 +0000
@@ -2406,16 +2406,13 @@
int disp = $mem$$disp;
if (index == -1) {
__ prfm(Address(base, disp), PLDL1KEEP);
- __ nop();
} else {
Register index_reg = as_Register(index);
if (disp == 0) {
- // __ prfm(Address(base, index_reg, Address::lsl(scale)),
PLDL1KEEP);
- __ nop();
+ __ prfm(Address(base, index_reg, Address::lsl(scale)), PLDL1KEEP);
} else {
__ lea(rscratch1, Address(base, disp));
__ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PLDL1KEEP);
- __ nop();
}
}
%}
@@ -2433,11 +2430,9 @@
Register index_reg = as_Register(index);
if (disp == 0) {
__ prfm(Address(base, index_reg, Address::lsl(scale)), PSTL1KEEP);
- __ nop();
} else {
__ lea(rscratch1, Address(base, disp));
__ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1KEEP);
- __ nop();
}
}
%}
@@ -2450,16 +2445,13 @@
int disp = $mem$$disp;
if (index == -1) {
__ prfm(Address(base, disp), PSTL1STRM);
- __ nop();
} else {
Register index_reg = as_Register(index);
if (disp == 0) {
__ prfm(Address(base, index_reg, Address::lsl(scale)), PSTL1STRM);
- __ nop();
} else {
__ lea(rscratch1, Address(base, disp));
__ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1STRM);
- __ nop();
}
}
%}
diff -r ae4b26e6783b -r 4868ef1912f1
src/cpu/aarch64/vm/assembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.cpp Fri Nov 21 13:21:30 2014
+0000
+++ b/src/cpu/aarch64/vm/assembler_aarch64.cpp Fri Nov 21 20:35:24 2014
+0000
@@ -1573,7 +1573,8 @@
// Implementation of MacroAssembler
-void MacroAssembler::pd_patch_instruction(address branch, address target) {
+int MacroAssembler::pd_patch_instruction_size(address branch, address
target) {
+ int instructions = 1;
assert((uint64_t)target < (1ul << 48), "48-bit overflow in address
constant");
long offset = (target - branch) >> 2;
unsigned insn = *(unsigned*)branch;
@@ -1634,6 +1635,7 @@
Instruction_aarch64::patch(branch + sizeof (unsigned),
21, 10, offset_lo >> size);
guarantee(((dest >> size) << size) == dest, "misaligned target");
+ instructions = 2;
} else if (Instruction_aarch64::extract(insn2, 31, 22) ==
0b1001000100 &&
Instruction_aarch64::extract(insn, 4, 0) ==
Instruction_aarch64::extract(insn2, 4, 0)) {
@@ -1643,6 +1645,7 @@
(offset_lo & 0x3FFl) == 0, "offset must be 0x400 aligned for crc_table");
Instruction_aarch64::patch(branch + sizeof (unsigned),
21, 10, offset_lo);
+ instructions = 2;
} else {
assert((jbyte *)target ==
((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base ||
@@ -1665,6 +1668,7 @@
Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff);
Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
assert(pd_call_destination(branch) == target, "should be");
+ instructions = 2;
} else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
// nothing to do
@@ -1672,19 +1676,34 @@
} else {
ShouldNotReachHere();
}
+ return instructions * NativeInstruction::instruction_size;
}
-void MacroAssembler::patch_oop(address insn_addr, address o) {
+int MacroAssembler::patch_oop(address insn_addr, address o) {
+ int instructions;
unsigned insn = *(unsigned*)insn_addr;
+ assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in
patch");
+
+ // OOPs are either narrow (32 bits) or wide (48 bits). We encode
+ // narrow OOPs by setting the upper 16 bits in the first
+ // instruction.
if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
- // Move narrow constant
- assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns
in patch");
- narrowOop n = oopDesc::encode_heap_oop((oop)o);
- Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
- Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
+ // Move narrow OOP
+ assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns
in patch");
+ narrowOop n = oopDesc::encode_heap_oop((oop)o);
+ Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
+ Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
+ instructions = 2;
} else {
- pd_patch_instruction(insn_addr, o);
+ // Move wide OOP
+ assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns
in patch");
+ uintptr_t dest = (uintptr_t)o;
+ Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
+ Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
+ Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
+ instructions = 3;
}
+ return instructions * NativeInstruction::instruction_size;
}
address MacroAssembler::target_addr_for_insn(address insn_addr,
unsigned insn) {
diff -r ae4b26e6783b -r 4868ef1912f1
src/cpu/aarch64/vm/assembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp Fri Nov 21 13:21:30 2014
+0000
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp Fri Nov 21 20:35:24 2014
+0000
@@ -2727,7 +2727,10 @@
// Required platform-specific helpers for Label::patch_instructions.
// They _shadow_ the declarations in AbstractAssembler, which are
undefined.
- static void pd_patch_instruction(address branch, address target);
+ static int pd_patch_instruction_size (address branch, address target);
+ static void pd_patch_instruction(address branch, address target) {
+ pd_patch_instruction_size (branch, target);
+ }
static address pd_call_destination(address branch) {
unsigned insn = *(unsigned*)branch;
return target_addr_for_insn(branch, insn);
@@ -2736,7 +2739,7 @@
static void pd_print_patched_instruction(address branch);
#endif
- static void patch_oop(address insn_addr, address o);
+ static int patch_oop(address insn_addr, address o);
// The following 4 methods return the offset of the appropriate move
instruction
diff -r ae4b26e6783b -r 4868ef1912f1
src/cpu/aarch64/vm/relocInfo_aarch64.cpp
--- a/src/cpu/aarch64/vm/relocInfo_aarch64.cpp Fri Nov 21 13:21:30 2014
+0000
+++ b/src/cpu/aarch64/vm/relocInfo_aarch64.cpp Fri Nov 21 20:35:24 2014
+0000
@@ -34,23 +34,30 @@
void Relocation::pd_set_data_value(address x, intptr_t o, bool
verify_only) {
+ if (verify_only) {
+ return;
+ }
+
+ int bytes;
+
switch(type()) {
case relocInfo::oop_type:
{
oop_Relocation *reloc = (oop_Relocation *)this;
if (NativeInstruction::is_ldr_literal_at(addr())) {
address constptr = (address)code()->oop_addr_at(reloc->oop_index());
- MacroAssembler::pd_patch_instruction(addr(), constptr);
+ bytes = MacroAssembler::pd_patch_instruction_size(addr(), constptr);
assert(*(address*)constptr == x, "error in oop relocation");
} else{
- MacroAssembler::patch_oop(addr(), x);
+ bytes = MacroAssembler::patch_oop(addr(), x);
}
}
break;
default:
- MacroAssembler::pd_patch_instruction(addr(), x);
+ bytes = MacroAssembler::pd_patch_instruction_size(addr(), x);
break;
}
+ ICache::invalidate_range(addr(), bytes);
}
address Relocation::pd_call_destination(address orig_addr) {
diff -r ae4b26e6783b -r 4868ef1912f1
src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp
--- a/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp Fri Nov 21 13:21:30
2014 +0000
+++ b/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp Fri Nov 21 20:35:24
2014 +0000
@@ -319,7 +319,8 @@
__ mov(c_rarg1, lr);
__ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address,
SharedRuntime::fixup_callers_callsite)));
__ blrt(rscratch1, 2, 0, 0);
- __ maybe_isb();
+ __ maybe_isb();
+ __ membar(Assembler::LoadLoad | Assembler::LoadStore);
__ pop_CPU_state();
// restore sp
diff -r ae4b26e6783b -r 4868ef1912f1
src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp Fri Nov 21
13:21:30 2014 +0000
+++ b/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp Fri Nov 21
20:35:24 2014 +0000
@@ -325,6 +325,7 @@
address entry = __ pc();
__ push(state);
__ call_VM(noreg, runtime_entry);
+ __ membar(Assembler::AnyAny);
__ dispatch_via(vtos, Interpreter::_normal_table.table_for(vtos));
return entry;
}
diff -r ae4b26e6783b -r 4868ef1912f1
src/cpu/aarch64/vm/templateTable_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp Fri Nov 21 13:21:30
2014 +0000
+++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp Fri Nov 21 20:35:24
2014 +0000
@@ -3391,6 +3391,8 @@
// continue
__ bind(done);
+ // Must prevent reordering of stores for object initialization with
stores that publish the new object.
+ __ membar(Assembler::StoreStore);
}
void TemplateTable::newarray() {
@@ -3399,6 +3401,7 @@
__ mov(c_rarg2, r0);
call_VM(r0, CAST_FROM_FN_PTR(address, InterpreterRuntime::newarray),
c_rarg1, c_rarg2);
+ __ membar(Assembler::StoreStore);
}
void TemplateTable::anewarray() {
@@ -3408,6 +3411,7 @@
__ mov(c_rarg3, r0);
call_VM(r0, CAST_FROM_FN_PTR(address, InterpreterRuntime::anewarray),
c_rarg1, c_rarg2, c_rarg3);
+ __ membar(Assembler::StoreStore);
}
void TemplateTable::arraylength() {
diff -r ae4b26e6783b -r 4868ef1912f1
src/cpu/aarch64/vm/vm_version_aarch64.cpp
--- a/src/cpu/aarch64/vm/vm_version_aarch64.cpp Fri Nov 21 13:21:30 2014
+0000
+++ b/src/cpu/aarch64/vm/vm_version_aarch64.cpp Fri Nov 21 20:35:24 2014
+0000
@@ -105,7 +105,10 @@
_supports_atomic_getset8 = true;
_supports_atomic_getadd8 = true;
- FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
+ if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
+ FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
+ if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
+ FLAG_SET_DEFAULT(AllocatePrefetchStepSize, 64);
FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 256);
FLAG_SET_DEFAULT(PrefetchFieldsAhead, 256);
FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 256);
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