[aarch64-port-dev ] RFR: aarch64: 8133842: C2 generates illegal instructions with int shifts >=32

[Vladimir Kozlov]

Changes are fine but I am curious why results will be the same even if you mask less bits - I don't see predicates which 
checks shift's value (to select different instructions for different shift values) and you use general immI operand type 
for it.

Thanks,
Vladimir

On 8/20/15 3:47 AM, Edward Nevill wrote:
> Hi,
>
> The following webrev
>
> http://cr.openjdk.java.net/~enevill/8133842/webrev.01/
>
> fixes a problem reported by one of our partners whereby C2 can generate illegal instructions on certain partners HW.
>
> JIRA issue here
>
> https://bugs.openjdk.java.net/browse/JDK-8133842
>
> The problem occurs when you have a logical or arithmetic instruction with a RHS which is shifted by a constant where (const & 32) != 0, ie the constant is 32..63 or 96..127 etc.
>
> For example the following
>
>    res = i | (j >> 53)
>
> generates the instruction
>
>    orrw Rd, Rn, Rm, ASR #53
>
> This instruction has a 6 bit field for the shift so this would appear to be a legal encoding. However certain partner HW treats this as an undefined instruction generating a SIGILL.
>
> The problem was that the rules in aarch64.ad were always anding the constant with 0x3f for both ints and longs.
>
> The above webrev fixes this to mask with 0x1f for ints and 0x3f for longs.
>
> Tested with hotspot and langtools. Results the same in both cases.
>
> Hotspot: Test results: passed: 863; failed: 2; error: 10
> Langtools: Test results: passed: 3,263
>
> Thanks for your help with this review,
> Ed.
>
>