[aarch64-port-dev ] RFR: aarch64: 8133842: C2 generates illegal instructions with int shifts >=32

[Vladimir Kozlov]

Thank you. Andrew answered my question (only 0-31 values are meaningful).
I thought you had on low level asm instruction masking already.
For example on sparc we use u_field(imm5a, 4, 0):

void sll(  Register s1, int imm5a,   Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | 
immed(true) | u_field(imm5a, 4, 0) ); }

It looks like you have to mask on more high level then we do on SPARC.

Again, changes are good.

Thanks,
Vladimir

On 8/20/15 9:06 AM, Edward Nevill wrote:
> On Thu, 2015-08-20 at 08:55 -0700, Vladimir Kozlov wrote:
>> Changes are fine but I am curious why results will be the same even if you mask less bits - I don't see predicates which
>> checks shift's value (to select different instructions for different shift values) and you use general immI operand type
>> for it.
>
> Not sure I understand the question.
>
> Currently it generate
>
>      orrw Rd, Rn, Rm, ASR #53
>
> Rd, Rn and Rm are 32 bit here (for orrw as opposed to orr).
>
> So on our partners implementation this generates a SIGILL.
>
> The webrev change this to
>
>      orrw Rd, Rn, Rm, ASR #21
>
> which is correct (for Java).
>
> All the best,
> Ed.
>
>