[aarch64-port-dev ] Guarantee failures since 8144028: Use AArch64 bit-test instructions in C2

[Edward Nevill]

On Wed, 2015-12-09 at 19:00 +0000, Andrew Haley wrote:
> On 12/08/2015 06:22 PM, Edward Nevill wrote:
> > Hi,
> > 
> > Since "8144028: Use AArch64 bit-test instructions in C2" I have been seeing occasional guarantee failures of the form.
> > 
> > #  Internal Error (assembler_aarch64.hpp:223), pid=4241, tid=4595
> > #  guarantee(chk == -1 || chk == 0) failed: Field too big for insn
> > 
> > These are being generated by the following call from pd_patch_instruction_size in macroAssembler_aarch64.cpp
> > 
> >     // Test & branch (immediate)
> >     Instruction_aarch64::spatch(branch, 18, 5, offset);
> > 
> > The problem is that test and branch instructions only have a 14 bit offset giving a range of +/- 32Kb which is not sufficient for large C2 methods.
> > 
> > What can we do about this? It seems a shame to backout this optimization but I cannot see any easy way around it.
> 
> Please try this patch.

I think the following patch is needed in addition.

diff -r af66c2e5a0f6 src/cpu/aarch64/vm/interp_masm_aarch64.cpp
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Thu Dec 10 15:58:02 2015 +0000
+++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Thu Dec 10 17:02:12 2015 +0000
@@ -1355,8 +1355,9 @@
   if (JvmtiExport::can_post_interpreter_events()) {
     Label L;
     ldr(r3, Address(rthread, JavaThread::interp_only_mode_offset()));
-    tst(r3, ~0);
-    br(Assembler::EQ, L);
+//    tst(r3, ~0);
+//    br(Assembler::EQ, L);
+    cbz(r3, L);
     call_VM(noreg, CAST_FROM_FN_PTR(address,
                                     InterpreterRuntime::post_method_entry));
     bind(L);

Regards,
Ed.