[aarch64-port-dev ] AArch64: vectorization fails RSA crypto tests

[Edward Nevill]

On 15 June 2015 at 17:21, Andrew Haley <aph at redhat.com> wrote:

>
>
> diff -r 6217fd2c767b src/cpu/aarch64/vm/assembler_aarch64.hpp
> --- a/src/cpu/aarch64/vm/assembler_aarch64.hpp  Fri Jun 12 16:09:45 2015
> +0100
> +++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp  Mon Jun 15 17:16:58 2015
> +0100
> @@ -491,6 +491,11 @@
>          i->rf(_index, 16);
>          i->f(_ext.option(), 15, 13);
>          unsigned size = i->get(31, 30);
> +        if (i->get(26, 26) && i->get(23, 23)) {
> +          // SIMD Q Type - Size = 128 bits
> +          assert(size == 0, "bad size");
> +          size = 0b100;
> +        }
>          if (size == 0) // It's a byte
>            i->f(_ext.shift() >= 0, 12);
>          else {
>

Oops, sorry about that.

The following fixes the assertion failure in
java/math/BigInteger/BigIntegerTest.java

diff -r 6217fd2c767b src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp     Fri Jun 12 16:09:45
2015 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp     Mon Jun 15 20:20:12
2015 +0000
@@ -477,8 +477,11 @@
   //   T1D/T2D: invalid
   void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) {
     assert(T != T1D && T != T2D, "invalid arrangement");
+    if (T == T8B || T == T16B) {
+      movi(Vd, T, imm32 & 0xff, 0);
+      return;
+    }
     u_int32_t nimm32 = ~imm32;
-    if (T == T8B || T == T16B) { imm32 &= 0xff; nimm32 &= 0xff; }
     if (T == T4H || T == T8H) { imm32 &= 0xffff; nimm32 &= 0xffff; }
     u_int32_t x = imm32;
     int movi_cnt = 0;

Would you like me to merge these two as a single patch, file a JBS
"regression" bug report and push a cr.

All the best,
Ed.