[aarch64-port-dev ] Proposed patch for C2 volatile generation (resent)

[Andrew Haley]

On 03/27/2015 04:25 PM, Andrew Dinn wrote:
> The current rules translate that sequence to
> 
>   dmb ish
>   str<x>
>   dmb ish
> 
> i.e. they add a redundant dmb after the store. This is achieved by
> translating all MemBarRelease nodes to a dmb ish, all MemBarVolatile
> nodes to a dmb ish and all StoreX nodes to a normal (non-releasing)
> store. Clearly, for a volatile store the trailing dmb is redundant.

That's not quite right.  The JMM requires the trailing barrier because
all volatile loads and stores are sequentially consistent, so stores
must become visible immediately.  A preceding barrier is insufficient
for a volatile store.

> Even if the above concern is justified when the volatile write node
> pattern is seen there can be no harm in translating the first two nodes
> into a stlr<x>. If the above translation is valid then the following
> will be semantically equivalent and hence also valid:
> 
>   stlr<x>
>   dmb ish

STLR will do: it satisfies all the rules in the JMM.  The rules in the
AArch64 specification are quite subtle, but they amount to full
sequential consistency if volatile stores are always observed by
volatile loads.

> We really only want
> 
>   stlr<x>
> 
> or
> 
>   dmb ish
>   stl<x>

Again, STLR is sufficient.

Andrew.