[aarch64-port-dev ] Proposed patch for C2 volatile generation (resent)

[Andrew Dinn]

On 30/03/15 10:10, Andrew Dinn wrote:
> I'll prepare a suitably tweaked patch and post that for review.

Attached is a revised version of the patch.

I have managed to test inlining of various unsafe operations, in
particular the Unsafe.putVolatile + Unsafe.fullFence sequence I thought
might be a problem (the corner case). The rules only elide the barriers
when we have a put volatile.

As regards the corner case it turns out that the respective inlined
volatile barriers are separated by a cpuorder barrier. So, the double
elision I was worried about (by the matcher and then by my adlc rules)
will never happen. Also, it sems that the matcher routine which does
elision of repeated membar volatiles never gets called anyway. So, the
corner case does not arise.

Another thing I discovered by testing of Unsafe calls is that an inlined
Unsafe.putVolatile results in this node sequence

  MemBarRelease
  MemBarCPUOrder
  StoreI[mo_release]
  MemBarVolatile

i.e. compared with the translation of a normal volatile write there is
an extra MemBarCPUOrder node in the sequence. I have modified the
predicates which inhibit dmb generation (unnecessary_release and
unnecessary_volatile) so that they detect the node signature with or
without this intermediate MemBarCPUOrder.

regards,


Andrew Dinn
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