[aarch64-port-dev ] DMB elimination in C2 synchronization implementation

[Andrew Haley]

On 09/01/2015 04:06 PM, Wei Tang wrote:

>   We investigated aarch64 C2 synchronization implementation recently, and
> found some space to improve, please take a look.
> 
> The attached is patch and some supporting figures.

This may be OK, but we have been here before.  We used to have empty
barriers before and after lock operations and do everything internally
with ldaxr/stlxr but I reversed that because of correctness concerns:

http://mail.openjdk.java.net/pipermail/aarch64-port-dev/2014-May/001096.html

Unfortunately I did not explain my reasoning in the email, and I
cannot now remember.  It may have been to do with the question of
whether CAS needs to be a full barrier if the store fails: it's always
been hard to discover the assumptions made about memory operations by
programmers.

I'm tempted to accept this patch.

Andrew.