[aarch64-port-dev ] RFR: 8134869: AARCH64: GHASH intrinsic is not optimal

[Edward Nevill]

On Wed, 2015-09-02 at 09:55 +0100, Andrew Haley wrote:
> On 09/02/2015 09:52 AM, Edward Nevill wrote:
> > One minor point. The following seems to have suffered some whitespace mangling.
> 
> It's whitespace correction: the lines are way too wide, and it's hard to
> read the rest unless you have a super-wide editor.

OK. But the changeset as posted

http://cr.openjdk.java.net/~aph/8134869-ghash-1/

seems to have TABs embedded in it. I thought this was verboten?

If I edit the changset in vi with ":se list" I get

   // Table vector lookup$
-#define INSN(NAME, op)                                                                                       \$
-  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) {  \$
-    starti;                                                                                                  \$
-    assert(T == T8B || T == T16B, "invalid arrangement");                                                    \$
-    assert(0 < registers && registers <= 4, "invalid number of registers");                                  \$
-    f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15);                               \$
-    f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0);                               \$
+#define INSN(NAME, op)^I^I^I^I^I^I^I\$
+  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \$
+    starti;^I^I^I^I^I^I^I^I\$
+    assert(T == T8B || T == T16B, "invalid arrangement");^I^I\$
+    assert(0 < registers && registers <= 4, "invalid number of registers"); \$
+    f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \$
+    f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \$

All the best,
Ed.