[aarch64-port-dev ] DMB elimination in C2 synchronization implementation

[Andrew Haley]

This hunk is odd:

@@ -8381,7 +8458,7 @@
     "cmpw rscratch1, zr\t# EQ on successful write"
   %}

-  ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval));
+  ins_encode(aarch64_enc_cmpxchg_acq(mem, oldval, newval));

   ins_pipe(pipe_slow);
 %}
@@ -8398,7 +8475,7 @@
     "cmpw rscratch1, zr\t# EQ on successful write"
   %}

-  ins_encode(aarch64_enc_cmpxchgw(mem, oldval, newval));
+  ins_encode(aarch64_enc_cmpxchgw_acq(mem, oldval, newval));

   ins_pipe(pipe_slow);
 %}

In it, you strengthen storeLConditional and storeIConditional to use acq.

However, you do not strengthen storePConditional.

What is this for?

Andrew.