[aarch64-port-dev ] RFR: aarch64: add support for vectorizing floating-point fabs & fneg

[Felix Yang]

Hi,

    As the patch is not trivial, I also managed to put it on a http server
for your convenience.
    Please review this:
http://people.linaro.org/~felix.yang/aarch64-fabs-fneg-v1.diff
    Thanks for your help.

Felix


On 24 September 2015 at 21:22, Felix Yang <felix.yang at linaro.org> wrote:

> Hi,
>
>     I would like to contribute support for vectorizing fabs & fneg
> instructions on aarch64 architecture.
>     The patch takes a similar way as adding support for vectorizing double
> precision sqrt on Intel architectures.  And two new tests are added.
>     The performance gain for the "sumReductionImplement" function is: 30%
> for single precision and 10% for double precision with LoopMaxUnroll=16.
>     I have tested this with JTreg hotspot+langtools+jdk with no
> regressions.  Is it OK?
>     As this patch involves changes to shared code, I also need an Oracle
> sponsor for it if approved.
>
> Thanks,
> Felix
>