[aarch64-port-dev ] RFR(s): 8149418 AArch64: replace tst+br with tbz instruction when tst's constant operand is 2 power

[Hui Shi]

Would someone help review this webrev? Finding this when adding byte arrays
equals for aarch64 early.

webrev: http://cr.openjdk.java.net/~hshi/8149418/webrev/
bug: https://bugs.openjdk.java.net/browse/JDK-8149418

Replace consecutive tst + br instructions  with tbz/tbnz when constant is 2
power and not zero. This patch perform following actions
1. tst(r, constant) + br(EQ, L) -> tbz(r, exact_log2(constant), L)
2. tst(r, constant) + br(NE, L) -> tbnz(r, exact_log2(constant), L)

For remaining tst+br patterns:
1. Most are assertion for debug build, leave them there.
2. tst source register is redefined before branch, code sequence tst(r,
constant) + ldr(r ..) + br(EQ, L), optimize this need another register.

Regards
Hui