[aarch64-port-dev ] Help with SIMD for string_compare

[Pinski, Andrew]

What about doing addv (adding across lanes) and then seeing if that result is zero.
Something like:
addv h0, v0.8h
mov w0, s0
cbnz w0, diff

Thanks,
Andrew

-----Original Message-----
From: aarch64-port-dev [mailto:aarch64-port-dev-bounces at openjdk.java.net] On Behalf Of Edward Nevill
Sent: Wednesday, May 18, 2016 7:22 AM
To: aarch64-port-dev at openjdk.java.net
Cc: simon.hosie at arm.com
Subject: [aarch64-port-dev ] Help with SIMD for string_compare

Hi,

I am trying to implement string_compare for the UL & LU variants using the SIMD zip1 instruction, so the loop looks something like (for LU)

loop:
   ldr v0.8b, [str1, cnt1]
   ldr v1.8h, [str2, cnt2]
   eor v0.16b, v0,16b, v1.16b
   < cbnz v0, differ >
   add cnt1, cnt1, #8
   adds cnt2, cnt2, #16
   blt loop

But I can find no easy way to do < cbnz v0, differ > in SIMD. The alternative would be to do something like

   < vcmp v0.8h, v1.8h >
   bne differ

but I can find no instruction to do a bitwise vector comparison, only FCMP which does a floating point comparison.

Am I missing something, or is there any way to do this?

Thanks,
Ed.