[aarch64-port-dev ] Backports from jdk9 to aarch64-port/jdk8u

[Stuart Monteith]

Hi,
   Thanks for that. There was one error - 8169901 does not apply and I
shouldn't have included it on the list. Those intrinsics are generated
by cas.m4, and aren't meaningful for jdk8u.
The patchset compiles cleanly against the current tip of
aarch64-port/jdk8u . A sniff test runs ok (a short SPECjbb2015 run) -
I'll kick off a JCStress/JTReg run too.

For clarity, the patchset is:

8173472: AArch64: C1 comparisons with null only use 32-bit instructions
         https://bugs.openjdk.java.net/browse/JDK-8173472
         http://hg.openjdk.java.net/jdk9/dev/hotspot/rev/b53b0251e250

8172881: AArch64: assertion failure: the int pressure is incorrect
         https://bugs.openjdk.java.net/browse/JDK-8172881
         http://hg.openjdk.java.net/jdk9/dev/hotspot/rev/bfa8e4b0d4e2


8170100: AArch64: Crash in C1-compiled code accessing References
         https://bugs.openjdk.java.net/browse/JDK-8170100
         http://hg.openjdk.java.net/jdk9/dev/hotspot/rev/52d18f20804b


BR,
    Stuart

# HG changeset patch
# User aph
# Date 1479749893 0
#      Mon Nov 21 17:38:13 2016 +0000
# Node ID 67dfa7ba19e65e69526b940a422345eafba44dec
# Parent  64d241247b0662f0f77e7eda2d1ea09a5b63a524
8170100: AArch64: Crash in C1-compiled code accessing References
Reviewed-by: roland

diff -r 64d241247b06 -r 67dfa7ba19e6
src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp Fri Oct 07
15:59:38 2016 +0200
+++ b/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp Mon Nov 21
17:38:13 2016 +0000
@@ -694,7 +694,7 @@
   //   and so we don't need to call the G1 pre-barrier. Thus we can use the
   //   regular method entry code to generate the NPE.
   //
-  // This code is based on generate_accessor_enty.
+  // This code is based on generate_accessor_entry.
   //
   // rmethod: Method*
   // r13: senderSP must preserve for slow path, set SP to it on fast path
@@ -712,11 +712,11 @@
     __ ldr(local_0, Address(esp, 0));
     __ cbz(local_0, slow_path);

-
     // Load the value of the referent field.
     const Address field_address(local_0, referent_offset);
     __ load_heap_oop(local_0, field_address);

+    __ mov(r19, r13);   // Move senderSP to a callee-saved register
     // Generate the G1 pre-barrier code to log the value of
     // the referent field in an SATB buffer.
     __ enter(); // g1_write may call runtime
@@ -728,7 +728,7 @@
                             true /* expand_call */);
     __ leave();
     // areturn
-    __ andr(sp, r13, -16);  // done with stack
+    __ andr(sp, r19, -16);  // done with stack
     __ ret(lr);

     // generate a vanilla interpreter entry as the slow path
# HG changeset patch
# User njian
# Date 1485074034 -28800
#      Sun Jan 22 16:33:54 2017 +0800
# Node ID ee08f247222da94981c3c8ff4e0ff0e713b168fd
# Parent  35600737c103f09e399697f6f3cf22fc4c862b7e
8172881: AArch64: assertion failure: the int pressure is incorrect
Summary: Change the dst register type of get_and_setI/L/N/P from any
register to non-special register.
Reviewed-by: aph
Contributed-by: yang.zhang at linaro.org

diff -r 35600737c103 -r ee08f247222d src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Tue Dec 20 15:49:30 2016 -0500
+++ b/src/cpu/aarch64/vm/aarch64.ad Sun Jan 22 16:33:54 2017 +0800
@@ -9677,7 +9677,7 @@
 %}


-instruct get_and_setI(indirect mem, iRegINoSp newv, iRegI prev) %{
+instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev) %{
   match(Set prev (GetAndSetI mem newv));
   format %{ "atomic_xchgw  $prev, $newv, [$mem]" %}
   ins_encode %{
@@ -9686,7 +9686,7 @@
   ins_pipe(pipe_serial);
 %}

-instruct get_and_setL(indirect mem, iRegLNoSp newv, iRegL prev) %{
+instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev) %{
   match(Set prev (GetAndSetL mem newv));
   format %{ "atomic_xchg  $prev, $newv, [$mem]" %}
   ins_encode %{
@@ -9695,7 +9695,7 @@
   ins_pipe(pipe_serial);
 %}

-instruct get_and_setN(indirect mem, iRegNNoSp newv, iRegI prev) %{
+instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev) %{
   match(Set prev (GetAndSetN mem newv));
   format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
   ins_encode %{
@@ -9704,7 +9704,7 @@
   ins_pipe(pipe_serial);
 %}

-instruct get_and_setP(indirect mem, iRegPNoSp newv, iRegP prev) %{
+instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev) %{
   match(Set prev (GetAndSetP mem newv));
   format %{ "atomic_xchg  $prev, $newv, [$mem]" %}
   ins_encode %{
# HG changeset patch
# User aph
# Date 1485510615 0
#      Fri Jan 27 09:50:15 2017 +0000
# Node ID a2c49092763aa13f0c64e6ad14e50052b6131190
# Parent  ee08f247222da94981c3c8ff4e0ff0e713b168fd
8173472: AArch64: C1 comparisons with null only use 32-bit instructions
Reviewed-by: roland

diff -r bfa8e4b0d4e2 -r b53b0251e250
src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp

diff -r ee08f247222d -r a2c49092763a
src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Sun Jan 22
16:33:54 2017 +0800
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Fri Jan 27
09:50:15 2017 +0000
@@ -1982,12 +1982,17 @@
     }

     if (opr2->is_constant()) {
+      bool is_32bit = false; // width of register operand
       jlong imm;
+
       switch(opr2->type()) {
-      case T_LONG:
+      case T_INT:
+        imm = opr2->as_constant_ptr()->as_jint();
+        is_32bit = true;
+        break;
+     case T_LONG:
  imm = opr2->as_constant_ptr()->as_jlong();
  break;
-      case T_INT:
       case T_ADDRESS:
  imm = opr2->as_constant_ptr()->as_jint();
  break;
@@ -2001,14 +2006,14 @@
       }

       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
- if (type2aelembytes(opr1->type()) <= 4)
+ if (is_32bit)
   __ cmpw(reg1, imm);
  else
   __ cmp(reg1, imm);
  return;
       } else {
  __ mov(rscratch1, imm);
- if (type2aelembytes(opr1->type()) <= 4)
+ if (is_32bit)
   __ cmpw(reg1, rscratch1);
  else
   __ cmp(reg1, rscratch1);