[aarch64-port-dev ] jdk1 Fix for hotspot/test/gc/g1/TestJNIWeakG1/TestJNIWeakG1.java

[Stuart Monteith]

Hello,
  I'm not going to be able to upload the patch and webrev today, but
here's my latest attempt. I've backed out passing the temporary
registers and added the comments and asserts. It passes JTreg (with
fastdebug).

Many thanks,
    Stuart

# HG changeset patch
# User smonteith
# Date 1503067917 -3600
#      Fri Aug 18 15:51:57 2017 +0100
# Node ID 47ae436ce6043703d795a8a8438c10581495c841
# Parent  ecc706979abd3e5281e060f195fc729a8770f923
[mq]: add_regs

diff -r ecc706979abd -r 47ae436ce604
src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Wed Aug 16
20:57:00 2017 +0000
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Fri Aug 18
15:51:57 2017 +0100
@@ -3624,6 +3624,13 @@
 }

 #if INCLUDE_ALL_GCS
+
+/*
+ * g1_write_barrier_pre -- G1GC pre-write barrier for store of new_val at
+ * store_addr.
+ *
+ * allocates rscratch1
+ */
 void MacroAssembler::g1_write_barrier_pre(Register obj,
                                           Register pre_val,
                                           Register thread,
@@ -3641,8 +3648,8 @@

   assert(pre_val != noreg, "check this code");

-  if (obj != noreg)
-    assert_different_registers(obj, pre_val, tmp);
+  assert_different_registers(obj, pre_val, tmp, rscratch1);
+  assert(pre_val != noreg &&  tmp != noreg, "expecting a register");

   Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +

SATBMarkQueue::byte_offset_of_active()));
@@ -3716,12 +3723,21 @@
   bind(done);
 }

+/*
+ * g1_write_barrier_post -- G1GC post-write barrier for store of new_val at
+ * store_addr
+ *
+ * allocates rscratch1
+ */
 void MacroAssembler::g1_write_barrier_post(Register store_addr,
                                            Register new_val,
                                            Register thread,
                                            Register tmp,
                                            Register tmp2) {
   assert(thread == rthread, "must be");
+  assert_different_registers(store_addr, new_val, thread, tmp, tmp2,
rscratch1);
+  assert(store_addr != noreg && new_val != noreg && tmp != noreg
+         && tmp2 != noreg, "expecting a register");

   Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +

DirtyCardQueue::byte_offset_of_index()));
diff -r ecc706979abd -r 47ae436ce604
src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp
--- a/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp Wed Aug 16 20:57:00
2017 +0000
+++ b/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp Fri Aug 18 15:51:57
2017 +0100
@@ -2067,7 +2067,7 @@
       __ g1_write_barrier_pre(noreg /* obj */,
                               r0 /* pre_val */,
                               rthread /* thread */,
-                              rscratch1 /* tmp */,
+                              rscratch2 /* tmp */,
                               true /* tosca_live */,
                               true /* expand_call */);
     }
diff -r ecc706979abd -r 47ae436ce604
src/cpu/aarch64/vm/templateTable_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp Wed Aug 16 20:57:00
2017 +0000
+++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp Fri Aug 18 15:51:57
2017 +0100
@@ -170,7 +170,7 @@
           // G1 barrier needs uncompressed oop for region cross check.
           Register new_val = val;
           if (UseCompressedOops) {
-            new_val = rscratch1;
+            new_val = rscratch2;
             __ mov(new_val, val);
           }
           __ store_heap_oop(Address(r3, 0), val);