[aarch64-port-dev ] RFR: 88158361: AArch64: Address calculation missed optimizations
Zhongwei Yao
zhongwei.yao at linaro.org
Fri Jun 23 04:00:01 UTC 2017
Hi, all,
Patch is updated: http://cr.openjdk.java.net/~njian/8158361/webrev.01/
Summary: 22 rules are added. Please refers following table for why some
rule is excluded in this patch. (fixed-width font will make the format
better).
| no. | rule | match code
| Added in | note |
| | |
| this patch? | |
|-----+------------------------+--------------------------------------+-------------+------------------------------------------|
| 1 | AddExtL_uxtb_and_shift | y + ((x & 255) << 3)
| y | |
| 2 | AddExtL_uxth_and_shift | y + ((x & 65535) << 3)
| y | |
| 3 | AddExtL_uxtw_and_shift | y + ((x & 0xFFFFFFFFL) << 3)
| y | |
| 4 | AddExtL_uxtx_and_shift | y + ((x & 0xFFFFFFFFFFFFFFFFL) <<
3) | n | make no sense |
| 5 | SubExtL_uxtb_and_shift | y - ((x & 255) << 3)
| y | |
| 6 | SubExtL_uxth_and_shift | y - ((x & 65535) << 3)
| y | |
| 7 | SubExtL_uxtw_and_shift | y - ((x & 0xFFFFFFFFL) << 3)
| y | |
| 8 | SubExtL_uxtx_and_shift | y - ((x & 0xFFFFFFFFFFFFFFFFL) <<
3) | n | make no sense |
| 9 | AddExtI_uxtb_and_shift | y + ((x & 255) << 1)
| y | |
| 10 | AddExtI_uxth_and_shift | y + ((x & 65535) << 1)
| y | |
| 11 | AddExtI_uxtw_and_shift | y + ((x & 0xFFFFFFFF) << 1)
| n | make no sense |
| 12 | AddExtI_uxtx_and_shift | y + ((x & 0xFFFFFFFFFFFFFFFFL) <<
1) | n | make no sense |
| 13 | SubExtI_uxtb_and_shift | y - ((x & 255) << 1)
| y | |
| 14 | SubExtI_uxth_and_shift | y - ((x & 65535) << 1)
| y | |
| 15 | SubExtI_uxtw_and_shift | y - ((x & 0xFFFFFFFF) << 1)
| n | make no sense |
| 16 | SubExtI_uxtx_and_shift | y - ((x & 0xFFFFFFFFFFFFFFFFL) <<
1) | n | make no sense |
| 17 | AddExtL_sxtb_shift | y + (((x << 56) >> 56) << 3)
| y | |
| 18 | AddExtL_sxth_shift | y + (((x << 48) >> 48) << 3)
| y | |
| 19 | AddExtL_sxtw_shift | y + (((x << 32) >> 32) << 3)
| y | |
| 20 | AddExtL_sxtx_shift | y + (((x << 0) >> 0) << 3)
| n | make no sense |
| 21 | SubExtL_sxtb_shift | y - (((x << 56) >> 56) << 3)
| y | |
| 22 | SubExtL_sxth_shift | y - (((x << 48) >> 48) << 3)
| y | |
| 23 | SubExtL_sxtw_shift | y - (((x << 32) >> 32) << 3)
| y | |
| 24 | SubExtL_sxtx_shift | y - (((x << 0) >> 0) << 3)
| n | make no sense |
| 25 | AddExtI_sxtb_shift | y + (((x << 24) >> 24) << 1)
| y | |
| 26 | AddExtI_sxth_shift | y + (((x << 16) >> 16) << 1)
| y | |
| 27 | AddExtI_sxtw_shift | y + (((x << 0) >> 0) << 1)
| n | make no sense |
| 28 | AddExtI_sxtx_shift | no such match code
| n | make no sense |
| 29 | SubExtI_sxtb_shift | y - (((x << 24) >> 24) << 1)
| y | |
| 30 | SubExtI_sxth_shift | y - (((x << 16) >> 16) << 1)
| y | |
| 31 | SubExtI_sxtw_shift | y - (((x << 0) >> 0) << 1)
| n | make no sense |
| 32 | SubExtI_sxtx_shift | no such match code
| n | make no sense |
| 33 | AddExtL_uxtb_shift | y + (((x << 56) >>> 56) << 4)
| n | same as: y + ((x & 255) << 3) rule 1 |
| | |
| | such convertion is done in earlier stage |
| 34 | AddExtL_uxth_shift | y + (((x << 48) >>> 48) << 4)
| n | similar with rule 33 |
| 35 | AddExtL_uxtw_shift | y + (((x << 32) >>> 32) << 4)
| n | similar with rule 33 |
| 36 | AddExtL_uxtx_shift | y + (((x << 0) >>> 0) << 4)
| n | make no sense |
| 37 | AddExtI_uxtb_shift | y + (((x << 24) >>> 24) << 2)
| n | similar with rule 33 |
| 38 | AddExtI_uxth_shift | y + (((x << 16) >>> 16) << 2)
| n | similar with rule 33 |
| 39 | AddExtI_uxtw_shift | y + (((x << 0) >>> 0) << 2)
| n | make no sense |
| 40 | AddExtI_uxtx_shift | no such match code
| n | make no sense |
| 41 | SubExtL_uxtb_shift | y - (((x << 56) >>> 56) << 4)
| n | similar with rule 33 |
| 42 | SubExtL_uxth_shift | y - (((x << 48) >>> 48) << 4)
| n | similar with rule 33 |
| 43 | SubExtL_uxtw_shift | y - (((x << 32) >>> 32) << 4)
| n | similar with rule 33 |
| 44 | SubExtL_uxtx_shift | y - (((x << 0) >>> 0) << 4)
| n | make no sense |
| 45 | SubExtI_uxtb_shift | y - (((x << 24) >>> 24) << 2)
| n | similar with rule 33 |
| 46 | SubExtI_uxth_shift | y - (((x << 16) >>> 16) << 2)
| n | similar with rule 33 |
| 47 | SubExtI_uxtw_shift | y - (((x << 0) >>> 0) << 2)
| n | make no sense |
| 48 | SubExtI_uxtx_shift | no such match code
| n | make no sense |
| 49 | AddExtI_shift | y + (((long)x) << 2)
| y | |
| 50 | SubExtI_shift | y - (((long)x) << 2)
| y | |
On 19 June 2017 at 18:23, Zhongwei Yao <zhongwei.yao at linaro.org> wrote:
>
>
> On 16 June 2017 at 21:39, Andrew Haley <aph at redhat.com> wrote:
>
>> On 16/06/17 11:35, Zhongwei Yao wrote:
>> > And there are 32 kinds of add/sub extension combination. I have tried to
>> > add 18 rules in aarch64.ad, and found many of them are quite contrived,
>> > like:
>> > subw $dst, $src1, $src2, uxtb, #lshift //match rule: Set dst (SubI
>> > src1 (LShiftI (AndI src2 mask) lshift)), where mask=255. java code: z =
>> x -
>> > ((y & 255) << lshift), where x, y, z are all int, lshift = [0, 4]
>> > addw $dst, $src1, $src2, uxth, #lshift //match rule: Set dst (AddI
>> > src1 (LShiftI (AndI src2 mask) lshift)), where mask=65535. java code: z
>> = x
>> > + ((y & 65535) << lshift), where x, y, z are all int, lshift = [0, 4]
>> >
>> > Shall I add all of these 18 rules?
>>
>> I would not want you to do anything you feel does not make sense. Please
>> add
>> the nodes that seem reasonable and that can be tested in code that C2
>> generates.
>>
>
> I see. I will add most of the combinations except instructions like: add
> x0, x1, x2, uxtx, # 1, which is replaced by add x0, x1, x2, lsl, #1.
>
>
>> > And for the left 14 combination (as following), I have not come up
>> rules to
>> > utilise such instructions. Do you have any suggestion?
>> > add SXTB (simplified for add rd, rm, rn, sxtb, #[0,4], same for
>> below)
>>
>> Sign extension is modelled as Shift Left followed by Shift Right.
>> SXTB is (RShiftL (LShiftL src 56) 56). You can figure out the rest from
>> that.
>>
>
> Thanks for your suggestions!
>
>
>> --
>> Andrew Haley
>> Java Platform Lead Engineer
>> Red Hat UK Ltd. <https://www.redhat.com>
>> EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671
>>
>
>
>
> --
> Best regards,
> Zhongwei
>
--
Best regards,
Zhongwei
More information about the aarch64-port-dev
mailing list