[aarch64-port-dev ] ZeroTLAB and block zeroing

[Stuart Monteith]

On 26 October 2017 at 12:16, Andrew Haley <aph at redhat.com> wrote:

> On 26/10/17 11:53, Stuart Monteith wrote:
> > The ARM ARM is quite explicit in the expectations for the behaviour of
> the
> > DC ZVA instruction. It should be considered as behaving as a series of
> > ordinary stores:
> >
> > D3.4.9 Data cache zero instruction
> >> The DC ZVA instruction behaves as a set of stores to the location being
> >> accessed, and:
> >> • Generates a Permission fault if the translation regime being used when
> >> the instruction is executed does not permit writes to the locations.
> >> • Requires the same considerations for ordering and the management of
> >> coherency as any other store instruction.
>
> Good.
>
> > In fact, it is stated as being different from most other cache
> operations.
> > Cache maintenance instructions should execute in program order relative
> to
> > once another, /except/ for DC ZVA.
>
> OK, no problem.
>
> How does this answer the question?
>
>
Just reinforcing your point. I see no justification for memory barriers in
this circumstances except for where they stand in relation to other cache
operations. If the barriers were preventing issues, then it's not clear why.


> --
> Andrew Haley
> Java Platform Lead Engineer
> Red Hat UK Ltd. <https://www.redhat.com>
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>