[aarch64-port-dev ] RFC: 64 bit literal oops

[Andrew Haley]

On 12/3/18 4:53 PM, Stuart Monteith wrote:

> There is another possible option, which is to just avoid 48-bit
> literals, and just use 64-bit unconditionally everywhere. It would
> mean that we could be easily consistent and 52-bit VA would be easier
> to implement on top of it. Again, I seek people's opinions.

Could well be. I am starting to wonder if it is worth the effort.
Maybe the best thing to do is have a global 48- to 64-bit switch
and use it everywhere we want a pointer literal.

Please don't put code of any complexity into header files. Put it
into .c files instead.

The logic in MacroAssembler::movoop is a already a mess, and
adding an isOop flag to pass to doesn't help. I think it would
make more sense to have explicit 48- and 64-bit mov methods, and
let MacroAssembler::mov(Register, Address) control which one is
called.

This hunk makes no sense. The comment directly contradicts
the code:

  enum Aarch64_specific_constants {
    instruction_size            =    3 * 4, // movz, movk, movk, [movk].  See movptr().
    instruction_offset          =    0,
    displacement_offset         =    0,
  };

It makes no sense to have instruction_size be a constant here.
I guess it never did.

-- 
Andrew Haley
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
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